Project Report

On

Investigation Performance of Double Gate-

Junctionless FET with Graded Doping
Submitted in the partial fulfillment of the requirement for of the award of degree of

Bachelor of Technology
In
Electronics & Communication Engineering
For the session
2018-2019

Submitted by

Md Asjad 1550131008
Sachin kumar 1550131010
Shalini Verma 1550131006
Sumit Maheshwari 1550131011

Under the Guidance of

Mr. Ankit Saini

R V INSTITUTE OF TECHNOLOGY
9 km.Milestone, Bijnor-Moradabad Road, Bijnor (U.P) INDIA

i
 2019

Investigation Performance of DG-JLFET With

Graded Doping Profile
By
MD ASJAD (1550131008)
SACHIN KUMAR (1550131010)
SHALINI VERMA (15550131006)
SUMIT MAHESHWARI (1550131011)

DEPARTMENT OF ELECTRONICS &

COMMUNICATION ENGINEERING

RV INSTITUTE OF TEHNOLOGY, BIJNOR

Submitted to Submitted by
Project Guide Md Asjad
Er.Ankit Saini Sachin kumar
(Assistant professor) Shalini Verma
Sumit Maheshwari

Electronics & Communication Engineering

R V Institute of Technology

ii
 Certificate

This is Certified that this project entitled “Investigation Performance of DG-

JLFET With Graded Doping Profile” submitted by Sachin Kumar
(1550131010), Md Asjad (1550131008), Shalini Verma (1550131006), Sumit
Maheshwari (1550131011) students of Electronics & Communication, R V
INSTITUTE OF TECHNOLOGY, BIJNOR in the partial fulfillment of the
requirement for the award of Bachelors of Technology (Electronics &
Communication) Degree of AKTU, is a Bona-fide record of students own study
carried under my supervision & guidance.

This report has not been submitted to any other university or institution for the
award of any degree.

Project Guide External Examination Head of Department

Mr. Ankit Saini Er. Sayad Tathir Abbas Naqvi
Assistant Professor Head of Department
ECE Department (ECE)

iii
 Acknowledgement

With Immense please we present the project report as part of the curriculum of the
final year in “BRANCH NAME”. We wish to give a special thanks to our H.O.D
Er. Sayad Tathir Abbas Naqvi Sir who gave us an unending support right from
the idea was conceived.

We also express our sincere and profound thanks to our Project Guide
Mr. Ankit Saini sir who always stood by us as helping and guiding support. We
are also thankful to all the staff members who always gave us a helping hand and
showed immense faith in us whenever required.

At last thanks to our Director sir who has organized so well and disciplined
college and gave us a chance to show our potentials and made us the memories of
this college by allowing us to complete this project. Thanks to ALL…

1. Md Asjad
2. Sachin Kumar
3. Shalini Verma
4. Sumit Maheshwari

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 ABSTRACT
As the CMOS scaling continues to shrink feature sizes, many efforts have been
directed toward reducing short-channel effects by employing structures that
impose greater control on the channel. As an alternative, multi-gate devices have
been developed due to the better electrostatic control of the charges, which leads
to a reduction of short-channel effects. Further scaling of these devices, however,
seems to be limited by the formation of an abrupt S/D junction that abruptly
change from a heavily-doped n-type (p-type) to an undoped or lightly-doped p-
type (n-type) within a few nanometers. A junctionless metal-oxide semiconductor
field-effect transistor (JL MOSFET) that has the same doping profile in the
silicon body region from the source to the drain has been proposed to overcome
this difficulty.

This paper compares the characteristics of uniform and Graded Channel

structures of junctionless MOSFETs.

Keyword: Double-Gate (DG-JL-MOSFET), Hot-Carrier Effects (HCEs),

Short-Channel Effects (SCEs), Graded doping

v
 DECLEARATION

We hereby declare that the project entitled “Investigation Performance of DG-

JLFET With Graded Doping Profile” towards the partial fulfillment for the
award of BACHELOR OF TECHNOLOGY in Electronic And Communication
Engineering submitted in the department of RVIT, BIJNOR (U.P) is an authentic
record of our work carried out under the kind guidance of Mr.Ankit saini.

Name- Md Asjad Name- Sachin Kumar

Roll no. – 1550131008 Roll no.-1550131010
Date – Date –
Signature- Signature-
Name- Shalini Verma Name – Sumit Maheshwari
Roll no.-1550131006 Roll no.-1550131011
Date – Date -
Signature- Signature –

vi
 TABLE OF CONTENTS

CONTENTS PAGE NO.

Certificate………………………………………..………………………….i

Acknowledgement………………………………………………….………ii

Abstract……………………………………………………………. ………iii

Declaration………………………………………………………….……….iv

Table of Contents…………………………………………………………….v
.
CHAPTER 1………………………………………………1
1. Introduction……………………………………………………………….1
1.1 Conventional MOSFET…………………………………………….1
1.2 Short Channel Effects in a scaled transistor………………………..4
1.2.1 Sub-threshold swing…………………………………………4
1.2.2 Drain Induced Barrier Lowering (DIBL)…………….……..5
1.2.3 Velocity saturation…………………………………….……..6
1.2.4 Gate oxide leakage………………………………………..….6
1.2.5 Gate Induced Drain Leakage (GIDL)…………………..…….7
1.2.6 Hot Carrier effects…………………………………………....7
1.3 Junction-Less Transistor (JLT)…………………………………..….8
1.3.1 Theory of junctionless Transistor………………………….....9
CHAPTER 2……………………………………………...10
2. Literature Review………………………………………………………...10

vii
CHAPTER 3……………………………………………..16
3. Material and Methods……………………………………………………16
3.1 SILVACO TCAD…………………………………………………16
3.2 Device Simulation Framework……………………………………18
3.3 Visualization Tool…………………………………………………20
CHAPTER 4………………………………………………21
4. Proposed Objective and Methodology……………………………………21
4.1 Objective…………………………………………………………...22
4.2 Methodology…………………………………………………….…23
CHAPTER 5…………………………………………….....26
5. Simulation………………………………………………………………….26

6. Result and Discussion…………………………………………………...…28

7. Conclusion………………………………………………………………….37

8. Future Scope……………………………………………………………..…38

References…………………………………………………………………….39

APPENDIX A
APPENDIX B

viii
 LIST OF FIGURES
S.NO. TITLE PAGE NO.
1

ix
CHAPTER 1

1.INTRODUCTION
Complementary metal oxide semiconductor (CMOS) technology revolutionized the
human life style for more than four decades. It would have been hard to think of life
today without silicon CMOS technology. The CMOS technology had advanced with a
double the number of on-chip transistors every generation, reducing the physical device
size. A smaller sized transistor comes with an advantage of improved performance and
packing density. This is referred as scaling and had enabled the Moore’s law to happen.
Continued scaling of CMOS technology has now reached to the atomic scale
dimensions, in order to serve the next generation low standby power (LSP), low
operating power (LOP) and high performance (HP) requirements. While the often
referred short channel effects (SCEs) like drain induced barrier lowering (DIBL), gate
induced drain leakage (GIDL), gate tunneling leakages and leakage current problems
are challenging on one side, realizing the transistor for the next generations itself have
become a much more challenging task. This is because of the ultra-steep doping profile
requirements at the source-drain junctions.

1.1. Conventional MOSFET

Metal oxide semiconductor field effect transistor (MOSFET) is a four terminal

semiconductor device. The schematic of this device is shown in Fig. 1.1. It has five
regions viz., source, drain, channel, gate and gate dielectric. The source and drain
regions are doped with an impurity that is complementary to that of the channel. For
example, in an n-channel MOSFET, the source and drain regions are doped with n-type
impurity and the channel is p- type doped. Usually, in the traditional MOSFET, the
work function of the gate material is similar to that of the source/drain regions. For n-
channel operation the drain is biased at a higher potential with respect to the source.
When no bias is applied to the gate terminal, the current between source and drain is
very small due to the high potential barrier for electrons

1
 Figure 1.1: Electron concentration profile above threshold in IM, AM and
JNT devices. Surface channels are formed in IM and AM device, while
conduction takes place in the bulk of the nanowire in the JNT.

between source and channel-this is called the OFF state of the transistor. When a
positive bias is applied on the gate terminal, the minority carriers in the substrate gets
attracted towards the channel surface due to the electric field developed across the
gate dielectric (hence, the field effect). The accumulation of minority carriers in the
channel, inverts the type of free carriers available near the surface of the channel.
Hence, this state is called inversion.

Figure 1.2: Current in inversion-mode (a), accumulation-mode (b) and

junctionless (c) nanowire MuGFETs. Note the very different positions of the
flatband voltage, VFB.

The inverted channel acts as a conducting layer between the source and drain. Hence a
high current starts to flow between the source and drain-this is called the ON state of the
transistor. The ON and OFF states described here together makes the MOSFET to act as
2
a switch. The ideal switching behavior one would like to have is shown in Fig. 1.2.
When the voltage applied at the control gate is less than some pre-defined threshold
voltage (VT )
, the switch should be OFF, i.e., the current should be zero and once the
control gate voltage is above VT, the device should be ON with a finite amount of
current (indicated as ION), between source and drain.

Figure 1.3: Electron concentration contour plots in an n-type junctionless

transistor. A: VD = 50mV; B: VD = 200mV; C: VD = 400mV; D: VD = 600mV.
VG>VTH.

However, the MOSFET can not achieve an ideal switching behaviour. The current
versus voltage transfer characteristics of MOSFET looks like shown in Fig. 1.3.
Normally for n- channel operation the gate is operated in the positive voltage regime.
The region of gate to source voltages (VGS) between 0V and VT is called the
subthreshold region where the current increases exponentially with gate voltage. The
above-threshold region is for gate voltage greater than VT. Depending on the bias
applied to the drain, the MOSFET is said to operate in
either saturation region (for high drain to source voltage) or in linear region (f or a
low drain to source voltage). For a very low or negative bias at the gate, the current
tends to increase due to an affect called as gate induced drain leakage (GIDL), which
will be explained in detail in subsequent sections

3
 1.2. Short channel effects in a scaled transistor
In Fig. 1.4 shows the typical ID versus VGS characteristics of short and long channel
devices. It can be clearly observed that the OFF current increases drastically in a short
channel device. Along with this, lowering of V T, large VT variation with drain bias,
reduced slope of transfer characteristics in the sub-threshold region, etc., are
observed in short channel devices compared to a long channel device. All
of these are extremely undesirable factors, collectively known as short channel
effects and need to be addressed. We explain in details each of the short channel effects
below.

Figure 1.4: Schematic of an n-channel nanowire transistor

1.2.1 Sub-threshold swing

Sub-threshold swing (SS) is defined as the variation in the gate voltage required to
have a decade variation in current. For a MOSFET this is given by the following
equation

where, T is the temperature in degrees Kelvin, q is the charge of electron, C D is the

depletion capacitance, Cox is the gate oxide capacitance. Even if we neglect the second
term as it is far less than 1 (i.e., when Cox $CD), SS is limited by the first term to 60
mV/Decade. Higher SS means that the device can have a fewer orders of change in

6
drain current from the OFF state to the VT, which in turn means a higher OFF current
for a given VT.

1.2.2 Drain Induced Barrier Lowering (DIBL)

Ideally, we need to operate the MOSFET in 1-D mode, i.e., only gate voltage
controlling the current of the device. But, as the channel lengths are going small, the
drain starts to behave as a second gate, i.e., ID is not only controlled by the gate
voltage but is also controlled by the drain voltage. This is called as the 2-D behavior of
the transistor. In a long channel device any increase in VDS is accounted by lowering
the band only in the drain side. As the channel length is decreased this increase in VDS
account in lowering the source to channel barrier (which should be actually controlled
by the gate). Where only the conduction band edge is shown along the source-channel-
drain for 32nm and 250nm gate length devices. It can be observed that the source-
channel barrier is lowered significantly for a 32nm device compared to a 250nm
MOSFET. Effect of DIBL is noticed in the transfer characteristics as a decrease in
threshold voltage. This also results in the non-saturation behavior of the transistor (ID
keeps on increasing with VDS). Low VT again leads to an increase of OFF current.
However there will be an increase in ON current of the transistor, but the increase in
ON current is not as high as the increase in OFF current, hence degrading the ON/OFF
current ratio of the device. There are several ways to address DIBL like (a) Increase the
gate control by decreasing the oxide thickness, which in turn increases the direct
tunneling current through the gate oxide. and (b) By increasing the substrate doping,
region widths. (c) By using a different material which has a lower dielectric
constant instead of Si, so that the drain coupling to the source is reduced.

Figure 1.5:Drain Induced Barrier Lowering

7
2.3. Velocity saturation
The velocity of carriers is known to saturate due to mobility saturation at higher electric
fields. A constant field scaling (i.e., scaling all parameters equally) would have been
helpful to maintain the same electric fields in the scaled down transistor. However, the
scaling trend followed by semiconductor industries is not a constant field one. For
example, oxide thickness is scaled more and supply voltages are scaled less. This had
resulted in an increased electric fields in the nano-scale MOSFET. As electric field
increases the velocity gets saturated. This would not have been be a problem if the
saturation occurs at drain voltages greater than the gate overdrive. But, in a nano-scale
MOSFET, this is observed at lower drain voltages itself, resulting in a decreased ON
current (as the current is saturating earlier). We can easily identify weather the
saturation is due to velocity saturation or due to V DS, from the ID-VDS characteristics. If
there are equal increments of current for equal increments of gate overdrive then the
saturation is due to velocity saturation, whereas if there is a square dependency of ID on
overdrive then it is due to increase in VDS above the gate overdrive.

Figure 1.6: Cross-sectional TEM image and ID - VGS plot of 50nm channel
length tri-gate JLT fabricated by Colinge et al.

1.2.4 Gate oxide leakage

SiO2 is a good insulator to be used in the MOS structure. But, when gate oxide thickness
is reduced less than 3nm or 2nm, tunneling probability increases and result in an
increase of the oxide leakage current. Using a high-k dielectric is used to solve this
problem to some extent, as a high-k dielectric can provide a similar gate electric
field even with a physically thick high-k gate dielectric. This can reduce the direct
tunneling leakage.

8
1.2.5 Gate Induced Drain Leakage (GIDL)
Scaling results in an increase of field in oxide as well as in the gate-drain overlap
region. For a high drain bias and a low gate bias, the electric field in the gate/drain
overlap region is very high. This increase in the field actually depletes the carriers in the
drain overlap region of the band diagram in the vertical direction in the gate/drain
overlap region. It can be seen that there is a significant band overlap between the
valance band of the drain to the conduction band of the drain in the overlap region.
This band overlap triggers band-to-band tunneling between the valance band and
conduction band of the drain. The electron and hole pair generated due to band to band
tunneling will be swept to the drain and substrate respectively.

Figure 1.7: (a) - (b) Schematic representation of JLT and BPJLT with spacers

1.2.6 Hot carrier effects

After fabricating a certain device there should not be a drift in performance of the device
over time. But hot carrier effect leads to the drift over certain period of operation. This is
more dominant in short channel devices where the electric field is higher. The three
kinds of possible hot carrier injection mechanisms are illustrated in (a) Carriers
generated due to impact ionization on the drain side can multiply and can lead to a
heavy substrate current. (b) the carriers having energy higher than the silicon/gate
dielectric conduction band offset can lead to a conduction current to the gate. (c)
The sufficiently high energy electrons can damage the silicon-gate dielectric interface
leading to degradation in important device parameters like drain current, threshold
voltage etc.

9
 Fig 1.8: A hot electron manages to enter the oxide and gets trapped in it.

Impact ionization
As mentioned earlier, short-channel transistors create strong lateral electric fields,
since the distance between source and drain is very small. This electric field endows
the charge carriers with high velocity, and therefore, high energy. The carriers that
have high enough energy to cause troubles are called "hot" carriers. These normally
appear close to the drain, where they have the most energy.
Since they are travelling through a Silicon lattice, there is a possibility that they collide
with an atom of the structure. Given enough energy, the energy passed to the atom
upon collision can knock out an electron out of the valence band to the conduction
band. This originates an electron-hole pair: the hole is attracted to the bulk while the
generated electron moves
on to the drain. The substrate current is a good way to measure the impact
ionization effect.

10
 1.3Junction-Less Transistor (JLT)

Some of the process challenges for scaling the CMOS devices can be reduced by a
device which does not need any junctions and this is the main advantage of junctionless
transistor. Unlike the conventional MOSFET, JLTs have heavy channel doping and is
fully depleted in the OFF state. For this purpose, a gate metal which has a large work
function difference to that of the channel is needed. Gate bias need to be applied to
bring the channel out-of depletion and to see conduction between source and drain. As
there is a single semiconducting silicon bar with uniform doping from the source to
channel, it can be modeled as a resistor whose resistance can by modulated by the gate.
However, for a reasonable conductance between source and drain, the doping of the
semi-conductor bar need to be very high. On the other hand, the depletion width in a
heavily doped semiconductor is very small and this demands an ultra thin silicon body
for a JLT.

1.3.1 Theory of junctionless transistors

The schematic representation of junctionless transistor is shown in Fig. 1.4. It can be

seen that for an n-channel operation, the source, channel and drain are of n-type
doping and the gate is of a p-type work function (~5.2 eV). Since the work function
difference between the n- type channel and the p-type gate is of ~1eV, there is depletion
in the channel, where the depletion is decided by the doping of the channel region (thin
depletion width for high doping and vice-versa). Channel can be made fully depleted by
choosing an extremely thin channel and low channel doping in the range of 10nm and
1019 respectively. Once the channel is fully depleted, the current between the source and
drain becomes very small. As shown in the IDVDS characteristics in the current is very
small when the gate is at 0V. Also, it can be seen in the band diagram for VGS =0V, that
there exists a barrier between the source and the channel due to depletion of carriers in
the channel. There exists a similar barrier between the source and channel, even in the
conventional MOSFET. Once a positive gate bias is applied (note this is for an n-channel
operation), the channel is now brought out of depletion and the barrier between the
source and channel is reduced. This result in a high drain current for a non-zero drain
bias. When voltage applied at the gate is approximately equal to the work function
difference between the gate and channel, the device is brought into the flat- band
condition and the transistor is said to be turned ON.

11
 Figure 1.8: Schematic of an SOI junctionless transistor
However, all this is valid when the channel thickness is less than its depletion width, else,
the device will not be turn OFF at zero gate bias. For example, if the depletion width
calculated is 10nm and the channel thickness is 20nm, the device will conduct due to the
drain to source bias, even for a zero gate bias, i.e., the device can not be turned OFF.
CHAPTER 2

2.LITERATURE REVIEW
In order to understand the evolution of integrated electronics and its developments in
present day, it is first essential to understand the basic concepts of MOSFET, its
history that led to the development of MOSFETs. The basic functionality of MOSFET,
its different region of operation and qualitative approach of the device is studied. These
paper discusses about the various characteristics of the device plotted between device
current and various voltages of the device in linear and logarithmic scale. The
capacitance generated between different device region and their effects is studied [1].
Proper understanding of the device gave us the idea of integrating these devices on the
single wafer there by increasing the integrity. This helps in reducing the area required
for transistors in the chip doubles every 24 months but after a certain time, it is proved
practically that it doubles every 18 months[2].
Basically the idea of integrating the large no of devices on the single chip leads to the
idea of scaling. Scaling is the process of reducing the dimensions, supply voltage and
other parameters in order to increase the integrity of the device. Scaling is done on
various parameters. The scaling on various parameter leads different type of scaling [3]
[4].
Scaling of the device leads to the reduction the dimension of the device thereby
reducing the channel length, width and other parameters of the device. This reduction of
parameters lead to the short channel effects which are studied [6]. These effect the
performance and reliability of the device and they give the undesired results. The
prominent short channel effect is leakage current. It is the current that flows in the
device in the weak inversion region [8]. These leakage currents arrive due to different
mechanism which needs to be studied so that their reduction technique can be studied.

There are various reduction technique used to compensate these leakage current in
conventional bulk MOSFET [12]. These reduction techniques can be classified on the
basis of use of new materials, well engineering and circuit reduction techniques [13]. In
order to solve the problem, a new architecture is to be introduced where the architecture
of the device is changed from the simple bulk MOSFET.

The new architectural devices have slight fabrication changes than that of the bulk
MOSFET. These devices are Silicon on Insulator, Double Gate and multiple Gate FET
structures . A brief study of these devices is being done to have an overview of these
devices, their functionality, their operation, and their advantages over the conventional
bulk MOSFET. These devices help in reducing the short channel effects of the bulk
MOSFET. SOI improves the short channel effects by the removal of the body terminal
of the bulk MOSFET, instead it has a buried oxide layer (BOX). Removal of the body
12
reduces most of the leakage mechanisms such as DIBL, GIDL, drain to body leakage
current et.al. SOI is basically categorized as Partially Depleted SOI (PD SOI) and Fully
Depleted (FD SOI). The categorization of these SOIs is done on the basis of the
thickness of the silicon layer compared to that of the depletion layer thickness. PD
SOI has a small body region which may act as a floating terminal if not grounded.
This floating body terminal gives rise to kink effect which deviates the current
mechanism from its intended characteristic behavior. These kink effect is absent in FD
SOI due to the absence of the body terminal [14][15].The further modification of the
SOI gives rise to Double Gate MOSFET having two gates one front gate and one back
gate. Due to the presence of the two gates it provides better controllability of the gate
voltage over the threshold voltage (Vt). Thus increasing the number of gate terminals
around the channel increases the gate controllability over V t. This concept gives rise to
the idea behind Multiple Gate FET structures and FIN-FETs .The short channel effects
are present in great extent in these devices
Therefore, to reduce the short channel effects, a new device is introduced called
Junctionless (JL) Transistors .This device having the uniform doping along the whole
channel region and source/drain region to overcome the challenges face by the
conventional nano devices. These device have low leakage current and simple
fabrication process as compared to conventional bulk MOSFET [16] . But due to high
doping concentration in the channel, it causes decrease in carrier mobility which
results in low current and transconductance of JL MOSFETs. Now, in JL MOSFET as
we reach the high gate voltage, there is a reduction in drain current in saturation region.
This occurs because as we have S/D implantation, it reduces the series resistance but at
the same time, increases parasitic capacitance thereby causing a delay in a circuit. This
problem can be solved by using JL MOSFET with source/ drain junction having non-
uniform doping and also using JL MOSFET transistors without the S/D extensions.

Junctionless MOSFET

1) WuMeile, JinXiaoshi , ChuaiRongyan, LiuXi, and Jong-HoLee[16] : In this

paper, author describes the characteristics of Short Channel Double-Gate(DG)
Junctionless(JL) FETs by device simulation. Threshold voltage and sub-threshold slope
variation due to variations of body doping, body thickness and channel length are
analyzed. As we decrease the channel length for both devices, there is a decrease in
threshold voltage of both devices but the change in Vt for JL MOSFET is less as
compared to IM MOSFET which lead to the conclusion that smaller channel has lesser
impact on JL MOSFET as compared to IM MOSFET. Sub-threshold slope is used to
define the speed of the device to open. Smaller will be the value of the SS, fast the
device open. With decrease in channel length, SS increases. Smaller channel length has
less impact on SS of JL MOSFET as compared to IM MOSFET. The threshold voltage
of IM MOSFET is larger as compared to JL MOSFET because in JL MOSFET, there is
require majority carriers to form the channel but in the case of IM MOSFET, the
inversion layer formed is made of minority carriers, due to which more the doping
concentration, more the voltage is required to deplete the carriers in order to form the
13
inversion layer. With increase in drain voltage, SSs of the device increases but influence
of SS of VDS is smaller in JL MOSFET as compared to IM MOSFET. Conclusion
obtain from these variation leads to more advantage of Junction-less MOSFET as
compared to conventional MOSFET because the impact of channel length and V DS on
JL FETs is small as compared to conventional FETs.

2) Mukta Singh Parihar and Abhinav Kranti[17] : In this paper, author discusses the
demand of higher channel doping(>1019 cm-3) in Junction-less(JL) double gate
MOSFETs. It is shown that moderately doped(10 18cm-3) ultra low power(ULP) JL
transistors achieve better as compared to heavily doped devices.
In moderately doped devices, the carriers are spread out across the entire film but in
heavily doped devices, it is concentrated at the centre of the film. This increases the
controllability of the gate in order to have high on-off current ratio and lower delay for
sub-threshold logic applications. It also reduces the threshold voltage sensitivity to
change in parameters of the devices. For the depletion of the channel, the gate work
function requirement is reduced to below 5eV.

3) Elena Gnani, Antonio Gnudi, Susanna Reggiani, and Giorgio Baccarani[18]: In

this paper, the electrical properties of junction-less(JL) MOSFETs are modeled. The
motivation related to analytical model proposed to provide physical understanding of
device behavior. In this work, authors describes the device with ideal sub-threshold
slope and excellent on- current while having a lesser electron mobility due to the
impurity scattering. The most important limitations of JL MOSFETs are device
variability and parasitic source/drain resistances. The ideal sub-threshold slope, small
DIBL and large electron mobility together with the simplified manufacturing process
makes the junctionless MOSFETs as the possible candidate for the future technology.
On the other hand, the value of impurity concentration cannot increase above 3x1018 cm-
3
in order to have proper threshold voltages and good contact resistance.

4) Thomas Holtij, Mike Schwarz, Alexander Kloes and Benjamın Inıguez [19]: In
this work, a two dimensional model is described in order to calculate potential in the
junction-less MOSFETs valid in sub-threshold region. The comparison with 2D TCAD
simulation found to be in accuracy with the 2D model. It is proved that threshold
voltage is heavily affected by channel length and applied drain voltages. The threshold
voltages also decrease if the doping concentration is above 1x10 19cm-3. Also decreasing
the channel length effect the DIBL more as compared to increasing the doping
concentration.

5) Mukta Singh Parihar, Dipankar Ghosh, and Abhinav Kranti [20]: In this work,
double gate junction-less MOSFETs is liken with underlap DG MOSFETs for ULP
(Ultra low power) applications. JL devices exhibit least reactivity to gate length as
compared to inversion mode and underlap MOSFETs. The performance of the device
depends on film thickness, gate oxide thickness, and doping .JL MOSFETs shows least

14
sensitivity to gate length so they can be useful for ULP sub-threshold operation.

6) Chi-Woo Lee, Adrien Borne, Isabelle Ferain, Aryan Afzalian, Ran Yan, Nima
Dehdashti Akhavan, Pedram Razavi, and Jean-Pierre Colinge [21]: The authors
discuss the temperature dependence of main electrical parameters of junction-less
MOSFETs. The threshold voltage and on-off current variation is analyzed. The JL
MOSFETs have large variation of temperature as compared to inversion and
accumulation mode MOSFETs. The drain current of JL MOSFETs increase as
temperature is increases.

7) Ming-Hung Han, Chun-Yen Chang, Hung-Bin Chen, Jia-Jiun Wu, Ya-Chi

Cheng, and Yung-Chun Wu [22]: The characteristics and design of bulk JL MOSFETs
is compared with SOI JL MOSFETs. The bulk MOSFETs exhibits a good on-off current
ratio and better short channel characteristics by reducing the channel thickness. It is less
sensitive to channel thickness as compared to SOI MOSFETs. The threshold voltage of
bulk MOSFETs can easily be varied by substrate doping concerned.

15
Review of Double Gate Junction-less (DG JL) MOSFET

The scaling of channel length is a difficult process as short channel effect and leakage current
increases due to less control of gate over channel. In MuGFET, the gate electrode wrapped
along the silicon film forming the multi-gate structure having better control of the channel
providing full depletion of the channel. The formation of source and drain junctions in short
channel devices provide a quite a tough challenges and it points out the condition on doping
techniques and thermal budget. The JL is basically a resistor with uniform doping. It has the
constant doping from source to drain[16].

Gaps in Literature Survey

From the literature review it has been observed that the field of “MOSFET Devices” has been
emerging a lot in the past many decades. The bulk MOSFET ruled the industry for many
decades until it became difficult to scale the device to the nanometer regime in order to follow
Moore’s law and obtain high performance and low voltage characteristics due to prevailing
short channel effects and limitations of scaling.To overcome these problems many techniques
were designed to reduce the leakage currents. New device structures or advance MOSFETs
have been designed such as SOIs to have an advantage over these problems of bulk MOSFETs
in terms of short channel effects and scalability issues. Recent developments have been made
to develop devices having better gate controllability in short channels such as DOUBLE
GATE MOSFETs, GATE ALL AROUND MOSFETs, and FINFETs.
Therefore, to reduce the short channel effects, a new device is introduced called Junctionless
(JL) Transistors .This device having the uniform doping along the whole channel region and
source/drain region to overcome the challenges face by the conventional nano devices. These
devices have low leakage current and simple fabrication process as compared to conventional
bulk MOSFET. But due to high doping concentration in the channel, it causes decrease in
carrier mobility which results in low current and transconductance of JL MOSFETs.

CHAPTER 3
 3.METHODS AND MATERIALS

3.1. SILVACO TCAD

Atlas is a physically-based two and three dimensional device simulator. It predicts the
electrical behavior of specified semiconductor structures and provides insight into the
internal physical mechanisms associated with device operation. Atlas can be used
standalone or as a core tool in Silvaco’s Virtual Wafer Fab simulation environment. In
the sequence of predicting the impact of process variables on circuit performance,
device simulation fits between process simulation and SPICE model extraction.
Atlas is a physically-based device simulator. Physically-based device simulation is not
a familiar concept for all engineers. This section will briefly describe this type of
simulation. Physically-based device simulators predict the electrical characteristics that
are associated with specified physical structures and bias conditions. This is achieved
by approximating the operation of a device onto a two or three dimensional grid,
consisting of a number of grid points called nodes. By applying a set of differential
equations, derived from Maxwell’s laws, onto this grid you can simulate the transport of
carriers through a structure. This means that the electrical performance of a device can
now be modeled in DC, AC or transient modes of operation.

There are three physically-based simulations. These are:

1. It is predictive.
2. It provides insight.
3. It conveniently captures and visualizes theoretical knowledge.

Physically-based simulation is different from empirical modeling. The goal of empirical

modeling is to obtain analytic formulae that approximate existing data with good
accuracy and minimum complexity. Empirical models provide efficient approximation
and interpolation. They do not provide insight, or predictive capabilities, or
encapsulation of theoretical knowledge.
Physically-based simulation has become very important for two reasons. One, it is
almost always much quicker and cheaper than performing experiments. Two, it provides
information that is difficult or impossible to measure. The drawbacks of physically-
based simulation are that all the relevant physics must be incorporated into a simulator.
Also, numerical procedures must be implemented to solve the associated equations.
These tasks have been taken care of for Atlas users.

Those who use physically-based device simulation tools must specify the problem to
be simulated. In Atlas, specify device simulation problems by defining:
1. The physical structure to be simulated.
2. The physical models to be used.
3. The bias conditions for which electrical characteristics are to be simulated.
3.2 Device Simulation Framework

ATLAS

Atlas is best used with the VWF Interactive Tools. DeckBuild provides an interactive
run time environment. TonyPlot supplies scientific visualization capabilities. DevEdit
is an interactive tool for structure and mesh specification and refinement. MaskViews
is an IC Layout Editor. The Optimizer supports black box optimization across
multiple simulators.
Atlas, however, is often used with the Athena process simulator. Athena predicts the
physical structures that result from processing steps. The resulting physical structures
are used as input by Atlas, which then predicts the electrical characteristics
associated with specified bias
conditions. The combination of Athena and Atlas makes it possible to determine the
impact of process parameters on device characteristics.

The electrical characteristics predicted by Atlas can be used as input by the Utmost
device characterization and SPICE modeling software. Compact models based on
simulated device characteristics can then be supplied to circuit
designers for preliminary circuit design.Combining Athena, Atlas,
Utmost, and SmartSpice makes it possible to predict the impact of process parameters
on circuit characteristics.

Atlas can also be used as one of the simulators within the VWF Automation Tools.
VWF makes it convenient to perform highly automated simulation-based
experimentation. VWF is used in a way that reflects experimental research and
development procedures using split lot.
It therefore links very closely to technology resulting in simulaton development,
significantly increased benefits from simulation use.
Figure 3.1 Atlas Inputs and Outputs
3.3Visualization

Tool TONYPLOT

Atlas is best used with the VWF Interactive Tools. These include DeckBuild, TonyPlot,
DevEdit, MaskViews, and Optimizer. DeckBuild provides an interactive run time
environment. TonyPlot supplies scientific visualization capabilities. DevEdit is an
interactive tool for structure and mesh specification and refinement. MaskViews is an
IC Layout Editor. The Optimizer supports black box optimization across multiple
simulators the first input file is a text file that contains commands for Atlas to execute.
The second input file is a structure file that defines the structure that will be simulated.
Atlas produces three types of output files. The first type of output file is the run-time
output, which gives you the progress and the error and warning messages as the
simulation proceeds.

Figure 3.2 Tonyplot of silvaco TCAD

The second type of output file is the log file, which stores all terminal voltages and
currents from the device analysis. The third type of output file is the solution file, which
stores 2D and 3D data relating to the values of solution variables within the device at a
given bias point.
CHAPTER 4

4. PROPOSED OBJECTIVE AND METHODOLOGY

RESEARCH GAP

Why we are designing a junctionless devices?

1. Till now by changing the doping profile (Graded) and structure of a device, we
improve the device parameters.
2. To further improve the device performance and to reduce SCEs, the Uniform
doping profile is used in channel region.

AIMS & OBJECTIVES

Aim : Designing a Graded-Channel Double-Gate

Junctionless MOSFETs Using Si

Fig 4.1 DG-JL-MOSFET simulated in silvaco Atlas

 4.1 OBJECTIVES

1. Designing of DG-JLMOSFET in SILVACO software.

2. Analyze the digital characteristics and SCEs for Fully Depleted SOI
JLMOSFET (Threshold Voltage, DIBL, Subthreshold Slope and Subthreshold
Current).

3. Comparison of Graded Doping DG JLMOSFET and Uniform Doping DG-

JLMOSFET.

Work Flow:

Fig 4.2: WorkFlow of Silvaco Software

4.2 METHODOLOGY

Aim: Designing a Graded Doping Double-Gate Junctionless MOSFETs and

Comprasion with Uniform Doping Profile

The Double-gate (DG)-JL-MOSFET has been the most entertained structure

Of DG-JL-MOSFETs over the single-gate structures have enabled them as a promising
MOS transistor with sub-50 nm scalability for the VLSI/Ultra Large Scale Integration
applications with the different technology boosters. However, the major drawbacks of
the sub-50nm CMOS transistors include the severe degradation of the subthreshold
characteristics and hot- carrier effects (HCEs) with the decreased gate lengths, while
scaling from one technology node to another technology node. While the retrograde
channel doping and super-halo channel doping in the gate-to-channel direction have
been used to optimize the ON-state drive current and OFF-state leakage current
separately lateral graded-channel (GC) doping engineering (by maintaining a high
doping near the source end and a low doping at the drain end) has also been explored for
achieving improved drive current, reduced SCEs, and reduced HCEs. The low doped
region near the drain end reduces the electric field thereby reducing the impact
ionization and, hence, the HCEs at the drain side of the device.

1. Design and simulation of DG-JL-MOSFET.

2. Device parameters used during simulation.
3. Model used during simulation of device BGN, Shockley-Read-Hall (SRH), Auger
Recombination Model, FLDMOB.
4. To find out digital parameters.
Figure 4.3 Schematic Structure of DG-JL-MOSFET using Graded Doping.
27
 CHAPTER 5

5.SIMULATION
Graded Doping (DG-JL-MOSFET) Using Si

 Structure of Graded Doping (DG-JL-MOSFET) (Si) :

Figure 5.1 Schematic Structure of DG-JL-MOSFET using Graded doping.

 Tonyplot Structure of Graded Doping (DG-JL-MOSFET) :

26


Figure 5.2 Tonyplot Structure of an DG-JL-MOSFET using Graded doping

 Parameters Structure :
Table 5.1 Various parameters used in Graded Doping DG-JL- MOSFET
using Si

Result:
27
Fig 5.3 : Center Potential DG-JL-MOSFET different Channel length Using Graded Doping

28
Fig 5.4 : Transfer Curve(Log scale) Different Channel length Using Graded Doping

Fig 5.5 : Threshold Voltage, Vth (volt) of an DG-JL-MOSFET

29
Fig 5.5 : Sub-threshold Swing (SS) of a DG-JL-MOSFET Using Graded doping

30
Uniform Doping (DG-JL-MOSFET) Using Si

Fig 5.6: Schematic capture of DG-JL-MOSFET Using Uniform Doping

31
 Fig 5.7 : Transfer curve (Log Scale) DG-JL-MOSFET Using Uniform Doping

Fig5.8 : Comparison of Graded Doping DG-JL-MOSFET and Uniform Doping DG-JL-MOSFET

32
Fig 5.9: Comprasion Of Sub-threshold Swing (SS) Graded Doping DG-JL-MOSFET and
Uniform Doping DG-JL-MOSFET

CHAPTER 6

6.RESULT AND DISCUSSION

The Graded Doping Double Gate Junctionless (DG-JL) MOSFET, Uniform Doping
Double Gate Junctionless (DG-JL) MOSFET were implemented in the device simulator
(SILVACO ATLAS).

The Drift-Diffusion, Lombardi (CVT) Model, Fermi–Dirac Carrier Statistics, and the
Standard SRH and Auger recombination Models have been used for simulating all the
device structures.

33
Fig 6.1 : Comparison Of Graded Doping DG-JL-MOSFET and Uniform Doping DG –JL-MOSFET

From the fig it is evident that there is significant decrease in off current i.e. the
subthreshold leakage current due to Graded Channel Double Gate Junctionless (DG-JL)
MOSFET in comparison with uniform doped channel. But for the ON current we can
see that it is bit higher for the Graded doping DG-JL-MOSFET.

It is also observed that the depression in the center potential for graded channel than in
uniform doped channel case so the electric field is higher at the source than drain side
for graded channel.

34
7. CONCLUSION
By the simulation results we can see that there is significant improvement in
performance of Graded Doping Double Gate Junctionless (DG-JL) MOSFET by
considering the Uniform Doping Double Gate Junctionless (DG-JL) MOSFET.
The purposed model characteristics are yet to be compared with results obtained by
modelling.

It has been found that the performance of the Uniform Doping DG-JL-MOSFETs can
be significantly improved in the Graded Doping (DG-JL) MOSFET structure. A
reasonably good agreement between the analytical and simulated results obtained from
the 2-D ATLASTM device simulator shows the validity of the model reported in this
thesis.

35
8. FUTURE SCOPE
We can further change the other parameters of the device (tsi, doping profile, work
function of gate material) to check the outcome results for development of new
devices .

The following recommendations can be made based on the present work.

1. The work related to the comparison between different JL devices in terms of

transfer characteristics, CMOS inverter can be extended to other multi gate MOSFET.

2. The present work can be extended by considering SCEs and compare among the
devices which have the better immunity with respect to these effects.

REFERENCES

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[31]We were going to complete our project J.B. Pant College Pauri
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38
APPENDIX A

Graded Doping simulation code

go atlas simflags="-P 4"

mesh space.mult=2.0

y.mesh loc =-0.001 spac = 0.001

y.mesh loc = 0.000 spac = 0.0001
y.mesh loc = 0.001 spac = 0.001
y.mesh loc = 0.002 spac = 0.001
y.mesh loc = 0.003 spac = 0.001
y.mesh loc = 0.004 spac = 0.001
y.mesh loc = 0.005 spac = 0.001
y.mesh loc = 0.006 spac = 0.001
y.mesh loc = 0.007 spac = go atlas simflags="-P 4"
mesh space.mult=2.0

x.mesh loc=0.000 spac=0.001

x.mesh loc=0.001 spac=0.001
x.mesh loc=0.002 spac=0.001
x.mesh loc=0.003 spac=0.001
x.mesh loc=0.004 spac=0.001
x.mesh loc=0.005 spac=0.001
x.mesh loc=0.006 spac=0.001
x.mesh loc=0.007 spac=0.001
x.mesh loc=0.008 spac=0.001
x.mesh loc=0.009 spac=0.001
x.mesh loc=0.010 spac=0.001
x.mesh loc=0.011 spac=0.001
x.mesh loc=0.012 spac=0.001
x.mesh loc=0.013 spac=0.001
x.mesh loc=0.014 spac=0.001
x.mesh loc=0.015 spac=0.001
x.mesh loc=0.016 spac=0.001
x.mesh loc=0.017 spac=0.001
x.mesh loc=0.018 spac=0.001
43
x.mesh loc=0.019 spac=0.001
x.mesh loc=0.020 spac=0.001

0.001
y.mesh loc = 0.008 spac = 0.001
y.mesh loc = 0.009 spac = 0.001
y.mesh loc = 0.010 spac = 0.0001
y.mesh loc = 0.011 spac = 0.001

region number=1 x.min= 0.000 x.max= 0.020 y.min= -0.001 y.max= 0.000
material=SiO2
region number=2 x.min= 0.00 x.max=0.010 y.min= 0.00 y.max=0.01
material=Silicon
region number=3 x.min= 0.010 x.max=0.020 y.min= 0.00 y.max=0.01
material=Silicon
region number=4 x.min= 0.000 x.max= 0.020 y.min= 0.010 y.max= 0.011
material=SiO2

# #1-source #2-drain #3-fgate #4-bgate

electrode name=source number=1 x.min= 0.0 x.max=0.0 y.min= 0.00

y.max=0.010
electrode name=drain number=2 x.min= 0.020 x.max= 0.020 y.min= 0.00
y.max=0.010

electrode name=fgate number=3 x.min=0.00 x.max=0.020 y.min=-0.001 y.max=-

0.001
electrode name=bgate number=4 x.min=0.00 x.max=0.020 y.min= 0.011 y.max=
0.011

doping uniform conc=1e18 n.type region=2

doping uniform conc=1e19 n.type region=3
44
contact name=source neutral
contact name=drain neutral
contact name=fgate workfunction=5.2
contact name=bgate workfunction=5.2 common=fgate

models srh auger cvt fermidirac

# models auger consrh conmob fldmob b.electrons=2 b.holes=1 evsatmod=0 \

hvsatmod=0 fermi hcte.el print numcarr=2 temperature=300

method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4 autonr \

nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03 maxinner=25

#
# method newton itlimit=25 trap atrap=0.5 maxtrap=4 autonr nrcriterion=0.1 \
tol.time=0.005 dt.min=1e-25

solve init
solve vdrain=0.01
solve vdrain=0.01 vstep=0.01 vfinal=0.1 name=drain
#solve vgate =0.001
#solve vgate =1.0
#solve vgate =1.5
solve vsource=0.0

# log file for id vg characteristics

log outf=wf1_5.2_wf2_5.2_Nd1_10e19_Nd2_10e19_L20_0.1vds.log
# solve vfgate =0.0

solve vfgate=0 vstep=0.01 vfinal= 0.8 name=fgate

output e.field recombination band.param con.band val.band e.mobility ex.velocity \

45
 ey.velocity e.velocity impact.i flowlines charge
j.drift j.total j.diffusion

save outf=wf1_5.2_wf2_5.2_Nd1_10e19_Nd2_10e19_L20_0.1vds.str

tonyplot wf1_5.2_wf2_5.2_Nd1_10e19_Nd2_10e19_L20_0.1vds.str
wf1_5.2_wf2_5.2_Nd1_10e19_Nd2_10e19_L20_0.1vds.log

extract name="vt" (xintercept(maxslope(curve(abs(v."fgate"),abs(i."drain")))) \

- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."fgate"),log10(abs(i."drain")))))

extract name="vtcc_0.1vds" x.val from curve(v."fgate",i."drain") where y.val=5e-6

46
APPENDIX B

Uniform Doping simulation code

go atlas simflags="-P 4"

mesh space.mult=2.0

x.mesh loc=0.000 spac=0.001

x.mesh loc=0.001 spac=0.001
x.mesh loc=0.002 spac=0.001
x.mesh loc=0.003 spac=0.001
x.mesh loc=0.004 spac=0.001
x.mesh loc=0.005 spac=0.001
x.mesh loc=0.006 spac=0.001
x.mesh loc=0.007 spac=0.001
x.mesh loc=0.008 spac=0.001
x.mesh loc=0.009 spac=0.001
x.mesh loc=0.010 spac=0.001
x.mesh loc=0.011 spac=0.001
x.mesh loc=0.012 spac=0.001
x.mesh loc=0.013 spac=0.001
x.mesh loc=0.014 spac=0.001
x.mesh loc=0.015 spac=0.001
x.mesh loc=0.016 spac=0.001
x.mesh loc=0.017 spac=0.001
x.mesh loc=0.018 spac=0.001
x.mesh loc=0.019 spac=0.001
x.mesh loc=0.020 spac=0.001

y.mesh loc =-0.001 spac = 0.001

y.mesh loc = 0.000 spac = 0.0001
y.mesh loc = 0.001 spac = 0.001
47
y.mesh loc = 0.002 spac = 0.001
y.mesh loc = 0.003 spac = 0.001
y.mesh loc = 0.004 spac = 0.001
y.mesh loc = 0.005 spac = 0.001
y.mesh loc = 0.006 spac = 0.001
y.mesh loc = 0.007 spac = 0.001
y.mesh loc = 0.008 spac = 0.001
y.mesh loc = 0.009 spac = 0.001
y.mesh loc = 0.010 spac = 0.0001
y.mesh loc = 0.011 spac = 0.001

region number=1 x.min= 0.000 x.max= 0.020 y.min= -0.001 y.max= 0.000
material=SiO2
region number=2 x.min= 0.00 x.max=0.020 y.min= 0.00 y.max=0.01
material=Silicon
region number=3 x.min= 0.000 x.max= 0.020 y.min= 0.010 y.max= 0.011
material=SiO2

# #1-source #2-drain #3-fgate #4-bgate

electrode name=source number=1 x.min= 0.0 x.max=0.0 y.min= 0.00

y.max=0.010
electrode name=drain number=2 x.min= 0.020 x.max= 0.020 y.min= 0.00
y.max=0.010

electrode name=fgate number=3 x.min=0.00 x.max=0.020 y.min=-0.001 y.max=-

0.001
electrode name=bgate number=4 x.min=0.00 x.max=0.020 y.min= 0.011 y.max=
0.011

doping uniform conc=1e19 n.type region=2

48
contact name=source neutral
contact name=drain neutral
contact name=fgate workfunction=5.2
contact name=bgate workfunction=5.2 common=fgate

models srh auger cvt fermidirac

# models auger consrh conmob fldmob b.electrons=2 b.holes=1 evsatmod=0 \

hvsatmod=0 fermi hcte.el print numcarr=2 temperature=300

method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4 autonr \

nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03 maxinner=25

#
# method newton itlimit=25 trap atrap=0.5 maxtrap=4 autonr nrcriterion=0.1 \
tol.time=0.005 dt.min=1e-25

solve init
#solve vdrain=0.1
solve vdrain=0 vstep=0.01 vfinal=0.1 name=drain
#solve vgate =0.001
#solve vgate =1.0
#solve vgate =1.5
solve vsource=0.0

# log file for id vg characteristics

log outf=wf1_5.2_wf2_5.2_Nd1_10e18_Nd2_10e19_L20_0.5vds.log
#solve vfgate =0.1

solve vfgate=0 vstep=0.01 vfinal= 0.8 name=fgate

output e.field recombination band.param con.band val.band e.mobility ex.velocity \

ey.velocity e.velocity impact.i flowlines charge j.drift j.total j.diffusion
49
save outf=wf1_5.2_wf2_5.2_Nd1_10e18_Nd2_10e19_L20_0.5vds.str

tonyplot wf1_5.2_wf2_5.2_Nd1_10e18_Nd2_10e19_L20_0.5vds.str
wf1_5.2_wf2_5.2_Nd1_10e18_Nd2_10e19_L20_0.5vds.log

extract name="vt" (xintercept(maxslope(curve(abs(v."fgate"),abs(i."drain")))) \

- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."fgate"),log10(abs(i."drain")))))

extract name="vtcc_0.05vds" x.val from curve(v."fgate",i."drain") where y.val=5e-

6

50