Encounter

Floorplanning, Physical Synthesis,
and Place and Route (Flat)
Version 10.1
Lab Manual January 29, 2010
 1990-2010 Cadence Design Systems, Inc. All rights reserved.
Printed in the United States of America.
Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134, USA
Cadence Trademarks
Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol.
For queries regarding Cadence trademarks, contact the corporate legal department at the address above or call 800.862.4522.
Allegro® Incisive® Silicon Express™

Accelerating Mixed Signal Design® InstallScape™ SKILL®
Assura® IP Gallery™ SoC Encounter™
BuildGates® NanoRoute® SourceLink® online customer support
Cadence® (brand and logo) NC-Verilog® Specman®
CeltIC® NeoCell® Spectre®
Conformal® NeoCircuit® Speed Bridge®
Connections® OpenBook® online documentation library UltraSim®
Diva® OrCAD® Verifault-XL®
Dracula® Palladium® Verification Advisor®
ElectronStorm® Pearl® Verilog®
Encounter® PowerSuite® Virtuoso®
EU CAD® PSpice® VoltageStorm®
Fire & Ice® SignalStorm® Xtreme®
First Encounter® Silicon Design Chain™
HDL-ICE® Silicon Ensemble®
Other Trademarks
Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in
the United States and other countries and are used with permission.
All other trademarks are the property of their respective holders.
Confidentiality Notice
No part of this publication may be reproduced in whole or in part by any means (including photocopying or storage in an information storage/retrieval system)
or transmitted in any form or by any means without prior written permission from Cadence Design Systems, Inc. (Cadence).
Information in this document is subject to change without notice and does not represent a commitment on the part of Cadence. The information contained herein
is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence customers in accordance
with a written agreement between Cadence and its customers. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly
disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not
warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may
result from use of such information.
RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the
Rights in Technical Data and Computer Software clause at DFARS 252.227-7013.
UNPUBLISHED This document contains unpublished confidential information and is not to be disclosed or used except as authorized by written contract with
Cadence. Rights reserved under the copyright laws of the United States.
Table of Contents Floorplanning, Physical Synthesis, and Place and Route (Flat)
Table of Contents
Floorplanning, Physical Synthesis, and Place and Route (Flat)
Module 1 About this Course
Lab ii-1 Locating Cadence Online Support Solutions................................................................... ii-1

Lab ii-2 Customizing Notification and Search Preferences .......................................................... ii-3
Objective:....... To set preferences so you can improve search results and receive email
notification. ................................................................................................................ ii-3
Module 2 Design Import and Floorplanning
Lab 1-1 Importing a Design .......................................................................................................... 1-1

Design Information .................................................................................................... 1-1
Starting the Software ................................................................................................. 1-1
Importing a Design .................................................................................................... 1-1
Viewing the Design ................................................................................................... 1-3
Viewing the Design Hierarchy .................................................................................. 1-6
Lab 1-2 Using Bindkeys................................................................................................................ 1-7
Using the Bindkey Form............................................................................................ 1-7
Using Bindkeys.......................................................................................................... 1-8
Lab 1-3 Tearing Off Menus......................................................................................................... 1-10
Lab 1-4 Clearing the Floorplan ................................................................................................... 1-11
Using the Clear Floorplan Form .............................................................................. 1-11
Lab 1-5 Initializing the Floorplan ............................................................................................... 1-12
Specifying the Core Size.......................................................................................... 1-12
Lab 1-6 Customizing the Menus ................................................................................................. 1-14
Lab 1-7 Checking the Design ...................................................................................................... 1-16
Lab 1-8 Floorplanning a Design.................................................................................................. 1-18
Floorplanning........................................................................................................... 1-18
Relative Floorplanning ............................................................................................ 1-21
Automatic Floorplanning Synthesis for Block Placement....................................... 1-24
Adding a Block Halo ............................................................................................... 1-24
Power Planning ........................................................................................................ 1-27
Preplacing a Cell with the Design Browser ............................................................. 1-29
Creating Followpin Routing with Special Route ..................................................... 1-32
Saving the Session ................................................................................................... 1-33
January 29, 2010 Cadence Design Systems, Inc. iii

Floorplanning, Physical Synthesis, and Place and Route (Flat) Table of Contents
Module 3 Placement and Trial Route
Lab 2-1 Running Placement .......................................................................................................... 2-1

Lab 2-2 Running a Trial Route...................................................................................................... 2-6
Viewing Routing Congestion..................................................................................... 2-6
Saving the Design ...................................................................................................... 2-9
Viewing a Design After a Trial Route ....................................................................... 2-9
Module 4 Extraction, Timing Analysis, Optimization, and CTS
Lab 3-1 Extracting RC Data .......................................................................................................... 3-1

Calculating Delays ..................................................................................................... 3-2
Lab 3-2 Running Timing Analysis and Generating a Slack Report.............................................. 3-3
Lab 3-3 Running Timing Optimization......................................................................................... 3-5
Lab 3-4 Running Clock Tree Synthesis ........................................................................................ 3-7
Viewing Clock Tree Results ...................................................................................... 3-8
Module 5 Generating Scale Factors for Extraction
Lab 4-1 Extracting and Generating Scale Factors......................................................................... 4-1

Loading the Design .................................................................................................... 4-1
Generating Scale Factors with External SPEF File ................................................... 4-2
Module 6 Power Analysis
Lab 5-1 Running Power Analysis ................................................................................................. 5-1

Starting the Software ................................................................................................. 5-1
Importing a Design .................................................................................................... 5-1
Loading a Floorplan................................................................................................... 5-1
Running Placement and Trial Route .......................................................................... 5-2
Extracting RC Data .................................................................................................... 5-2
Setting the Power Analysis Mode.............................................................................. 5-3
Running Early Rail Analysis ..................................................................................... 5-4
Viewing Power Analysis Results............................................................................... 5-5
Module 7 Routing and Optimizing the Design
Lab 6-1 Routing Critical Nets with Shielding and Spacing .......................................................... 6-1
Setting Shielded and Spacing Net Attributes............................................................. 6-1
Routing the Nets ........................................................................................................ 6-2
iv Cadence Design Systems, Inc. January 29, 2010

Table of Contents Floorplanning, Physical Synthesis, and Place and Route (Flat)
Module 8 Wire Editing
Lab 7-1 Using the Interactive Wire Editor .................................................................................... 7-1

Locating the Net for Manual Routing........................................................................ 7-1
Using the Wire Editor ................................................................................................ 7-7
Replacing a Via in a Design .................................................................................... 7-12
Reshaping a Wire..................................................................................................... 7-14
Forcing the Width of a Signal Wire......................................................................... 7-15
Module 9 Verifying a Design
Lab 8-1 Using the Verify Commands in a Design ........................................................................ 8-1

Using Verify Connectivity......................................................................................... 8-1
Using Verify Geometry and the Influence Rule ........................................................ 8-5
Module 10 Running the ECO Flow
Lab 9-1 Loading a Design for ECO Routing ................................................................................ 9-1

Getting Started ........................................................................................................... 9-1
Implementing an ECO in the New Netlist with a Design.......................................... 9-1
Module 11 Database Commands
Lab 10-1 Using the dbGet and dbSet Commands ......................................................................... 10-1
Getting Started ......................................................................................................... 10-1
Module 12 Generating and Running the Foundation Flow Scripts
Lab 11-1 Generating and Running the Foundation Flow Scripts.................................................. 11-1
Getting Started ......................................................................................................... 11-1
Running the Foundation Flow Wizard..................................................................... 11-2
January 29, 2010 Cadence Design Systems, Inc. v

Floorplanning, Physical Synthesis, and Place and Route (Flat) Table of Contents
vi Cadence Design Systems, Inc. January 29, 2010

Terminology Conventions
Mouse Use and Terminology
Term Action Icon Example
click Quickly press and release the specified mouse button.

On menus and forms, you use the left mouse button Click left
most of the time.
double-click Rapidly press the specified mouse button twice.

Double
2 click
Shift-click Hold down the appropriate key or keys and click a

Control-click specified mouse button. Shift
Shift-Control-click
Shift- click right
pop up Press the middle mouse button.

Click
middle
pull down Move the mouse cursor to the menu name on the menu
banner, press and hold the left mouse button, move the
cursor down to highlight the menu selection, release the
mouse button to execute the selection.
Enter Type a command in a window and press Return to

execute the command.
Choose Position the cursor over a command and press the left
mouse button. Select or pick are synonyms for choose.
1/12/11 Cadence Design Systems, Inc. vii

Conventions Terminology
viii Cadence Design Systems, Inc. 1/12/11

Labs for Module ii
About this Course

Locating Cadence Online Support Solutions
Objective: To log in to Cadence Online Support (COS) and

search for information about a specific issue.
You can only complete this lab if you have access to the internet and a
Cadence® Online Support account. If you do not, your instructor might be
able to perform a demo of this lab for the class.
1. In a web browser, enter

http://support.cadence.com
2. Log in to Cadence Online Support with your email and password.
The Support Home page appears.
3. On the Support Home page, make sure the following options are
selected:
a. All Document Types
1/12/11 Floorplanning, Physical Synthesis, and Place and Route (Flat) ii-1
b. All Products
4. In the Search field, enter congestion click SEARCH.

A window displays the search results.
5. In the Troubleshooting Info section, click the match called:

What is the meaning of the colors in the routing congestion map?
A window opens with a description of the problem and the solution.
6. Close the solution window.
7. You can filter the search results by selecting specific document

types or products which are listed to the left of the results.
Note: You can filter the search results by selecting specific

document types or products which are listed to the left of the
results.
End of Lab
ii-2 Floorplanning, Physical Synthesis, and Place and Route (Flat) 1/12/11
Customizing Notification and Search Preferences
Objective:To set preferences so you can improve search results

and receive email notification.
---------------------------------------------------------------------------------
1. You can set product and other preferences for improved search
results and email notification.
2. Click the My Account link.
3. Click the Notification Preferences tab.
4. On the Set Email Notification Preferences page, do the following

actions:
a. If you are interested in receiving email notifications, check Send

me email notifications about new product releases.
b. Click Edit Product List and select your products of interest.
c. Specify your preferred email format.
d. Select the document types you are interested in and the frequency
of delivery.
e. Click Save.
5. Click the Search Preferences tab.
6. On the Set Search Preferences page:
a. Click Use same product and document type preferences as my

Notification Preferences.
b. Click Save.
End of Lab
1/12/11 Floorplanning, Physical Synthesis, and Place and Route (Flat) ii-3
ii-4 Floorplanning, Physical Synthesis, and Place and Route (Flat) 1/12/11
Labs for Module 1
Design Import and Floorplanning

Lab 1-1 Importing a Design
Objective: To start the software and import a design.
In this lab, you import a gate-level netlist and libraries into the Encounter®
Digital Implementation system and create a floorplan. You become familiar
with the floorplanning and power planning forms and icons. You also
become familiar with checking the libraries, checking the design, and using
bindkeys.
Design Information
The design contains almost 6000 instances, 57 I/Os and about 6274 nets. The
netlist is a hierarchical Verilog® netlist. The DMA source clock is
DTMF_INST/clk. The Serial Port Interface Clock is DTMF_INST/spi_clk.
The scan clock is scan_clk. The process used is the180 nanometer process
technology with 6 layers of metal.
Starting the Software
1. Change to the working directory by entering this command:

cd FPR/work
2. Start the Encounter Digitital Implementation (DI) system by

entering:
encounter
The Encounter DI system appears.
Do not use the window where you started the software for any
windowing or UNIX operations, except to communicate with the
tool.
Importing a Design
1. Import a gate-level netlist, timing constraints, and libraries by

choosing File –Import Design on the pull-down menu.
The Design Import form comes up.
a. Click the Load button.
1/12/11 Floorplanning, Physical Synthesis, and Place and Route (Flat) 1-1
Importing a Design Lab 1-1
b. Select the dtmf.conf file and click Open.

When you load the file, it fills in the fields in the Design Import
window.
Ignore the Warning related to the MMMC specification.
You will see the technology files and the ./dtmf.view file that you
will use in the labs. The dtmf.view file contains pointers to the
timing library and the constraints files.
The I/O assignment file dtmf.io contains directives about how to
place the I/O pads around the periphery of the core area.
2. In the Design Import window, click OK to load the design and

libraries.
Here is a brief description of the fields in the Design Import window.
Field Description
Verilog Files Contains the name(s) of gate-level Verilog netlist file(s).
1-2 Floorplanning, Physical Synthesis, and Place and Route (Flat) 1/12/11
Field Description
LEF Files Library of components and physical data for the components in LEF
format.
IO Assignment File This file contains the I/O pad order information to enable the software
to place the pads on the periphery of the design. If this file is not
provided, the tool will place the I/O pads randomly around the
periphery of the design.
MMMC View Contains pointers to timing libraries and SDC constraints files
Definition File
Viewing the Design
In this section, you learn more about the objects on the screen and how to
view and interpret what you see in the design window.
1. Enlarge the window by dragging out the corner of the window so

that you can see all the modules in your design as well as all the EDI
menus.
2. Select Tools-Log Viewer
3. In the Log File form, click Open.

Are there any errors displayed?
Answer:
4. Close the Log Viewer.
5. Use the zoom out icon to view more of the objects.

Zoom in and out to see these objects, using the zoom in and zoom
out buttons. The zoom fit icon fits only the design core in the
window.
You can also press z to zoom in and Shift-z to zoom out. z Z
6. Move the cursor over the icons.
a. Notice that their functions are displayed in text boxes as shown

here.
7. Select the pink module DTMF_INST on the left of the core

area.
8. Click the Ungroup icon once to ungroup the modules. Do not

perform this operation more then once.
9. Double-click several objects to see names and properties of the

design objects.
2
The pink objects on the left of the core area is the module guide,
whereas the green objects to the right of the core area are all the
blocks (hard macros) in the design. The pink guide represents
modules that were defined in the imported Verilog netlist.
Note: The size of the module guides relates to the utilization of each
module and the number of standard cells that the modules
contain.
10. To zoom a particular area, press and drag the right mouse button
over a rectangular area.
The window zooms to that area.
11. Choose Options–Set Preference and select the Display tab.

The Min Floorplan Module Size parameter determines the size of
the module guides. Because the Min. Floorplan Module Size is
defined as 100, if a module contain fewer than 100 instances, it will
be merged into another module guide.
a. Click the Help button on the form to better understand the fields
on the form.
Most forms have a Help button to bring up a Cadence Help
window and give you more information about the form.
b. Click the Cancel button on the form when you are finished.
12. Regroup the modules by selecting one of the pink guides and
pressing the Group icon.
Viewing the Design Hierarchy
1. To view the design hierarchy, choose Tools–Design Browser to

view the hierarchical design that you imported.
2. Expand the modules by clicking on the + sign next to Modules.
3. Expand DTMF_INST by clicking on the + sign.

How many nets does it contain?
Answer: _____________
4. Click the + sign in front of Terms to view the I/O terminals of

DTMF_INST.
5. Close the Design Browser window by choosing File–Quit when

you are done.
End of Lab
Lab 1-2 Using Bindkeys
Objective: To use the bindkeys to implement floorplanning

functions.
Using the Bindkey Form
1. Choose Options–Set Preference to bring up the form.
2. Make sure that the Design tab is selected.
3. Click the Binding Key button to display the bindkey definition

form.
4. Click Action to sort all the actions alphabetically by the action

names.
5. Click Key to sort the bindkeys alphabetically by the binding key

names.
Using Bindkeys Lab 1-2
6. Re-define the zoomIn key to v.
7. Click OK.
8. Test that it has been redefined.
9. Reset the zoom in key back to z.
10. Click Cancel in the Preferences form.
Using Bindkeys
1. Press Shift-z to zoom out. Z
2. Press Tab and the right arrow keys to Pan right.
3. Click the green hard macro RAM_256x16_INST. It is the first macro

to the right of the core area.
Note: The blue flight lines display connections between the block
and the module guide that it connects to.
4. Double-click RAM_256X16_INST.
2
The Attribute Editor appears.
5. Check the orientation of the macro.

What is the orientation of the hard block?
Answer: _________________________
6. Close the Attribute Editor form.
7. Click the Move button and move the RAM inside the core area of
the design.
8. Click left to place the RAM inside the core area.
9. Press the r key to bring up the Flip/Rotate Selected Instances r

form.
10. Select R90.
11. Click OK.
12. Press a to get out of the move mode and into the selection mode. a
13. Select DTMF_INST, the large pink module on the left of the core
area.
G
14. Press Shift-g once to ungroup the DTMF_INST module.
15. Staying in Select mode, click a pink module to select it.
16. Hold the Shift key down and click to select another module. Release
Shift –
the Shift key after selecting the module.
Using Bindkeys Lab 1-2
17. Click the Move button and move the two modules into the core
area.
18. Click to place the modules.
End of Lab
Lab 1-3 Tearing Off Menus
Lab 1-3 Tearing Off Menus
Objective: To use the tear-off menu feature when you have to

repeat tasks.
1. Choose Floorplan.
2. Click the dashed line above the menu list to detach the menu from
the main task bar.
3. Place the detached menu in a convenient location on your desktop.
End of Lab
Clearing the Floorplan Lab 1-4
Lab 1-4 Clearing the Floorplan
Objective: To clear floorplanning objects from a floorplan to

improve an existing floorplan or create a new one.
Using the Clear Floorplan Form
1. In the Floorplan menu, choose Clear Floorplan to bring up the

form.
2. Select All Floorplan Objects.
3. Click OK.
The Module Guides and the hard macro that were placed in the core
area will be unplaced.
4. You can select to clear all floorplan objects or a subset of floorplan

objects.
End of Lab
Lab 1-5 Initializing the Floorplan
Lab 1-5 Initializing the Floorplan
Objective: To set the aspect ratio and explore the hierarchy.
Specifying the Core Size
1. Choose Specify Floorplan.

The Specify Floorplan form appears.
Core width and height can also be

specified by selecting the Width
and Height option, and entering
Core Height and Core Width
numbers.
As an alternative, die size can be
specified by selecting the Die
Size by option and entering Die
Height and Die Width values.
The Core Size by Ratio, Core Utilization, and Core Margins by

fields are populated with values from the dtmf.conf file.
2. Click the Help button on the Specify Floorplan form to learn more
about the options on this form.
3. Click OK to initialize the floorplan.
Initializing the Floorplan Lab 1-5
4. Select the ruler icon or press the k key and measure the distance
between the core area and the I/O boundary.
5. Delete the ruler by clicking the Clear all ruler icon or by pressing
Shift-k.
Lab 1-6 Customizing the Menus
Lab 1-6 Customizing the Menus
Objective: To create a menu item and associated commands.
Use the commands uiAdd and uiDelete to add and delete menu items.
1. Run the following command in the csh window where you started
the tool:
uiAdd expMenu -type menu -label NewMenu -in main
2. Notice that a new menu NewMenu appears in the upper right corner
of the main menu. You might have to expand the design window to
see the newly created menu.
3. To add a subcommand in under NewMenu enter the following

command:
uiAdd expCmd -type command -label "New command..." \
-command [list puts "execute my command"] -in expMenu
Next you will add a new menu item to an existing menu.
4. Enter the following command to identify the exisiting menu where

you will add a new menu item:
set vMenu [uiFind main -type menu -label \
"Verify"]
Customizing the Menus Lab 1-6
5. Run the following command to add New Verify to the Verify menu:
uiAdd expVerify -type command \
-label "New Verify..." -command [list puts \
"New Verify"] -in $vMenu
6. Notice that a new menu item appears under the Verify menu.
7. Now, add a new toolbar by entering the following:

uiAdd expToolbar -type toolbar -in main -label\
“New Toolbar" -newline true
8. Add a new toolbutton “my toolbutton” in “New toolbar” by

entering:
uiAdd expToolbutton -type toolbutton -in expToolbar \

-label "new toolbutton" -tooltip "new toolbutton"
9. Delete the menu, NewMenu, that you created in a previous step by

entering this command:
uiDelete expMenu
End of Lab
Lab 1-7 Checking the Design
Lab 1-7 Checking the Design
Objective: To determine if there is missing or incorrect

information in the libraries or in the netlist.
In this lab, you check the design files and identify the problems to fix.
1. At the prompt, enter:

checkDesign -netlist
2. View the checkDesign/DTMF_CHIP.main.htm.ascii file.

How many floating outputs are in the design?
Tip: Hint: Check for the string “Output Floating nets” in the
checkDesign/DTMF_CHIP.main.htm.ascii file.
Answer: _____________
Which cells are marked “Dont Use”?
Answer:
Checking the Design Lab 1-7
3. At the prompt, enter:

help checkDesign
You will see the options that are available.
You can run the checkDesign command at any time during
prototyping and implementation. Depending on where you are in the
design process, the checkDesign command will check these items:
■ Netlist after the design has been loaded
■ Physical library before floorplanning
■ Power and ground connections before routing and extraction
■ Legal placement of cells
■ Timing libraries before any timing-related operations are run like

timing-driven placement/routing, timing optimization, clock-tree
synthesis, and static timing analysis
■ Tie-high/tie-low connections before routing and extraction
End of Lab
Lab 1-8 Floorplanning a Design
Objective: To floorplan and explore manual floorplanning icons.
Floorplanning
This section introduces you to the floorplanning icons in the Tools area.
1. Position your cursor over each of the icons in the Tools area to
display their functionality.
2. Pan left in the design window by pressing the Tab key and by
clicking the left arrow button on your keyboard.
3. Select a pink module guide.
4. Click the Ungroup icon once to move down the hierarchy.
5. Click the Move button and move a module guide (pink) into the core
design area.
If you do not want to see these blue flight lines, click theAll Colors
button.
This will bring up the Color Preferences form
Floorplanning a Design Lab 1-8
6. Under the View-Only tab, unselect Flight Line.
7. Close the Color Preferences form.
8. Click the Cut Rectilinear icon.
9. Grab an edge or corner of the selected module guide using the left
mouse button and draw a box to represent the cutout area.
10. Click again. The resulting rectangle will become the cutout area of
the originally rectangular-shaped guide.
Notice that the TU number changes. The TU value is the target
utilization percentage for the given module area.
11. Click the Select icon.

What is the binding key that you can use instead?
Tip: The binding key is associated with the selectMode action in the
Binding Key form.
12. Create placement blockage by selecting the corresponding icon.

Then use the left mouse button to create the blockage. Make sure
that the blockage that you create does not overlap a module.
13. Select the placement blockage that you created, and press q to view q
the properties.
What type of placement blockage is it?
Answer: ________________________
14. Close the attribute editor.
15. Look up the Encounter documentation to determine the difference

among hard, soft, and partial blockage.
Relative Floorplanning
In this section, you use the Relative Floorplan tool to place blocks in the core
area.
1. Select the DTMF_INST/ARB_INST/ROM_512x16_0_INST block.
2. From the detached menu, choose

Relative Floorplan–Edit Constraint.
3. Make sure that the DTMF_INST/ARB_INST/ROM_512x16_0_INST

block is in the Object field.
If the Object field is empty, click the Get Selected button in the
Relative Floorplan form.
This button populates the Object field.
4. Click Relative to Object and select the Bottom_Core_Boundary

by clicking the arrow button.
5. In the Relation field, select Above.
6. In the Align by field, select Left Side.
7. Click Apply.
8. To place the DTMF_INST/PLLCLK_INST block relative to the

bottom of the core boundary, select the block and click get selected.
9. Select Bottom_Core_Boundary for the Relative to Object

parameter.
10. For Relation, click Above.
11. For Space enter 20.
12. In the Align by field, enter -20, select Right Side.
13. Click Apply.
14. Click Save.
15. Enter dtmf_relfp.tcl.

Relative floorplanning commands will be saved in the specified Tcl
file. The file can be sourced later for updating or adjusting an
existing floorplan based on the updated block sizes and positions.
16. View the saved .tcl script and notice that the parameters that are
saved correspond to the settings that you specified in the forms
earlier.
17. Click Cancel.
Automatic Floorplanning Synthesis for Block Placement
You can place the blocks in your design before placing the standard cells by
running automatic floorplanning.
1. Undo the floorplanning that you have done so far by choosing

Clear Floorplan in the detached menu.
2. Select All Floorplan Objects.
3. Click OK.
4. Choose Floorplan–Automatic Floorplan–Plan Design.
5. Select the setPlanDesignMode Tab.
6. Select the Keep Guide option.
7. Using the default settings in the form, click OK.

The blocks (hardmacros) and the guides that contain the blocks have
been placed in the core area automatically. The guides which do not
contain hardmacros remain outside the core area.
Adding a Block Halo
1. Select the PLL block.
2. Choose Edit Floorplan–Edit Halo to add a placement blockage

around the block.
a. Click Selected Blocks/Pads.
b. Select Placement Halo.
c. Enter 5 um for the Top/Bottom/Left/Right dimensions of the halo.
d. Click OK.
3. Zoom in to the area where the block was placed to view the halo that
you created.
4. Create a routing blockage by selecting the corresponding icon and

using the left mouse button to create the blockage in a corner of the
core area. Routing blockages are added to the design to alleviate
areas of possible routing congestion.
5. Select the routing blockage created, and press q to view the

q
properties.
Which layer is blocked?
6. Click Close to close the Attribute Editor form.
7. Save the floorplan in the .fp format by choosing

File–Save–Floorplan.
8. Enter dtmf_fp.fp for the filename.
9. Click Save.
10. View the saved floorplan file.
What attribute is the routing blockage translated to in the floorplan

file?
Answer: ____________________________________
11. Create a placement blockage in any area of the core.

A partial placement blockage can alleviate congestion by spreading
components farther apart during placement.
12. View its properties by selecting the blockage and then pressing q. q
13. Change the Type cyclic field from Hard to Partial.
14. Change the blockage percentage to 25% in the cyclic field.
15. Click OK.

You will explore the remaining floorplanning icons in the
subsequent labs.
Power Planning
1. In the detached power planning menu, choose

Power Planning–Add Ring.
The Add Rings form appears.
a. In the Nets field, make sure that the nets are VSS and VDD.
b. In the Ring Configuration field, make sure that METAL5 H layer

is selected for Top and Bottom.
c. Make sure that a width of 8 and a spacing of 1 is set.
d. Use METAL6 V as the layer for left and right. Select a width of
8, a spacing of 1.
e. Under Offset, select Center in channel.
f. Click OK to generate the power rings.
2. Choose Power Planning–Add Stripe.

The Add Stripes form appears.
a. Make sure that the nets field contain VDD and VSS.
b. Select Metal6 from the cyclic field.
c. Select Vertical, if it is not already selected.
d. Set the Width to 8.
e. Set the Spacing to 1.
3. Set the Set-to-set distance to 100.
a. For the Relative from Core Area or selected area, enter 100 for
both X from left and X from right.
b. Click OK.
c. Notice the power stripes and the vias connecting the rings to the
stripes are created.
Preplacing a Cell with the Design Browser
1. Detach the Tools menu.
2. Open the Design Browser by choosing Design Browser in the Tools

menu.
3. In the Find field, type the instance name:

DTMF_INST/DIGIT_REG_INST/digit_out_reg_3
4. Press the Enter key.
Note: It is a standard cell of cell type SDFFSHQX1.
5. Select the instance in the Design Browser form and open the
Attribute form for the instance by clicking the Attribute Editor
icon.
a. Click the mouse icon in the Location section of the Attribute

Editor.
b. Move the mouse pointer into the core design area. The pointer
changes to a crosshair.
c. Click a point in the core area of the design to preplace the

instance.
In the form, the Location coordinates are populated by the
coordinates where you click.
d. In the Attribute Editor, change the Status field to Placed and click
OK.
e. Select the Physical View if it is not already the current view.
f. Click the Physical Tab under the All Colors button.

Make sure that Instance and Std. cell are both set to visible under
the All Colors menu.
You might need to zoom in to see the cell.

Can you see the preplaced standard cell?
6. Close the Design Browser by choosing File–Quit.
Note: You can use this method to preplace a module, block, or

standard cell with the Design Browser.
7. Select the Floorplan View.
8. Remove the objects from your current Floorplan view by choosing

Clear Floorplan in the floorplan menu.
The form displays several options and categories.
9. Select All Floorplan Objects and click OK.
Creating Followpin Routing with Special Route
1. Select Route-Special Route.

This will bring up the Sroute form.
2. Enter VSS and VDD in the Nets field
3. Unselect all options except Follow Pins
4. For Layer Change Control, select Metal 6 for the top layer and Metal
1 for the bottom layer
5. Make sure that Allow Jogging and Allow Layer Control and
selected.
6. Click OK
7. The power router will take a few minutes to complete.

Ignore the violations for the purposes of this lab.
8. Select Tools-Violation Browser
9. Click Clear Violation
10. Click Close
11. Zoom into the followpin routes in the Physical view.
12. Notice that the power routes have been connected to the power
planned targets with relevant vias.
Saving the Session
1. Keep the session open and save the session by choosing

File–Save Design.
2. Enter this filename:

floorplan.enc
3. Click OK.
4. Close the session.
Summary
In this lab, you read in a gate-level netlist, floorplanned, and experimented

with the Tools menu.
End of Lab
Labs for Module 2
Placement and Trial Route

Lab 2-1 Running Placement
Objective: To read in a floorplan file and place the standard cells

in the design.
1. Start the Encounter® Digital Implementation software by entering:

encounter
2. Choose File –Import Design on the pull-down menu and load the
dtmf.conf file.
3. Load a floorplan file by choosing File–Load–Floorplan.
a. Select dtmf.fp.
b. Click Open.
c. Press OK.
4. Choose Options–Set Mode-Mode Setup.
Running Placement Lab 2-1
5. Click Placement in the List of Modes section.

This choice brings up the Placement Mode pane.
a. Make sure that Congestion Effort is set as Auto.
b. Select Run Timing Driven Placement if it is not already

selected.
c. Click OK.
6. Specify the two scan chains in the design by entering the following:
specifyScanChain scan1 \
-start {IOPADS_INST/Pscanin1ip/C} \
-stop {IOPADS_INST/Pscanout1op/I}
specifyScanChain scan2 \
-start {IOPADS_INST/Pscanin2ip/C} \
-stop {IOPADS_INST/Pscanout2op/I}
Note: Instead of typing in the above specifyScanChain commands,

you can source the scan.tcl file in the work directory.
7. Choose Place – Place Standard Cell.
8. Make sure that the Run Full Placement option is selected.
9. Make sure that Include Pre-Place Optimization is selected.
10. Use the default options and click OK to run placement.

The placement takes a few minutes to complete.
Notice that the status of the design on the lower right corner changes to
ScanOptimized. This field is a convenient way to check where you are in the
flow and determine what you need to do next.
11. In a separate xterm window, view the log file for this session.
What were the initial and final wirelengths of scan1 and scan2 as a
result of reordering?
Answer: ___________________________________
12. Save the scan DEF files by entering the following:

defOutBySection -noNets -noComps -scanChains scan.def
13. Display the Physical view by clicking the Physical View

button.
14. Make sure that Std. Cell and Instance under All Colors is set to
visible.
15. Zoom in to see the standard cell placements.
Running Placement Lab 2-1
16. Notice that in addition to cell placement, Trial Route has been run
on the design.
17. Press the All Colors button.
18. Select the View-Only Tab.
19. Make sure that Vertical Congest, Horizontal Congest, Congestion

and Congestion Label options are all selected.
20. Zoom in to see the congestion display.

Is the congestion mainly in the Vertical or in the Horizontal
direction?
Answer:
21. Choose Place – Display – Display Scan Chain.

This will bring up the Display Scan Connection Form.
22. With defaults selected, click OK.
23. Notice that the scan chain paths are highlighted.
24. Clear the highlight by choosing

Place – Display – Clear Scan Display.
25. Zoom in to see the placement of the cells.
26. Save the design by choosing File–Save Design and entering this file
name:
placement.enc
End of Lab
Running a Trial Route Lab 2-2
Lab 2-2 Running a Trial Route
Objective: To restrict the layers for Trial Router and to analyze

routing congestion
1. To run a trial route, choose Route–Trial Route.
2. Make sure that the max. route layer is set to 4. Even though there are
6 routing layers for this technology, for this lab, restrict Trial Route
to use only 4 layers.
3. With all other default options, click OK to run Trial Route using
Medium (default) effort.
Notice the diamond and multicolored congestion shapes that appear
in the Design window. These are areas of congestion.
Viewing Routing Congestion
1. Press the All Colors button.

This will bring up the Color Preferences form.
2. Select the View Only tab.
a. Make sure that Horizontal Congest and Vertical Congest are

both selected.
b. In the Vertical Congest area, click the square shape next to the
check box to bring up the Vertical Congest Color Selection form.
The colors on this form map to the congestion colors that result
from Trial route.
c. Click Close.
3. In the Physical view, zoom in to a red diamond shape.

These diamond shapes are areas with routing congestion problems.
You will see rectangles within the diamond shapes.
You will also see horizontal or vertical congestion with numbers:
V= # / # or H = # / #. The congestion numbers might be hard to see
without really zooming in.
The V and H apply to vertical and horizontal routing tracks. The first
number indicates the required tracks, while the second number
indicates the total available tracks.
The degree of congestion is displayed with different color coding.
The colors in increasing order of congestion are blue, green, yellow,
red, magenta, grey, and white. These diamond-shaped congestion
locators represent an average in the area.
By default, an area is identified as being congested even if the
number of available tracks equal the number of required tracks. You
can change this behavior by using the Preferences form.
4. To get a general idea on the routability of the design, view .log file
for your session and view the log generated by Trial Route. Look for
the keyword Congestion distribution in the log file. Just above this
is a line stating the Overflow.
If both numbers in the (#% H) and (#% V) are less than 0.5% (for
3-layer metal), and less than 1.0% (for 5 or more layers), then this
design is routable. Evaluate the routability according to the layer
routing constraints (routing restricted to 4 layers) that you have set
for Trial Route.
Is this design routable?
Answer: ____________________________
5. Turn off the Trial Route Markers by selecting All Colors.
6. Select the View-Only tab.
7. Unselect Congestion, Congestion Label, Horizontal Congest, and

Vertical Congest.
8. Close the Color Preferences form.
Saving the Design
1. Save the session by choosing File– Save Design.
2. Enter routed.enc in the file name field and click OK.

You can restore your work in a future session by choosing
File–Restore Design and specifying routed.enc as the file name.
Viewing a Design After a Trial Route
1. Make sure that you are in the Physical view.
2. Turn on Net visibility if it is off.
3. Zoom in to see the routes.
4. Unselect the Std. Cell selectibility.
5. Select a net.
6. Press F12 to dim the background so that you can see the net better.
7. Double-click on the net to bring up the Attribute Editor and view its 2
properties.
What is the name of the net?
Answer: ______________________
Which layer is the selected net on?
Answer: ______________________
8. Close the Attribute Editor.
9. Deselect the net by clicking in any empty space.
10. Reset the visibility by pressing the F12 key twice.
11. Choose Tools–Design Browser.
12. Change the Find cyclic field from Instance to Net.
13. In the Design Browser, enter the net name:

DTMF_INST/TDSP_CORE_INST/MPY_32_INST/n_334
14. Press Return.
15. Select the net in the Design Browser.
16. Click the Select icon in the Design Browser.
17. This choice selects the net in the Physical view.
18. Verify that the net is selected by looking at the SelNum value on the
lower right corner of the design window.
19. Select the Zoom Selected icon in the Design Browser form to see
this net.
You might have to zoom further into this area to finally see this net.
20. To see better, dim the background by pressing F12. You can get
back to the original display by pressing F12 again.
21. You can see all the color assignments for the metal layers by
clicking the All Colors button and the Wire/Via tab.
22. Fill in the colors for the layers below:
Metal Layer Metal Color
Metal1 _________
Metal2 _________
Metal3 _________
Metal4 _________
Metal5 _________
Metal6 _________
Note: By default, Trial Route does not use metal1. You can force the
trial router to use metal1 by entering this command:
trialRoute -useM1
23. Save the design and enter pr.enc for the filename.
24. Do not close the software.

If you do close the software you can restore the design from the
pr.enc file that you saved in a previous step.
Summary
In this lab, you ran placement and trial routing. You also analyzed the
congestion after trial routing and determined the routability of the design.
End of Lab
Labs for Module 3
Extraction, Timing Analysis, Optimization,

and CTS
Lab 3-1 Extracting RC Data
Lab 3-1 Extracting RC Data
Objective: To extract parasitics based on Trial Route.
In this lab, you extract RCs (resistance and capacitance). They are a
prerequisite for running timing analysis.
1. (Skip these steps if you did NOT close Encounter® DI.)

If you did close the software before starting this lab, restart the
software.
a. Restore your design by choosing File – Restore Design.
b. Enter your previously saved pr.enc file.
2. (Skip these steps if you completed the previous lab.)

If you did not complete the previous lab, change to the work
directory.
cd work
a. Copy the file pr.enc and the directory pr.enc.dat from the saved
directory to the work directory.
cp -R ../saved/pr.* .
b. Restart the software.
c. Restore the pr.enc file.
3. To run extraction, choose Timing–Extract RC.
4. Unselect the Save cap to button and click OK.
Note: For the purposes of this lab, don’t save any files, because the
generated files will be very large. The extracted RC
information is annotated in the design database.
Notice that the status of the design on the bottom right corner
changes from Routed to RC Extracted.
Extracting RC Data Lab 3-1
Calculating Delays
Next, delays are calculated for the interconnect wires and include instance
delays.
1. Choose Timing – Write SDF.
a. Select Ideal Clock if it is not selected, because you have not yet
run clock tree synthesis on the design.
b. Click OK.
The command creates a file in SDF format.
2. To see what the default delay for the large nets has been set to,
choose File – Import Design.
a. Click the Advanced tab.
b. Make sure that Timing is selected on the left side.

What do the parameters in the fields signify?
Answer: ___________________________
Tip: Refer to the Lecture book for more information.
3. If you do this step, click Cancel to avoid importing the design again.
End of Lab
Lab 3-2 Running Timing Analysis and Generating a Slack Report
Lab 3-2 Running Timing Analysis and Generating a

Slack Report
Objective: To analyze timing and display violating paths.
After extracting parasitics, run timing analysis to generate timing reports.
1. Choose Timing – Report Timing.

The Timing Analysis form opens.
2. In the Timing Analysis form, make sure that the Pre-CTS option is
selected because you have not yet created a clock-tree for the design. Note: The Pre-Place option
considers a zero wire-load model
The Setup option is selected (default), because we are interested in while ignoring high-fanout nets.
generating reports for setup under worst-case conditions. This option is useful to check if
there are any errors in your
The timing reports will be saved to the directory specified in the constraints file prior to running
Output Directory field. placement for the first time.
3. Run timing analysis for setup by clicking OK.
Running Timing Analysis and Generating a Slack Report Lab 3-2
4. After running the analysis, view the slack report by choosing

Timing–Debug Timing.
This command brings up the Display/Generate Timing Report form.
5. Click OK.
The Timing Debug window comes up.
How many failing paths do you have in the design?
Answer: ______________________________________
What is the Worst Negative Slack (WNS) and the Total Negative
Slack (TNS)?
Answer: ____________________________________
6. Double-click one of the failing paths in the Path section of the

Timing Debug Window. 2
The selected path is highlighted in the Design window.
This choice will also display the Timing Path Analyzer with more
details in the path.
7. Close the Timing Path Analyzer window by clicking the X at the top
corner of the window.
8. Close the Global Timing Debug Tool by closing the window.
End of Lab
Lab 3-3 Running Timing Optimization
Lab 3-3 Running Timing Optimization
Objective: To run timing optimization to close timing.
Now you can run optimization to fix setup violations.
1. Choose Optimize – Optimize Design.

The Optimization form opens.
2. Because you have not yet run clock tree synthesis (CTS), make sure
that the pre-CTS button is selected.
3. Click the Mode button.

The mode setup form appear.
a. Make sure that the Max Density is 0.95.

This setting limits the increase in area due to the addition of
buffers during optimization.
As a recommendation, begin with a Core Utilization that is
approximately 5% lower than the final utilization.
Running Timing Optimization Lab 3-3
b. Click OK to run optimization.
4. After optimization has finished, update the timing debug display by

selecting Timing–Debug Timing.
This command displays the Timing Debug window.
5. Select the file folder icon next to the Report File(s) parameter.
This option brings up the Display/Generate Timing Report Form.
6. Click OK to regenerate the timing report file and to update the

timing display.
Did you close timing with a resulting positive slack?
Answer: ______________
7. When the optimization has finished, view the log file.

Compare the worst post-optimization slack to the pre-optimization
slack.
8. Save the design.
a. Make sure that you save the file in the work directory and not in
the timingReports directory.
b. Choose File – Save Design.
c. Enter preCTSopt.enc for the file name.
End of Lab
Lab 3-4 Running Clock Tree Synthesis
Objective: To run clock tree synthesis with a clock specification

file.
After running placement or pre-CTS optimization, you run clock tree

synthesis, which requires a clock specification file. This file specifies target
skews, insertion delay and transition times for the clocks in your design.
1. Generate a CTS spec file from the .sdc file by selecting

Clock – Synthesize Clock Tree.
This command displays the Synthesize Clock Tree form.
2. Click Gen Spec.

This button displays the Generate Clock Spec form.
3. Select the cells that start with CLK by selecting the first one on the
list.
4. Scroll down and hold down the shift key.
5. Click the Add button.
6. Enter dtmf_generate.cts in the Output Specification File field.
7. Click OK to generate the clock specification file.
8. In the Synthesize Clock tree form,
a. Make sure that in the Clock Specification File, the following is

specified:
dtmf_generate.cts
Running Clock Tree Synthesis Lab 3-4
b. Click OK to start clock tree generation.
c. This step takes a few minutes to run.
Viewing Clock Tree Results
1. Make sure that you are in the Physical View.
2. Turn off the visibility of the nets.
3. Choose Clock–Display–Display Clock Tree.
4. In the Display Clock Tree form, select the Display Clock Tree and
All Level buttons.
5. Click Apply.
In the Physical view window, the clock tree is highlighted in yellow.
6. Select Display Clock Phase Delay.
7. Click OK.
8. Zoom in to any area that contains a highlighted area and you see
multicolored instances.
Note: These colors represent the different insertions delays for the
leaf cells. The color coding is Red (most delay), orange,
yellow, green, blue-gray, blue, and purple (least delay). The
clock segments do not represent the entire clock tree. They
represent segments of the tree that are connected to the leaf
cells.
9. To clear the display, select

Clock–Display–Clear Clock Tree Display.
The clock tree reports are written to the clock_report directory.
The clock tree synthesis report is written as ASCII files.
10. View the clock.report file in the clock_report directory.

Were all clock constraints met?
If not, which constraints were not met?
Answer: ________________________
11. Display the detail routed clocks by first deleting the trial routes in
the design by entering the following command:
dbDeleteTrialRoute
12. Make sure that Std. Cell and Net are visible under All Colors.
13. Then, choose Clock – Display – Display Clock Tree.
a. Select All Clock(s).
b. Select Post-Route.
c. Select Display Clock Phase Delay.
d. Click OK.
e. Zoom into where you see highlighted leaf cells.

Notice that there are clock routes in the design.
14. Save the design by choosing File – Save Design and entering this
file name:
clock_tree_syn.enc
15. To further analyze the clock tree, select

Clock – Debug Clock Tree.
16. This will bring up the Clock Initialization form.
17. Select Add All.
18. Select Post-CTS
19. Click OK
The Global Clock Debug Tool will be displyed.
20. The left pane contains details about the clocks in your design. You
can expand the levels to display additional information.
As you explore the details, notice that some of the clocks seem to be
driving too few flip-flops. If this were a real design, you would go
back to the SDC file and debug why these clocks are defined in this
way and determine if there is an error that must be corrected.
21. Choose Tool – Find Object.
22. In the Object Type field, select Cell.
23. In the Name Pattern field enter CLK*.
24. Select In All Clocks.
25. Click Find.

This will display a list of instances in the clock tree that contains the
clk string.
26. In the Clock Tree Debug form, choose

Clock – Refresh Clock Data.
27. Double-click DTMF_INST/TEST_CONTROL_INST/i_150/Y in

the left pane.
28. Choose Tool – Find Object
29. Select Min/Max Path for the Object Type
30. Click Find
31. Click the highlight icon.
Notice that the min path is highlighted in green and the max path is
highlighted in red.
32. The right pane contains the root, timescale, and the number of
flip-flops. Move your mouse over the objects in the right hand pane
to display the names of the drivers, the leaf cells and their skew and
delay values.
33. Explore the clock tree analyst and close it after you are finished.
The clock uncertainty value in the dtmf.sdc file includes both jitter and
insertion delay. Because you have a clock tree now, the actual insertion delay
will be taken into account by the timing analysis tool. Therefore, you need to
reduce the clock uncertainty number in the constraints file and leave in the
jitter value.
34. To change the set_clock_uncertainty_value from 0.25 to 0.18,

complete the following steps at the Encounter prompt:
set_interactive_constraint_modes \
[all_constraint_modes -active]
set_clock_uncertainty 0.18 -from [all_clocks] \
-to [all_clocks]
35. Run timing analysis in post-CTS mode by running the following

command:
timeDesign -postCTS
Is your slack negative or positive?
Answer:
What is your slack at this point in time?
Answer: ________________________________
36. If you have a negative slack run post-CTS setup optimization by

entering:
optDesign -postCTS
37. Now run hold time analysis by entering:

timeDesign -postCTS -hold
Is your slack negative or positive?
Answer:
What is the slack in your design?
Answer: ________________________________
38. If you have hold violations (negative slack), run optimization for
hold.
What is the slack after optimization?
Answer: ________________________________
If you have hold violations after running hold optimization, then
routing the design might improve or fix the negative slack. In later
labs, you will route the design and rerun hold checks to see if you
still have violations.
39. Save your design as postCTSopt.enc.
40. Close the session.
Summary
In this lab, you extracted parasitics, ran timing analysis, and ran an
optimization. After optimization, you ran clock-tree synthesis to create a
clock tree in your design. You reran timing analysis to check if there are any
post-CTS timing violations. When you had violations, you reran optimization
to improve timing.
For a specific floorplan, you quickly got relatively accurate feedback on the
timing of the design.
End of Lab
Labs for Module 4
Generating Scale Factors for Extraction

Lab 4-1 Extracting and Generating Scale Factors
Lab 4-1 Extracting and Generating Scale Factors
Objective: Extract the RCs in the design using both the sign-off
and built in extractors and generate scale factors.
To generate scaling factors by running the generateRCFactor command on a

routed design for better correlation between the built-in extractor and a
sign-off extractor.
Loading the Design
1. Verify that your working directory is set to

FPR/work
2. Start the software by entering this command in a csh window:

encounter
The software will start up after a short time.
3. In the graphical interface, load the design which has been detail
routed by choosing File – Restore Design and specifying this file:
routeExtract.enc
4. Click OK to load the design.
Extracting and Generating Scale Factors Lab 4-1
Generating Scale Factors with External SPEF File
1. Run the generateRCFactor command to generate the scale factors

for preRoute and postRoute scale factors by running the following
command:
generateRCFactor -spefIn signoff.spef -postRoute medium
What are the scale factors that were generated for:

PreRoute Cap scale factor ________
PreRoute Res scale factor ___________
PostRoute Cap scale factor (medium)________
PostRoute Res scale factor (medium)___________
PostRoute XCap scale factor (medium)__________
Note: In order to set the scale factors you can either modify the
create_rc_corner defaults in the dtmf.view file or run the
setRCFactor command.
2. Close the Encounter software.
Summary
In this lab, you
■ Ran the generateRCFactor command to generate scale factors for

better correlation of native extraction with signoff extraction.
End of Lab
Labs for Module 5
Power Analysis
Lab 5-1 Running Power Analysis
Objective: To run early power analysis and view the IR drop on

power lines.
Starting the Software
1. Change to the working directory by entering:

cd FPR/work
2. Start the Encounter® Digital Implementation system by entering:

encounter
The software appears.
Importing a Design
1. Import a gate-level netlist, timing constraints, and libraries by

choosing File–Import Design.
The Design Import form comes up.
Load the configuration file for this lab.
a. Click the Load button, select the dtmf.conf file, and click Open.
This file populates the fields in the Design Import window.
b. Click OK on the Design Import form to load the design and

libraries.
Loading a Floorplan
1. Load the dtmf_power.fp file by choosing File–Load–Floorplan.
2. Source the power_globals.tcl file.

source power_globals.tcl
The commands in the script enable the power router to connect the
VDD and VSS global nets to the power and ground pins of the
components in the design.
Running Power Analysis Lab 5-1
Running Placement and Trial Route
1. Run placement by choosing Place – Place Standard Cells using

default options.
2. Select All Colors.
3. Select the View-Only tab and turn off Congestion Label,

Horizontal Congest, and Vertical Congest.
4. Choose Route–Trial Route using Medium effort.
Extracting RC Data
1. Extract RC by choosing Timing– Extract RC.

To save disk space, you can deselect Save Cap. You don’t need to
save this information to a file, because it is sufficient that the
extraction is done and the status of the design is changed from
Routed to RC Extracted.
Setting the Power Analysis Mode
1. Choose Power – Power Analysis – Setup.

You will run Static Power Analysis with defaults selected.
2. Click OK.
3. Choose Power – Power Analysis – Run.
4. Change the Dominant Frequency from 100 to 200 MHz.
5. Click OK.
6. View the DTMF_CHIP.rpt file.

What is the total internal power?
Answer: ___________
What is the total switching power?
Answer: ___________
What is the total leakage power?
Answer: ___________
What is the total power?
Answer: ___________
Running Early Rail Analysis
1. Click the Physical View icon to display the Physical view.
2. Unselect net visibility under All Colors.
3. Choose Power–Rail Analysis–Early Rail Analysis.

This command displays the Early Analysis form.
4. Enter VDD in the Net Name field.
5. Enter dtmf.vdd.pp in the Pad Location File parameter.

These VDD pad locations where there are 0 IR drops are reference
points defined in the dtmf.vdd.pp file.
6. Click OK.
Viewing Power Analysis Results
1. After the power analysis tool runs, the Power and Rail Analysis
Results form appears.
2. The filter ranges displayed in the form are organized from the
highest drop (in red) to the lowest drop (green).
3. Click Apply.
What are the primary colors and corresponding ranges of your IR
drops?
Answer: ____________________________________________
4. Change the filter range by by entering 1.59 for min and 1.62 for max.
5. Press the Auto button.
6. Click Apply to view the IR drop display.

The software displays a different IR drop map than before. By
narrowing the filter range, you will see a more dramatic IR drop
map.
Are there any violations displayed in the Rail Analysis Violation
Browser?
Answer: __________________________________________
Summary
In this lab, you ran and viewed the power and IR drop analysis of the
Encounter software.
End of Lab
Labs for Module 6
Routing and Optimizing the Design

Lab 6-1 Routing Critical Nets with Shielding and Spacing
Lab 6-1 Routing Critical Nets with Shielding and

Spacing
Objective: To specify critical nets for shielding, and to route and

optimize the design to meet timing and signal
integity.
Certain critical or high speed nets require shielding or spacing from other
nets. In this lab, you specify attributes to shield those nets and to assign the
nets used for shielding. You will also set up extra spacing for a particular net.
You typically want to route these nets and shields before routing any other
nets.
Loading the Design
1. Verify that your working directory is set to

FPR/work
2. If you did not save your design at the end of Lab 3, copy a saved
design that has been placed and in which the clock tree has been
synthesized.
cp -R ../saved/postCTSopt.enc* .
3. Start the software.
4. Open the postCTSopt.enc design.
Setting Shielded and Spacing Net Attributes
1. In the csh Encounter® window where you started the software, enter
this command at the encounter prompt:
setAttribute \
-net DTMF_INST/TDSP_CORE_INST/read_data \
-shield_net VDD
The actual shielding will take place in a later step.
Routing Critical Nets with Shielding and Spacing Lab 6-1
2. In the same csh window, check the attributes that you set for the
read_data net by entering:
getAttribute -net \
DTMF_INST/TDSP_CORE_INST/read_data
Is the read_data net going to be shielded?
Answer: __________________________
If so, with what net will be used for shielding?
Answer: __________________________
3. Set the net attributes to add space around a critical net (clk) by
setAttribute -net DTMF_INST/clk \
-preferred_extra_space 2
The router will add extra tracks of spacing around the net if the
design is not overly congested.
Routing the Nets
You will route the shielded net first. After routing the shielded net, you will
route the spaced net along with the remaining nets. The power nets will be
connected using default width wires to other prerouted power nets.
1. In the csh Encounter window, select the net that you will be
shielding by entering:
selectNet DTMF_INST/TDSP_CORE_INST/read_data
Make sure that you are in the Physical view.
2. Choose Route–NanoRoute–Route to route the selected net.

The NanoRoute form appears.
a. In the Concurrent Routing Features section, turn on the

Timing Driven button.
b. In the Routing Control section, turn on Selected Nets Only.
c. Click OK.
3. Make sure that you are still in the Physical View.
4. If the read_data net is selected in the Physical View, zoom to

examine the shielding that is connected to VDD.
Is the VDD shielding on one side or on both sides of the read_data
net?
Answer: __________________________
5. If the read_data net is not already selected, choose

Tools – Design Browser.
The Design Browser form appears.
a. In the form, change the object from Instance to Net.
b. Type *read_data* in the field.
c. Press Return.
d. Select the net in the Design Browser with the left mouse button
and click the Zoom Selected icon to highlight the net in the
Encounter window.
e. Zoom in further to examine the net for routing, as well as for

shielding that is connected to VDD. Dim the background by
pressing F12 for better visibility.
6. Keep pressing F12 to get back to the original visibility.
7. Choose Route–NanoRoute–Route to route the remaining nets.

The NanoRoute form appears.
a. In the Routing Control section, turn off the Selected Nets Only
option before starting the router.
b. Make sure that Timing Driven is selected.
c. Select SI Driven.
d. Click OK to start the router.
8. View the log file for the current session to determine if there were
antenna violations that have been fixed during Search and Repair.
9. Run setup timing analysis in postroute mode and include the effects
of SI.
a. Click OK.
Are there any timing violations?
Answer: _________________
10. If there are were timing violations, you would run the following
commands for optimization and timing analysis:
setSIMode –analysisType default
setDelayCalMode –engine default –siAware true
optDesign –postRoute
optDesign –postRoute –hold
setDelayCalMode -engine signalStorm -SIAware
false
timeDesign –postRoute –si
timeDesign –postRoute –si –hold
11. Save the design by choosing File–Save Design and then entering
this file name:
DTMF_detailrouted.enc
Summary
In this lab, you
■ Set options to shield and space critical nets in a design.
■ Routed the critical nets and then the remaining nets.
■ Routed, timed, and optimzed the entire design.
End of Lab
Labs for Module 7
Wire Editing
Lab 7-1 Using the Interactive Wire Editor
Objective: To manually add and modify signal nets.
In this lab, you load a design, set up wire snapping to pins and tracks, and
route with nondefault wires. You also route shielded nets and change the
width of a signal wire.
Loading the Design
1. Change the working directory to

FPR/work/EDIT_ROUTE
2. Start the software by entering this command in a csh window:

encounter
3. Load the design by sourcing a script in the csh Encounter® window:

source loadDesign.tcl
Locating the Net for Manual Routing
1. Widen the Encounter window to make the Tools menu visible.
2. Find the net you will be hand routing by choosing Tools–Design

Browser.
Using the Interactive Wire Editor Lab 7-1
3. In the Design Browser, click the + next to Modules, and then

IOPADS_INST.
4. Expand Pads to see the list of I/O pads.
5. Select the Prefclkip instance by clicking the name, then use the
Zoom Selected icon in the Design Browser window to view the
instance.
6. Click the Highlight button to highlight the cell.

The cell will be highlighted in red.
The net that you will route connects the pin in the lower right corner
of the I/O instance to the PLLCLK_INST block.
7. With the left mouse button, draw a box around the Prefclkip pad.
You will see the connectivity of the pin on the pad to the pin on the
PLL.
8. Click and drag the right mouse button to zoom to the point where
you can see both the pad pin and the PLL pin for this net.
This view lets you determine an optimal route for the net.
9. Again, click and drag the right mouse button to zoom an area near
the PLL block pin where you can see the pin and the nearest stripe
to its left.
Using the Wire Editor
1. Make sure that you are still in the Physical View.
2. Make sure that the Instance Pin visibility button is selected.
3. Turn off the Special

Net visibility button.
Bindkeys for the Wire Editor
Bindkey Description
A Starts the Add Wire mode. The cursor turns into a

pencil. Click left to add wires if the Nets field has a net
in it.
d Opens the Select/Delete route form.
e Brings up Edit Route form.
n Selects the Next Auto Query object (in Query mode
only).
p Selects the Previous Auto Query object (in Query mode
only).
S Selects the current Auto Query object and seeds the Nets
tab's Nets field and the Route tab's Layer and Width
fields in the Edit Route form (in Query mode only).
u Changes wire to next higher layer (in Add Wire mode).
d Changes wire to next lower layer (in Add Wire mode).
Control-w Deletes the last wire segment created (Query mode
only).
R Enters non-connectivity move mode.
N (next) or P Displays/replaces a via that has the same LEF rule as the
(previous) selected via
Single Click Ends the current wire segment.
Double Enters current point and stops wire creation.
Click
For a list of all bindkeys and how to add bindkeys, choose
Options–Set Preferences, and then click Binding Key.
4. Zoom in to the pin that you will be routing.
5. With the Encounter window active, press e to bring up the Edit e

Route form.
6. Click the Snap tab to set wire snapping options.
7. Turn off the Snap to Track (Regular).
8. Turn on the Snap to Pin command and set Alignment to Auto.
9. Select the Nets tab on the Edit Route form.
10. Click on an area where there is empty space to set the selection of
objects to 0.
11. Turn on auto query by clicking the Q button in the bottom of the
Encounter graphical interface.
Use this auto query feature to add the net name to the Nets field.
12. Make sure that the Encounter window is the active window and
move the pointer over the refclkI net (connecting to the refclk pin on
the PLL block).
13. Press Shift-s.

This bindkey populates the Nets field in the Edit Route form with
refclkI.
14. Making sure that the cursor is in the Encounter graphical window,
press Shift-a to change the cursor to a pencil for wire A or
editing.
15. Click left on the refclk block pin.

The wire snaps to the center of the pin and follows the cursor.
The LEF file has the widewire rule defined for layers and vias. You
can use this rule by selecting the widewire option in the Rule field
on the Nets tab as in the next step.
16. In the Edit Route Form, under the Nets tab, change the Rule field
from Default to widewire.
You will see a wider wire (defined in the LEF file) coming from the
pin, but you will also see violations. The width of the wire is greater
than the pin size and violates the obstructions that surround it.
17. Now, select the Default Rule.

Notice that the wire width changes back from wide to the default
width.
18. Move the cursor to left (in the horizontal direction) about half way
from the refclk pin to the destination pin by dragging the wire.
The wire segment will be created with a default width wire on M1.
19. Click the left mouse button to complete this segment of the
route.
20. Create a vertical wire on M4. On the keyboard, press 4.

This key starts the new segment for the vertical route on M4.
21. Change the Rule to widewire to route the next segment with a wide
wire in M4.
22. Click the left mouse button to end the M4 vertical route when the
flight line is horizontally even with the I/O pin.
23. This action lets you change to horizontal routing direction.
24. Press 5 on the keyboard to change the layer for the horizontal route
to M5.
25. Finish the route to the I/O pin by double-clicking the left mouse
button near the I/O pin. 2
Because you have previously set the Snap to Pin value to Auto, the
tool will automatically snap to pin C.
26. Press a to get out of the wire edit mode and into select mode. a
27. Press d if you want to delete and reroute the net. d
Replacing a Via in a Design
You can replace a selected via with another, provided they both have the
same LEF rule.
1. Zoom in to see the area where the stacked vias connecting M1 to M4

were placed on the refclkI net that you routed previously.
2. If it is off, turn on auto query by clicking the Q button at the bottom

of the Encounter graphical interface.
3. To select the via to change, draw a box around the via while pressing
the left mouse button at the same time.
4. Press q to bring up the Attribute editor. Confirm that the selected

q
object is the via.
If multiple objects have been selected, click Next on the form to
search for the via.
5. Close the attribute editor.
6. Without moving the mouse, use the N (next) or P (previous) bindkey

to display a via that has the same LEF rule as the selected via.
If a via is available, the display is updated with the new via when you
press the bindkey.
If another via is not available, then you hear a warning beep when
you press the bindkey. This can occur when only one via is defined
in the LEF file, when the currently queried object is not a via, or
when no object is currently queried. In the LEF file used for this lab,
there are two of each of the default vias.
Note: The Edit Route form does not provide access to this feature.
You can only change one via at a time using the bindkeys.
7. Press a to get into select mode. a
Reshaping a Wire
You can use the Cut Wires and Move Wires icons to modify a wire
following routing or editing.
1. Zoom in to an area to see the vertical Metal4 route you completed

earlier.
2. Click the Cut Wires icon.
3. Click and drag at two different places on Metal4 where you want to
create a jog.
You will see overlapping wire segments formed based on where you
made the cuts.
4. Press a to set the select mode. a
5. Select the cut wire segment.
6. Click the Move Wires icon.

The cursor changes from an arrow to a circle.
7. To create a jog, click and drag the Metal4 segment (where you
previously created the cuts). Click again where you want to place the
segment.
The segment and connecting wires are moved while keeping the
route intact.
Forcing the Width of a Signal Wire
In addition to routing a nondefault wire with a wide wire rule defined in the
LEF file, you can also use the Wire Editor to force the width of a wire by
making it a special wire. This procedure lets you specify any width for the
wire.
In this section, assume that you have just learned that the nondefault width
used for the refclkI net was too small. You need to make the width of the wire
the same as the width of the I/O pad pin.
1. Make sure that you are in the Physical view.
2. Delete the refclkI wires by selecting the segments.
3. Press d.
d
This bindkey brings up the Select/Deselect/Delete Routes form.
4. Change Action to Delete.
5. Make sure that Objects is set to Selected.
6. Deselect Type if it is selected.
7. Click Apply.
8. Close the Edit/Delete/Deselect Routes form.
9. Make sure that Special Net under All Colors is Visible and
Selectable.
10. Press e to bring up the Edit Route form. e
11. Select the Nets tab on the Edit Route form.
12. Put the cursor over Pin C on the I/O pad and press Shift-s. S
This action will populate the Nets field and select layers for
horizontal and vertical routing.
13. Turn the Force Special (to allow arbitrary widths) button on.
14. In the Edit Route form, click the Route tab and set the Vertical
Layer to M4 and the width field to 2.0.
15. Select the Snap tab and make sure that the Snap to Pin option is
selected and set to Auto.
16. Make sure that the net name in the Nets field is refclkI.
17. Press Shift-a to change the cursor to a pencil for wire A or

editing.
18. You will start the route by clicking left on the I/O pin to start the
horizontal route.
19. Click left to change directions to vertical.

Notice that the vertical segment’s width is your specified width for
M4.
20. Click left to change the direction to horizontal.
21. Complete the horizontal route to the PLL block pin using default
Metal1 widths.
Tip: Select Layer M1 and Default Rule. Deselect Force Special in

the Nets tab.
22. When you get to the pin, double-click left to end the route.
You may need to click the numeric keys (1, 2, 3, etc.) to select the
2
layers for routing.
23. When you finish, close the software.
Summary
In this lab, you
■ Loaded a design.
■ Manually routed a net.
■ Swapped vias.
■ Modified signal wires.
■ Forced the width of a wire to a nondefault width.
End of Lab
Labs for Module 8
Verifying a Design
Lab 8-1 Using the Verify Commands in a Design
Objective: To use and understand the verify commands to

check design rules.
In this lab, you run different verification options in the Encounter® system.
Loading the Design
1. Make sure that your working directory is:

FPR/work/VERIFY
2. Start the software by entering this command in an Encounter csh

window:
encounter
3. In the csh Encounter window, load the design for power routing by
choosing File–Import Design.
4. Click the Load button at the bottom of the Design Import form.
5. Select the verify.conf file and click Open.
6. In the Design Import form, click OK.
7. Choose File–Load–DEF and select the tdsp_core_routed.def file.

Then click Open.
There will be some ERRORs in the DEF file that have been
intentionally created for this lab.
8. Change the view to Physical View to see the detailed routes.
Using Verify Connectivity
1. Choose Verify–Verify Connectivity.

The form appears.
Using the Verify Commands in a Design Lab 8-1
2. Make sure you are looking at the Physical View. Turn on the
Geometry Loop option, and click OK.
You can also run this from the command line by entering:
verifyConnectivity -geomLoop
Loop problems will be reported.
3. Use the Violation Browser to locate the loop.

Choose Tools–Violation Browser to display the form.
4. If Verify and Connectivity are not expanded, click the + next to

Verify and Connectivity to expand the levels in the browser and to
display the violating nets.
5. Select the violation on net n_4074 and use the Fit Violation icon to
zoom into the violation marker.
You can alternatively zoom into the area which has the x violation
marker.
6. Zoom into the violation to see the loop.
7. Select a loop segment in the Design Window.
8. Use the Select/Delete/Deselect Routes menu to remove the loop.

Use the d bindkey to display the form. d
9. In the Action field, select Delete.
10. In the Objects field, pick Selected.
11. Click Apply in the Select/Delete/Deselect form.

These settings will delete the selected segment.
12. Repeat the Select and Apply steps until all the loop segments are
deleted.
13. After you have deleted the loop segments, click Close in the
Select/Delete/Deselect form.
Using Verify Geometry and the Influence Rule
1. Execute from the Encounter csh command line:

zoomBox 330 610 360 640
2. Choose Verify–Verify Geometry.
a. Click the Specify option.

Now you will debug errors in the vicinity of the current view area.
b. Click the View Area option, and click Apply.

How many Geometry violations are flagged?
Answer: ___________________________
Note the spacing violations. The corresponding LEF INFLUENCE
SPACING rule is:
WIDTH 4.50 WITHIN 1.50 SPACING 1.50 ;
The influence spacing rule is applied to all shapes within the halo
around the wide wire object (within distance 1.50 µm). The halo
extends in orthogonal directions only, and does not include the
corners. Any two shapes within the halo require extra spacing
between them (1.50 µm) if the shapes have a combined projected
run length onto the wide wire of greater than 4.50 µm.
3. Close the Verify Geometry form and the Encounter window.
Summary
In this lab, you
■ Loaded a design with design rule violations.
■ Used the Verify flow to find and fix violations.
■ Observed how the Influence rule in LEF is checked in

verification.
End of Lab
Labs for Module 9
Running the ECO Flow

Lab 9-1 Loading a Design for ECO Routing
Lab 9-1 Loading a Design for ECO Routing
Objective: To start the Encounter software, input the required

files, and implement an ECO using a Verilog file.
Getting Started
1. Make sure that your working directory is set to:

FPR/work/ECO
2. Compare the tdsp_core.v and tdsp_core_eco.v files.

The tdsp_core.v file is the original netlist. In the tdsp_core_eco.v
file, the instances connected to the p_data_out[15] and
p_data_out[14] nets have been swapped. Search for instances
i_5324 and i_5331 to find the nets.
Implementing an ECO in the New Netlist with a Design
1. Start the Encounter® software by entering:

encounter
2. In the Encounter® csh window, run the ecoDesign command to read

in the original design, read the new Verilog® file, and implement the
ECO.
ecoDesign tdsp_core.enc.dat tdsp_core tdsp_core_eco.v
The tdsp_core.enc.dat is the design corresponding to the original

tdsp_core.v netlist. The tdsp_core_eco.v file contains the required
ECO that will be implemented. The ecoDesign command will route
the changes in the netlist.
3. Write out a new DEF file, tdsp_core_routed_eco.def.
4. Run the following command to compare the original DEF file

tdsp_core.def (which corresponds to the original Verilog Netlist) to
the current, changed, EDI ECO database:
ecoCompareNetlist -def tdsp_core.def -outFile \
ecoFile
Loading a Design for ECO Routing Lab 9-1
5. View the ecoFile and verify the connections have been changed.
If this was a production design, you would continue with the
postroute flow if you want, including timing and signal integrity
analysis, repair, metal fill, and verification.
6. Close the software by choosing Design–Exit.
Summary
In this lab, you
■ Loaded a placed design
■ Ran an ECO and generated a routed design
End of Lab
Labs for Module 10
Database Commands
Lab 10-1 Using the dbGet and dbSet Commands
Objective: To report and change the EDI database by using the

dbGet and dbSet commands.
Getting Started

FPR/work
2. Start the Encounter® platform by entering:

encounter
3. Restore a previously stored design preCTSopt.enc from your current

directory. You can restore any other saved design instead of
preCTSopt.enc.
4. In the Encounter csh window enter the following:

help dbGet
This will return the command-line options of the command. The
usage is:
Usage: dbGet
dbGet
[-p | -<p_number>]
[-u]
[-regexp]
[-d]
{<objectList> | head | top | selected}
[.<object_type>]*
[.<attribute_name> | .? | .?? | .?h]
[<pattern>]
[-help]
Using the dbGet and dbSet Commands Lab 10-1
5. Select head from the attributes that are available at this level and
enter:
dbGet head.?
This command returns the attributes that are available at this level.
The attributes are:
head: allCells dbUnits layers mfgGrid objType
props ptns rules vias
6. Some interesting attributes at this level are dbUnits and mfgGrid. To

report the values, enter the following commands:
dbGet head.dbUnits
What is the value that is returned?
Answer: __________________
7. Enter the following command:

dbGet head.mfgGrid
What is the value that’s returned?
Answer: __________________
8. List all the attributes and their values by entering the following:
dbGet head.??
The results might not always be readable text, as in this example.
9. To list the layers, enter the following command:

dbGet head.layers
But, this command returns a hex representation of the layer names.
10. To display text, enter the following command:

dbGet head.layers.?
The name attribute displays the text.

dbGet head.layers.name
What does this command return?
Answer: ___________________
12. To get to the top level of the hierarchy, enter the following
command:
dbGet top.?
13. This lists all the attributes that you can query.
topCell: bumps fPlan hInst insts markers name
nets numBidirs numInputs numInsts numNets
numPGTerms numPhysInsts numPhysNets numPhysTerms
numTerms objType pgTerms physInsts physNets
physTerms pinToCornerDist props
statusClockSynthesized statusGRouted
statusIoPlaced statusPlaced statusPowerAnalyzed
statusRCExtracted statusRouted statusScanOpted
symmetryR90 symmetryX symmetryY terms texts
Try out different attributes and think of examples of how you can
use the results in scripts, or just to query the attributes of your design
and check a few things.
14. Select ROM_512x16_0_INST in the design window.

dbGet selected.?
This command returns the following attributes:
inst: box cell instTerms isDontTouch isHaloBlock
isJtagElem isPhysOnly isSpareGate name objType
orient pStatus pgCellTerms pgTermNets pt
16. Report the size of the halo on the right of the block by entering the
following command:
dbGet selected.pHaloRight
What is the value that is returned?
Answer: ___________________
17. Change the size if the halo around the block by entering the
following:
dbSet selected.pHaloRight 5
18. Refresh the Encounter design window to view the change.
Using the dbGet and dbSet Commands Lab 10-1
19. Now query some of the properties of the selected instances, by

dbGet selected.pgTermNets.?
20. Explore the attributes and properties that are returned and change
them.
21. Save the design as preCTSopt_db.enc.
Summary
In this lab, you ran the db commands to report and modify the attributes of
the design and its objects.
End of Lab
Labs for Module 11
Generating and Running the Foundation

Flow Scripts
Lab 11-1 Generating and Running the Foundation Flow Scripts
Lab 11-1 Generating and Running the Foundation Flow

Scripts
Objective: To start the Encounter platform, generate

foundations flow scripts, and run a design through a
part of the flow.
Getting Started

FPR/work/FF
2. Start the Encounter® platform by entering:

encounter
Generating and Running the Foundation Flow Scripts Lab 11-1
Running the Foundation Flow Wizard
1. Start the Foundation Flow Wizard by slecting Flows - Foundation

Flow Wizard
2. Make sure that Start from Scratch is selected.
3. Click Continue
4. Enter in the process node and LEF technology file name:
5. Enter 130 for the process node
6. Enter ../../lef/all.lef for the technology LEF file. In this example, the
technology part of the LEF file and the Physical LEF models for the
standard cells and macros are contained in one file.
7. Click Continue.
8. Review the setup and click Continue.

This will brign up the Setup your Design Netlist and Floorplan form
9. Click the file navigator icon next to the field which will contain the
paths and the names of the Verilog netlists.
Thie will bring up the form which you will use to navifate the
directory structure and select the Verilog files.
10. Click the arrows next to Add
11. In the right hand pane navigate up and into the verilog directory.
12. Double click the files dtmf_chip_ak.v and stubs.v
13. Make sure that the two files appear in the left hand pane.
14. Click Close
15. Make sure the Verilog field is populated:
16. Enter DTMF_CHIP in the Design Name field.
17. Enter ../dtmf.fp in the Use the floorplan file field...
18. Specify VDD in the Power Net Name field
19. Specify VSS in the Ground Net Name field
20. Click Continue
21. This will bring up the Setup your Clock Tree Synthesis Constraints
form
22. Select Use my clock tree spec file.
23. Enter dtmf.cts in the Use my spec file field.
24. Click Continue

This will bring up the form Review your design setup.
25. Make sure that the information that you see is correct
26. Click Continue
27. This will bring up the form Setup your design for Timing-driven
Place and Route
28. Leave the default selections as-is and click Continue.

This will bring up the Create Timing Library Sets form
29. Right click Library Sets to create a new Library set
30. This will bring up the Add Library Set form
31. In a separate xterm window run the following commands:

cd work
vi dtmf.view
You will be using the parameters specified in the dtmf.view file as a
reference to complete the next few steps.
32. In the Add Library Set form, create a new library set called
dtmf_lib_max
33. Use the navigation icons to populate the fields with the *slow*.lib
files and the slow.cdb file.
Refer to the .lib files and .cdb file specified for the dtmf_lib_max
library set in the dtmf.view file to make sure that you select all the
files associated with the dtmf_lib_max parameter.
34. Click OK in the Add Library Set Form.
35. Create another library set by right clicking on Library Sets.

This will bring up the Add Library Set form.
36. Enter dtmf_libs_min in the Name field.
37. Use the navigation icons to populate the fields with the *fast*.lib
files and the fast.cdb file.
38. Expand the library sets and check your setup
39. Click Continue

This will bring up the Create RC Extraction Corners form
40. Right click RC Corners to create a new corner
41. This will bring up the Add RC Corner form
42. Enter dtmf_rc_corner in the Name field
43. For the Cap Table File field, navigate to or enter in the following:
../../captable/t018s6mlv.capTbl
44. Leaving all other fields as-is, click OK
45. Expand the dtmf_rc_corner field and make sure that you see the
following:
46. Click Continue.

This will bring up the Create Delay Corner Sets field.
47. Click the OFF button next to dtmf_libs_max.

This will bring up the Add Delay Corner Form.
48. Enter dtmf_corner_max in the Name field.
49. Click OK.
50. Click the OFF button next to dtmf_libs_min
51. Enter dtmf_corner_min
52. Click OK
53. Click Continue

This will bring up the Create Constraints Mode form
54. Right click Constraint Modes
55. Enter common in the Name field
56. Use the Navigate icon to find the ../dtmf.sdc file.
57. Click OK
58. Click Continue

This will bring up the Create Analysis Views form
59. Click one of the two OFF buttons that you see.
This will bring up the Add Analysis View form
60. If the delay corner in the form is dtmf_corner_max, the, enter

dtmf_view_max to the Name field.
61. Click Add to setup Analysis Views
62. Click Set Active
63. Click OK
64. If the delay corner in the form is dtmf_corner_min, the, enter

dtmf_view_min to the Name field.
65. Click Add to hold Analysis Views
66. Click Set Active
67. Click OK
68. Click Continue
69. Review your setup
70. Click Continue.
71. In the interest of time, you will be leaving in defaults in the Setup
Your Power form.
72. Click Continue
73. Click Continue again

This will bring up the Set up Tool Specific Options form.
74. Click Continue
75. Click Continue to skip selecting the plug-ins.
76. Click Done.
77. Click OK to save all your inputs to the setup.tcl file.
78. Exit the Encounter tool

Now you will use the generated setup.tcl to generate Foundation
Flow scripts.
79. Run the following command:

tclsh SCRIPTS/gen_flow.tcl -d . all
80. This command will use the Foundation flow code generator to
generate the scripts required for implementation as well as the
Makefile
81. View the Makefile.
82. Run the follwing command to run EDI placement:

make place
What is the slack?
Answer:
83. Run the following command:

make prects
What is the slack?
Answer:
What are the other implementation steps that you can run through
the Makefile?
Answer:
84. If time permits, run additional make commands and record the slack.
Summary
In this lab, you
■ Used the foundation flow wizard to create a setup.tcl file
■ Used the setup.tcl file and the Foundation flow code generator to
create scripts and ran though parts of the implementation flow
End of Lab

Encounter

Hochgeladen von

Dokumentinformationen

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Encounter

Hochgeladen von

Copyright:

Verfügbare Formate

Floorplanning, Physical Synthesis,

and Place and Route (Flat)

Allegro® Incisive® Silicon Express™

Module 1 About this Course

Lab ii-1 Locating Cadence Online Support Solutions................................................................... ii-1

Module 2 Design Import and Floorplanning

Lab 1-1 Importing a Design .......................................................................................................... 1-1

January 29, 2010 Cadence Design Systems, Inc. iii

Module 3 Placement and Trial Route

Lab 2-1 Running Placement .......................................................................................................... 2-1

Module 4 Extraction, Timing Analysis, Optimization, and CTS

Lab 3-1 Extracting RC Data .......................................................................................................... 3-1

Module 5 Generating Scale Factors for Extraction

Lab 4-1 Extracting and Generating Scale Factors......................................................................... 4-1

Module 6 Power Analysis

Lab 5-1 Running Power Analysis ................................................................................................. 5-1

Module 7 Routing and Optimizing the Design

iv Cadence Design Systems, Inc. January 29, 2010

Module 8 Wire Editing

Lab 7-1 Using the Interactive Wire Editor .................................................................................... 7-1

Module 9 Verifying a Design

Lab 8-1 Using the Verify Commands in a Design ........................................................................ 8-1

Module 10 Running the ECO Flow

Lab 9-1 Loading a Design for ECO Routing ................................................................................ 9-1

Module 11 Database Commands

Module 12 Generating and Running the Foundation Flow Scripts

January 29, 2010 Cadence Design Systems, Inc. v

vi Cadence Design Systems, Inc. January 29, 2010

Mouse Use and Terminology

Term Action Icon Example

click Quickly press and release the specified mouse button.

double-click Rapidly press the specified mouse button twice.

Shift-click Hold down the appropriate key or keys and click a

pop up Press the middle mouse button.

Enter Type a command in a window and press Return to

1/12/11 Cadence Design Systems, Inc. vii

viii Cadence Design Systems, Inc. 1/12/11

About this Course

Objective: To log in to Cadence Online Support (COS) and

1. In a web browser, enter

2. Log in to Cadence Online Support with your email and password.

The Support Home page appears.

a. All Document Types

4. In the Search field, enter congestion click SEARCH.

5. In the Troubleshooting Info section, click the match called:

6. Close the solution window.

7. You can filter the search results by selecting specific document

Note: You can filter the search results by selecting specific

Objective:To set preferences so you can improve search results

2. Click the My Account link.

3. Click the Notification Preferences tab.

4. On the Set Email Notification Preferences page, do the following

a. If you are interested in receiving email notifications, check Send

b. Click Edit Product List and select your products of interest.

c. Specify your preferred email format.

5. Click the Search Preferences tab.

6. On the Set Search Preferences page:

a. Click Use same product and document type preferences as my

Design Import and Floorplanning

Lab 1-1 Importing a Design

Objective: To start the software and import a design.

Starting the Software

1. Change to the working directory by entering this command: