OZ962

High-Efficiency Inverter Controller

FEATURES GENERAL DESCRIPTION
• Single-stage power conversion, input voltage The OZ962 is a unique high-efficiency, CCFL
range of 5V to 18V backlight controller. It generates symmetrical,
• Reduces the number of components and board near sinusoidal output voltage and current
size by 30% compared with conventional design waveforms for driving a CCFL backlight. The
• Supports both floating and grounded secondary OZ962 operates in a single, constant frequency,
designs pulse-width-modulation (PWM) mode. Typical
• 90% efficiency vs. typical 75% efficiency of operating frequency ranges between 30 KHz to
conventional designs 100 KHz, depending on the CCFL and the
• Internal open-lamp and short-circuit protections transformer’s characteristics.
• Wide dimming range
Operating in a PWM push-pull manner, the
• Supports synchronization among multiple
transformer in the OZ962 backlight inverter
inverter modules
requires only one primary winding and one
• Reliable 2 -winding transformer design,
secondary winding, with the secondary winding
eliminates arcing problems
requiring no fold-back treatment.
• Constant frequency, symmetrical, sinusoidal
drive The OZ962 is available in both 16-pin SOIC and
TSSOP packages. It is specified over the
ORDERING INFORMATION commercial temperature range: 0 oC to +70 oC.

OZ962R - 16 lead TSSOP

OZ962G - 16-pin plastic SOP

TYPICAL APPLICATION CIRCUIT

F1
VDD (+12V) 1A Fast Fuse

ENA
+ C1
- 22u R10
GND 25V R5 100
CN1 10K
U1 3 U2 C7
1 16
REF VDD Q2 * *
C8 68p
2 OZ962G 15
0.22u 33T 2200T 3KV
OVP RT
R1 R9 4 C6 2.2u
3 14 3.5W
220K 200K C9 NC CT 5,6 50V
.01u C5 R7 - +
4 13 SI4559EY
SCP CLK 100K R14
220p
R2 5 12 7,8
ADJ ENA 1.0K
10K R6
6 11 30 2
FB NDR
C2 C3 7 10 Q1
R3 0.1u CMP PDR
5.1K 8 1
330p 9
GND SST
C4
0.1u R8
R11 R4 0.5
1M 15K R12
750

R13
100

Figure 1. Typical Floating Secondary Application

Circuit

03/01/00 OZ962-SF-2.7 Page 1

Copyright 1999 by O2Micro All Rights Reserved U.S. Patent #5,619,402
 OZ962

FUNCTIONAL BLOCK DIAGRAM

Ct(14) Rt(15) OVP(2)

Under Voltage RAMP OVP Voltage

OSC OVP NDR(11)
Lockout Generator
OVP=Vref-(Vdd - 1)(12.5/150) Break
VDD(16)
D=1.1(OVP)/2.5 - 0.2 Before N-Clamp
Make

Band Gap PDR(10)

Vref (2.5V)
Reference OSC
REF(1) P-Clamp
S Q
RAMP
R Q

1/2F
Error CLK(13)
Ve
ADJ(5) 40k Amp. Ve=Vcmp-2*(Vcmp-SST-Vgs)
Vcmp

60k
FB(6)
3V 30k
1k SST

CMP(7)
Dmax
Clamp
Vdd
OVP
9k

3µ A 10µA
SST ENA(12)

SST(9) OVP

2.0v OVP
SCP
SCP & OVP inhibited during UVL
2µA start-up shut GND(8)
down
ADJ latch

SCP(4)

Note:
OVP – Over Voltage Protection
SCP – Short-Circuit Protection Figure 2. Functional Block Diagram
UVL – Under Voltage Lockout

OZ962-SF-2.7 Page 2
 OZ962
PIN DESCRIPTION
Names Pin No. I/O Description
REF 1 O Reference voltage output. Nominal voltage is 2.5 V.
OVP 2 I Over-voltage protection setting. Refer to formula for OVP in block diagram
on page 2 of this document.
NC 3 - No connection.
SCP 4 I Short-circuit protection input.
ADJ 5 I Reference voltage input for dimming control.
FB 6 I Current sense feedback.
CMP 7 O Compensation for the current sense feedback.
GND 8 GND Ground.
SST 9 I Tsst ~ 0.2 Csst (Vdd - 5), where Csst is the soft start capacitor value in µF
and Tsst value is in µs.
PDR 10 O Gate drive output for the P-MOSFET.
NDR 11 O Gate drive output for the N-MOSFET.
ENA 12 I Enable input, active high (Vth is about 1.7 V).
CLK 13 O Open-drain clock output.
CT 14 I/O Timing capacitor. CT and RT set the clock frequency.
RT 15 I/O Timing resistor.
VDD 16 PWR Supply voltage input.

ABSOLUTE MAXIMUM RATINGS

VDD 18 V Operating temp. 0 oC to 70 oC
GND +/- 0.3 V Operating junction temp. 150 oC
Logic inputs -0.3 V to VDD+0.3 V Storage temp. -55 to 150 oC
Power dissipation 800 mW at 25 oC

RECOMMENDED OPERATING RANGE

VDD 5V to 18V
Fosc 30 KHz to 100 KHz
Rosc 50 k to 150 k

OZ962-SF-2.7 Page 3
 OZ962
FUNCTIONAL SPECIFICATIONS
Parameter Symbol Test Conditions Limits Unit
5 V < VDD < 15 V Min Typ Max
Reference Voltage
Nominal voltage Vref Iload = 0.25 mA, 2.37 2.50 2.63 V
VDD = 5 V
Line regulation - 8 - mV/V
Load regulation Iload = 0.2 mA to 1.0 mA - 1 - mV/mA
Oscillator
Initial accuracy fosc Ct = 220 pF, Rt = 120 k 48 53 58 KHz
Ramp peak 2.45 2.55 2.65 V
Ramp valley 0.40 0.45 0.50 V
o o
Temp. stability TA = 0 C to 70 C - - 200 ppm/ oC
Error Amplifier
Input bias current V ADJ =V FB =2.0 V - 25 500 nA
Input offset voltage V FB = 4.0 V - 5 10 mV
Input voltage range 0 - VDD- V
1.5
Open loop voltage gain 50 60 - dB
Unity gain bandwidth 1 1.5 - MHz
Power supply rejection 50 60 - dB
Under-Voltage Lockout
Positive-going threshold voltage - 3.8 4 V
Negative-going threshold voltage 3.4 3.6 - V
Supply
Supply current - Enable Low IOFF VDD = 5.0 V - 25 120 µA
Adj, CT = Open
Supply current - Enable Low IOFF VDD = 15 V - 25 120 µA
Adj, CT = Open
Supply current - Enable High ION VDD = 5.0 V - 0.6 1.5 mA
Supply current - Enable High ION VDD = 15 V - 0.6 1.5 mA
NDR output
Output high voltage V OH Isink = 10 mA, VDD- VDD- - V
0.3 0.5
VDD < 7.8 V
VDD >7.8 V 7.0 8.0 9.0 V
Output low voltage V OL Isource = 10 mA - 0.3 0.8 V
Output resistance ROUT VDD = 5.0 V - 50 80 Ω
PDR output
Output high voltage V OH Isink = 10 mA VDD- VDD- - V
0.6 0.3
Output low voltage V OL Isource = 10 mA, 0.4 0.5 0.8 V
VDD < 7.8 V
VDD > 7.8 V - VDD- VDD-
6.0 4.0
Output resistance ROUT VDD = 5.0 V - 50 80 Ω
Break-Before-Make
Qn off to Qp on delay THL 200 240 280 ns
Qp off to Qn on delay TLH 220 260 300 ns

OZ962-SF-2.7 Page 4
 OZ962
PACKAGE INFORMATION

A2 A1

TSSOP-16
PACKAGE

E E1

1
D θ2

R1
Gauge Plane R
b
e
b
θ1
c c1 L
θ3
L1
b1
DIM INCHES MILLIMETERS
MIN MAX MIN MAX
A - 0.043 - 1.20
A1 0.002 0.006 0.05 0.15
A2 0.031 0.041 0.80 1.05
L 0.020 0.030 0.45 0.75
D - - 4.90 5.10
E1 0.169 0.177 4.30 4.50
E 0.252BSC 6.40BSC
R 0.004 - 0.09 -
R1 0.004 - 0.09 -
b 0.007 0.012 0.19 0.30
b1 0.007 0.010 0.19 0.25
c 0.004 0.008 0.09 0.20
c1 0.004 0.006 0.09 0.16
L1 0.039REF 1.0REF
e 0.026BSC 0.65BSC
θ1 0° 8° 0° 8°
θ2 12°REF 12°REF
θ3 12°REF 12°REF

OZ962-SF-2.7 Page 5
 OZ962
DIM INCHES MILLIMETERS
MIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75
A1 0.0040 0.0098 0.10 0.25
SOP-16 B 0.013 0.020 0.33 0.51
E H C 0.0075 0.0098 0.19 0.25
PACKAGE D 0.3859 0.3937 9.80 10.00
E 0.1497 0.1574 3.80 4.00
e 0.050 BCS. 1.27 BCS.
H 0.2284 0.244 5.80 6.20
1 0
D L 0.016 0.050 0.40 1.27
α 0° 8° 0° 8°

α C
A
L
B e A1

OZ962-SF-2.7 Page 6