AN ULTRA-LOW-POWER FOUR-
STAGE CMOS OPERATIONAL
TRANSCONDUCTANCE AMPLIFIER
1
Minhaz Sultana 2Sarin Vijay Mythry ,3D.Chandra Prakash, 4K.Akhil, 5J.Anusha, 6M.Shiva Deepak
1, 2
Faculty 3,4,5,6 Graduate Students
Department of Electronic and Communication Engineering,
Christu Jyothi Institute of Technology & Sciences, Jangaon, Warangal, Telangana State, India
Email:sarinmythry@gmail.com
Abstract: This brief presents four-stage operational
transconductance amplifiers (OTA) suitable for large
capacitive loads. It is based on non trivial frequency
compensation procedure. In this paper a high-
performance OTA is designed by using differential
stage, cascade connection of three common source
stages is demonstrated. The frequency compensation
scheme and the slew-rate enhancer section are able to
drive large capacitive loads of 1fF. It improves the
bandwidth and speed of multi-stage circuits. It uses a
0.13-µm technology, with DC consumption of 346µW.
It also achieves nearly 3-MHz gain bandwidth
product while driving the 1fF load.
Keywords: Frequency Compensation, Multistage
amplifiers, Slew-Rate Enhancer, Folded Cascode
OTA.
I.INTRODUCTION
With the degradation of the transistor's
intrinsic gain in CMOS technologies, multistage
amplifiers have become increasingly developed in
recent years, since they provide high DC gains
without sacrificing output swings. Many modern
applications require high-gain and fast settling
operational transconductance amplifiers (OTAs)
driving large capacitive loads [2] in the order of
hundreds of Ferro farads. In this context the design
of high-gain OTAs driving heavy capacitive loads
is a difficult task, especially when nanometers
technologies are adopted, as they suffer from a
drastic reduction of the intrinsic gain .This can be
only partially satisfied by the adoption of non-
minimum channel length transistors.
The design of multistage amplifiers is also
complicated. In general, classical topologies based
on the nested Miller compensation (NMC) are
area/power inefficient and Reversed nested Miller
compensation (RNMC) topology causes the high-
frequency gain reduction. The single Miller
capacitor compensation network consists passive
components only and is implemented without using
extra transistors, thus saving circuit complexity and
power consumption. The last three stages are
implemented using the simplest common source
stages, thus involving minimum transistors number.
Regardless this simplicity, a class AB behavior is
achieved, further improved by a slew-rate
enhancement (SRE) section that enables large
capacitive loads to be driven.
The paper is organized as follows. The
compensation techniques and implementation of
the circuit are discussed in section II. The
simulation results and output values are reported in
section III. Finally the conclusion is given in
section IV.
II. CIRCUIT IMPLEMENTATION
The most popular and practical approach
is the Miller compensation technique [3]. In this
method, a compensation capacitor CC1 is placed
between the input and output of the fourth stage
amplifier. Stability is improved by exploiting the
phenomenon of pole splitting. Pole splitting has the
effect of pushing one of the two dominant poles to
a lower frequency and pushing the other dominant
pole to a higher frequency. The pole-splitting
principle behind two-stage Miller compensation
can be extended to stabilize op amps of more than
two horizontal gain stages.
A popular multi-stage Miller
compensation technique [4] is the nested-Miller
compensation (NMC) method. In order to obtain
adequate stability margin, the closed-loop
bandwidth must be lower than the second pole by a
certain factor. Since the 𝜔p2 is near the same
frequency as 𝜔T of the single-stage op amp, the
maximum achievable closed-loop bandwidth of the
two-stage op amp will always be lower than that of
the single-stage op amp with a first-order transfer
function. The settling time of a second-order
system is difficult to compute and predict as it is
highly dependent on both its gain-bandwidth
product.
 Fig.1 Proposed Circuit diagram

III.SIMULATION RESULTS

Fig 2.Four Stage OTA with 45dB Gain

Fig 3.Four Stage OTA with 68dB Gain

The gain is increased by varying the

PARAMETER VALUES biasing voltages according to the technology (130
Technology 130nm
nm) with respect to the stages in OTA increases a
gain of 15dB. Additional transistors in differential
UGB 3MHz amplifier circuit at first stage increases a gain of
7dB. A change in [W/L] ratios with respect to the
CL 1fF transistor brings the gain into positive and
maintains stability. Including an additional
Gain 68dB capacitor between first stage and second stage
makes an increase of gain by 10dB. Changes in
Power 346µW capacitive load at output shows an impact on the
output to be stable with a high gain.
Table 1: Simulation results
COMPARISON OF PROPOSED WORK WITH PREVIOUS LITERATURE:

Paper Technology Technique Gain Gain Margin Phase Power Load

in dB in dB Dissipation Capacitance
Adeline 0.35µm Neuromod 22.53 21 60̊ 69.73µW 1pF
Zbrzeski ulation
Boris 90nm NMC 15 32 110º 5mW 5Pf
murrmano
RidaAssdad 0.18 µm NCFF 52 81 80º 796 µW 3.6pF
Li Yilei 0.13 µm FC 53.61 43 87º 547 µW 5.5pF
This work 0.13 µm MC 68 117 165º 346 µW 1fF

Table 2: Comparison of different technologies

IV.CONCLUSION REFERENCES

A high-performance four-stage OTA [1] R. G. H. Eschauzier and J. H. Huijsing, “A 100-MHz 100-

driving 1fF load has been presented. The amplifier
uses minimum transistors count, since three gain
stages are implemented through the simplest
common source configuration, and develops a
compensation network made up of a single Miller
capacitor with a series resistance and two R-C
parallel branches. The design was developed using
a 0.13µm CMOS technology. It provides DC gain
greater than 45 dB, gain-bandwidth product of
about 3MHz. The proposed amplifier shows better
performance as compared to all previously reported
four-stage OTAs.
ACKNOWLEGEMENT
We feel glad to take this opportunity to
thank our Professor Ms. Minhaz Sultana and
Mr.Sarin Vijay Mythry of Christu Jyothi Institute
of Technology and Science, Jangaon, Telangana
State, India for taking keen interest and providing
encouragement in our project work. Also, I would
like to thank the CJITS, Jangaon for encouraging
taking part in this research work.
Authors Profile
dB Operational Amplifier with Multipath Nested Miller
Compensation,” IEEEJ. Solid-State Circuits, vol. 27, no. 12, pp.
1709–1716, Dec. 1992.
[2] R. G. H. Eschauzier and J. H. Huijsing, Frequency
Compensation Techniques for Low-Power Operational
Amplifiers. Dordrecht, The
Netherlands: Kluwer Academic, 1995.
[3] G. Palumbo and S. Pennisi, Feedback Amplifiers: Theory
and Design. Dordrecht, The Netherlands: Kluwer Academic,
2002.
[4] G. Palumbo and S. Pennisi, “Design methodology and
advances in nested-Miller compensation,” IEEE Trans. Circuits
Syst. I, Fundam.Theory Appl., vol. 49, no. 7, pp. 893–903, Jul.
2002.
[5] B. K. Thandri and J. Silva-Martinez, “A robust feedforward
compensation scheme for multistage operational
transconductance amplifiers with no Miller capacitors,” IEEE J.
Solid-State Circuits, vol. 38, no. 2, pp. 237–243, Feb. 2002.
[6] R. Mita, G. Palumbo, and S. Pennisi, “Design guidelines for
reversed nested Miller compensation in three-stage amplifiers,”
IEEE Trans.Circuits Syst. II, Analog Digit. Signal Process., vol.
50, pp. 227–233, May 2003.
[7] X. Peng and W. Sansen, “Transconductance with
capacitances feedback compensation for multistage amplifiers,”
IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1515–1520, Jul.
2005.
[8] A. D. Grasso, G. Palumbo, and S. Pennisi, “Three-stage
CMOS OTA for large capacitive loads with efficient frequency
compensation scheme,” IEEE Trans. Circuits Syst. II, Exp.
Briefs, vol. 53, no. 10, pp. 1044–1048, Oct. 2006.

DINDUGALA CHANDRA JANGAM ANUSHA, currently

PRAKASH, currently he is a she is a final year student in
final year student in Electronics Electronics and communication
and Communication Engineering engineering branch from CJITS,
branch from CJITS, Warangal Warangal district.
district.

KODAM AKHIL, currently he is MACHA SHIVA DEEPAK,

a final year student in Electronics currently he is a final year student
and communication engineering in Electronics and communication
branch from CJITS, Warangal engineering branch from CJITS,
district. Warangal district.
 MS.MINHAZ SULTANA, working
as a Assistant professor in CJITS,
Jangaon received B.Tech in
Electronics and Communication
Engineering degree from BITS
Narsampet JNTU, Hyderabad in 2012
and M.Tech Degree in Low Power
VLSI.

Mr. SARIN VIJAY MYTHRY was

born in Sangareddy in Telangana State,
India. He received M.E. Degree in VLSI
Design from Karunya University,
Coimbatore in 2009, Bachelor Degree in
from JNTU, Hyderabad, Telangana State, India & now he
is working towards his Ph.D. Degree in Electronics
Engineering with specialization in Low power
Biomedical VLSI technology at Karunya University.
Currently he is working as a Assistant Professor in
Electronics & Communication Department at Christu
Jyothi Institute of Technology and Science, Warangal.
His interests are in Micro Electronic System Design using
CMOS Technology, Biomedical VLSI, RF Design and
Bio-Electronics Engineering.