Synchronizers:A Review & Comparative Analysis
Santosh R. Chudasama
Electronics and Communication Engineering Department
Vishwakarma Government Engineering College
Chandkheda-382424,Ahmedabad, Gujarat, India
chudasamasantosh07@gmail.com
Abstract— Synchronizers play a main role in clock domain
crossing(CDC).Large multiple-clock domain systems on
chip(SoC) require synchronization in two cases: (1).When
transferring signals and data between various clock domains.(2).
When receiving asynchronous inputs.Such synchronizations
often affected to metastability effects.Synchronizers which are
designed specifically for the elimination of metastability from the
system are known as metastable hardened synchronizers.The
performance parameters of synchronizer are metastability time
constant(�),metastability window(Tw) and Mean Time Between
Failure(MTBF).These parameters are affected by the technology
scaling , process variation , temperature variations and voltage
variations.
Keywords- Metastability-Time-constant(� ), MTBF, CDC, PVT-
variations, Technology Scaling
I. INTRODUCTION
In modern, many applications consist of multiple
clock domains. There is data transfer between these clock
domain systems. Synchronizer is used for data
synchronization. To determine the reliability of system
synchronizer plays a very essential role. System on chip
designs have thousands of clock domain crossings (CDC),
where the system is affected to metastability errors[1].
Synchronizers are used to convert domain timings, to mitigate
those failures and provide reliable signal transition between
CDCs. The synchronizer is having a parameter such as �, Tw
and MTBF.As the data changes in metastability window
synchronizer suffers from a metastability problem,because of
that failures occur in system. As metastability occurs we cant
predict the correct level of output whether it is ‘0’ or ‘1’.The
metastability problem can never be completely avoided but its
probability can be reduced.
A. Basic Synchronizer
Fig.1.Basic Synchronizer[9]
Prof. Alpesh H. Dafda
Electronics and Communication Engineering Department
Vishwakarma Government Engineering College
Chandkheda-382424,Ahmedabad, Gujarat, India
sadafda@gmail.com
There are two digital systems which are working at different
clocks. System1 is working at clock1 and system2 is working
at clock2. When the data is transferred from one clock domain
to another clock domain data synchronization is required.
These two digital systems require a block to communicate
with each other[9]. A synchronizer samples an asynchronous
signal and give an output which is synchronized version to the
local clock.
B. Multistage Synchronizer
Fig.2 shows typical multistage synchronizer.To
mitigate the effects associated with metastability, latches and
flips flops are often used to synchronize the data [1], such as
the N pipelined flip flops shown in Figure.
Fig.2.Multistage Synchronizer[1]
Metastability resolution time is given as[1],S≈(N-1) × Tc
where,Tc is the clock cycle time of the receiving clock
domain.There is a probability that the circuit will not resolve
its metastable state correctly within the allowed time.
C. MTBF(Mean Time Between Failure)
Mean Time Between Failure gives us information on
how a particular element will fail.It also gives the average
time interval between two successive failures. The
performance of synchronizer is usually measured by the mean
time between failure(MTBF).MTBF is represented as
following equation[1],
where, Fc & Fd = Sender and Receiver frequency
respectively
 �=Metastability resolution constant
Tw=Metastability window
S=Metastability resolution time.
To design a reliable synchronizer ,the MTBF should be as high
as possible. As technology scales Fc & Fd increase, so to
maintain high MTBF, � must be decrease[1].So all the efforts
the researchers are doing to decrease the value of � so to
increase the value of MTBF and improving the performance of
synchronizer.
II. D FLIP-FLOP AS SYNCHRONIZER
A. Normal D Flip-flop
The D flip-flop which is normally used as a
synchronizer is shown in figure.This is a positive edge
triggered flip-flop[10].
Fig.3.Normal D flip-flop[10]
Assume that the clock is low, node A is at 1, and input D
changes from 0 to 1. As a result, node A is at 0 and node B is
at 1.When the clock rises, it disconnects the input from node A
and closes the A-B loop and whatever the value at B will be
propagate to the Q[10].If the D changes during the transition
of the clock than the A and B goes into the metastable state.
B. Standard Library D Flip-flop
The modified version of normal D flip-flop[5] is
given in Fig.4.This flip flop has a better performance in terms
of metastability.
Fig.4.Standard Library D Flip-lop[5]
The operation of the flip-flop is as follow : When the clock
CPI is low and CPN is high a data at the D input is inverted
through the enable inverter to node DN.The inverter of the
master latch propagates the signal to node A. When signal CPI
is high and CPN is low the feedback enable inverter of the
master latch holds the voltage at DN at its previous state. The
signal on node A is passed through an inverter and a
transmission gate when the clock signal CPI is high and CPN
low. The inverters of the slave latch provide the output signal
Q[5].The problem with latch circuitry occurs when the voltage
at the D input changes at the same time when the clock signal
CPI/CPN makes its low-to-high/high-to-low transition,at that
moment,then the output Q goes into the metastable
state[5].The propagation delay,� and power dissipation of
flipflops are very high, so that it prove to be inefficient.
III. METASTABLE HARDENED SYNCHRONIZERS
Metastable hardened means the synchronizers which are
designed specifically for the elimination of metastability from
the system.The Jamb latch design ,improved jamb latch design
and pseudo-nmos based synchronizer design are reported to
have very low values of �.This makes them better candidates
as synchronizers than the conventional flipflops.
A. Jamb Latch Synchronizer
Jamb latch is a circuit commonly used as a
synchronizer because of its relatively good performance. As
shown in Fig.5 the circuit is set by pulling Node A to ground
when data is high and clock is low, and reset by pulling Node
B to ground when data goes low[7].
Fig.5.Jamb Latch Synchronizer[7]
Metastability occurs when the data and clock arrive
very close to each other so that the Node A is pulled to around
VDD/2[8]. After that, the metastability is resolved towards 1
or 0 in the cross-coupled inverters.The resolution speed of
metastability is determined by the metastability time constant
τ which is dependent on transconductance in the cross-coupled
inverters and the capacitance at nodes A and B. The set and
reset structure in the Jamb latch allows a lighter load on nodes
A and B, therefore leads to a small τ and fast resolution of
metastability.The performance of Jamb latch synchronizer
degrades rapidly with VDD scaling[8].
B. Improved Jamb Latch Synchronizer
An improved synchronizer proposed in [8] is better in
order to deal with the performance degradation of the Jamb
latch synchronizer with decreasing VDD ,difference is that the
gates of P transistors are connected to ground rather than the
nodes A or B. This structure keep maintaining enough current
in the cross-coupled inverters.This modification slows down
the degradation of τ with decreasing VDD.The PMOS
transistors consume a lot of power during standby mode
because they remains always on[8].So in Figure.6, a
metastability detector is added to control the ON and OFF of
the P transistors in a way that the P transistors are ON only
during metastability and are OFF when the circuit is out of
metastability.
Fig.6.Improved Jamb Latch[7]
C. Pseudo-NMOS Synchronizer
Fig.7.Pseudo-NMOS Synchronizer[6]
The pseudo-nmos latch design shown in Fig.7 is a
very efficient synchronizer design with very low τ values.But
the propagation delay due to the circuit is very high.This
circuit is similar to the jamb latch design except for the
pseudo-nmos configuration[6].Operation of pseudo-nmos
latch design is as follow: when clock goes high, both PMOS
transistors are conducting. So q and qbar will be pulled to
VDD.As clock goes high q is set to high through PMOS when
d input is high and dbar is low,which disconnects any direct
path of q to ground.When clock is high and d is low than qbar
goes high turning on the NMOS whose drain is connected to q
thus forming a direct path of q to ground.When clock goes
low, the pull down transistors will conduct so the q and qbar
set to its previous values[6].The use of passive PMOS pull ups
transistors reduces the capacitance on the nodes q and
qbar,this results in a high Gm and very low capacitive load on
the critical nodes.Thus the pseudo-NMOS latch has lower �
value than any other synchronizer.
IV. IMPACT OF TECHNOLOGY SCALING ON �
The effect of technology scaling on � discussed in
[1].It was reported that � scales with technology till
180nm.They have also found that the effective metastability
window Tw also scales with technology[3].
In a more recent work by Beer et al the impact of
technology scaling on synchronizers for 130nm & lower
technology nodes up to 45nm has been discussed [1].The
authors show through on-chip measurements that � doesn’t
scale with technology, but increase with technology scaling as
shown in Fig.8.The authors call this devolution of
synchronizers because there have been opposing results
between experimental & simulation results as technology
scales[1].
Fig.8.Calculated,measured and simulated � [1]
Fig.9.The degradation effects of PVT on �[1]

Fig.10. � simulations for different process corners [3]
Fig.11. � vs temperature for different supply voltage [3]
Fig.12.Simulations of � vs supply voltage [3]
Fig.10 shows � siulations vs. supply voltage for different-
process corners Fast-Fast(FF), Slow-Slow(SS) and Typical-Typical
(TT).The effect of temperature on � depends on the supply voltage
& threshold of transistors[4].As the temperature increases the
Vth decreases so, � also decreases.When supply voltage is
high & threshold voltage is low,� increases with
temperature.Simulations of � vs. temperature for different
supply voltages are shown in fig.12.Supply voltage has a large
effect on �.When VDD is decreased, Gm also decreased and
so � increases[4].So to have a higher value of � higher supply
voltage is recommended.
V. CONCLUSION
In this paper the working, advantages and
disadvantages of all the synchronizers are discussed. Pseudo-
NMOS synchronizer has a lower � value and higher MTBF
value among all the synchronizers.The effect of technology
scaling and PVT variations is also discussed.The value of �
decreases as the technology scales.As the temperature
increases and VDD decreases the value of � increases because
Gm increases.
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