Ugd 2 C 6657

D.Module2.
C6657
User Guide
Document Rev. 1.12
Marktstr. 10
47647 Kerken
phone: +49 2833 / 570977

e-mail: info@dsignt.de
web: www.dsignt.de
D.Module.C6657 User Guide Contents
Table of Contents
1 Overview................................................................................................ 6
2 Hardware................................................................................................7
2.1 System Architecture.......................................................................7
2.2 Hardware Installation...................................................................10
3 Software .............................................................................................. 12
3.1 Software Installation.....................................................................13
3.2 Creating a new CCS project.........................................................14
3.3 Building a boot-loadable Intel-Hex File.........................................15
3.3.1 Dual Core Boot.....................................................................16
4 Memory................................................................................................ 17
4.1 Memory Map................................................................................17
4.2 C6657 on-chip memories.............................................................17
4.2.1 L1D and L1P .......................................................................18
4.2.2 L2RAM ................................................................................18
4.2.3 MSM.....................................................................................19
4.3 DDR3 .......................................................................................... 19
4.4 External Memory-Mapped Devices..............................................19
4.5 SPI NOR Flash.............................................................................19
4.6 NAND Flash.................................................................................20
4.7 Cache Coherence........................................................................21
5 Board Logic and Configuration Registers.............................................22
5.1 UARTCTRL..................................................................................24
5.2 BUSCTRL....................................................................................24
5.3 DSPCTRL....................................................................................25
5.4 SETUPSTAT................................................................................26
5.5 FLASHCTRL................................................................................26
5.6 GPIOMUX....................................................................................27
5.7 ETHCTRL.....................................................................................28
5.8 PCIECTRL...................................................................................28
5.9 BOOTMOD...................................................................................29
5.10 PRGIODATLO............................................................................29
5.11 PRGIODIR.................................................................................30
6 External Bus Interface..........................................................................31
6.1 UPP Mode....................................................................................34
6.2 EMIF Mode...................................................................................38
6.3 Auxiliary Bus Interface Signals.....................................................40
6.4 Usage and Routing Guidelines.....................................................42
© D.SignT 2013 Doc.Rev. 1.12 1

D.Module.C6657 User Guide
7 McBSP................................................................................................. 43
8 SPI....................................................................................................... 44
9 I²C........................................................................................................ 45
10 PRGIO ............................................................................................... 46
11 Interrupts............................................................................................ 49
12 SPI Flash Memory .............................................................................51
13 UART and USB..................................................................................55
14 Ethernet.............................................................................................. 56
15 PCIe and SRIO..................................................................................58
16 Real-Time Clock.................................................................................61
17 Fan Control and Supervision..............................................................63
18 Power Supply.....................................................................................66
19 Thermal Considerations.....................................................................67
20 Reset.................................................................................................. 68
21 Module Configuration File..................................................................69
22 Setup Utility........................................................................................ 70
23 Getting Support..................................................................................72

List of Tables
Table 4.1: Memory Map...........................................................................17
Table 5.1: Board Configuration Registers................................................23
Table 5.2: UARTCTRL Register...............................................................24
Table 5.3: BUSCTRL Register.................................................................24
Table 5.4: DSPCTRL Register.................................................................25
Table 5.5: SETUPSTAT Register.............................................................26
Table 5.6: FLASHCTRL Register.............................................................26
Table 5.7: GPIOMUXLO Register............................................................27
Table 5.8: GPIOMUXHI Register.............................................................27
Table 5.9: ETHCTRL Register.................................................................28
Table 5.10: PCIECTRL Register..............................................................28
Table 5.11: BOOTMODLO Register.........................................................29
Table 5.12: BOOTMODHI Register..........................................................29
Table 5.13: PRGIODATLO Register........................................................29
Table 5.14: PRGIODIRLO Register.........................................................30
Table 5.15: PRGIODIRHI Register...........................................................30
Table 6.1: Bus Interface Signals..............................................................33
Table 6.2: TCA6408 Port Pins..................................................................34
Table 7.1: McBSP Signals........................................................................43
Table 8.1: SPI Signals..............................................................................44
Table 9.1: I2C Signals..............................................................................45
Table 10.1: PRGIO Routing.....................................................................48
Table 12.1: SPI Flash Layout...................................................................51
Table 13.1: UART Connections................................................................55
Table 13.2: USB Connections..................................................................55
Table 14.1: Ethernet Connections ...........................................................56
Table 15.1: PCIe and SRIO Signals.........................................................60

List of Figures
Figure 2.1: D.Module2.C6657 Block Diagram............................................9
Figure 2.2: D.Module2 Base Board .........................................................10
Figure 6.1: Bus Interface in UPP Mode....................................................37
Figure 6.2: Bus Interface in EMIF Mode...................................................39
Figure 6.3: Bus GPIO Signals..................................................................41
Figure 10.1: PRGIO Connections.............................................................46
Figure 11.1: Interrupts..............................................................................49
Figure 14.1: Ethernet Connections...........................................................57
Figure 15.1: PCIe and SRIO Connections................................................59
Figure 17.1: Fan Connection....................................................................64

D.Module.C6657 User Guide Overview
1 Overview
The D.Module2.C6657 is a high-performance, stand-alone, floating-
point digital signal processing (DSP) computer board. It features a
variety of interface and communication peripherals:
• dual-core architecture, 2 x 1.25 GHz clock

• large internal memories, external 512 Mbytes DDR3 memory
• Gigabit Ethernet
• PCI express
• Serial Rapid IO
• UART
• USB 1.1
• SPI
• I²C
• external bus interface, EMIF and uPP mode
• GPIO
• two McBSP Synchronous Serial Ports
• Real-Time Clock
• fan control and supervision
• temperature monitor

D.Module.C6657 User Guide Hardware
2 Hardware
2.1 System Architecture

The board is based on the Texas Instruments TMS320C6657 Key-
stone processor, surrounded by supplemental functions like power
supplies, memories, interface transceivers, clock synthesizer, etc.
All external ports use level shifters to be compliant with LVTTL/
LVCMOS logic.
System start-up is controlled by an AVR micro-controller: Once the
power supplies have stabilized, the AVR programs the clock syn-
thesizer and starts the DSP reset sequence. The DSP reads its
boot configuration from the multiplexed GPIO/BOOTCFG pins. At
start-up the board logic presents the default boot configuration to
the DSP, which is SPI NOR boot. The DSP built-in ROM boot load-
er initializes its SPI port and starts boot-loading from the SPI flash.
The first program which is loaded from the flash now initializes and
configures the DSP (PLLs, DDR3 interface, EMIF, etc.). These ini-
tialization settings and parameters are also stored in the flash
memory. The GPIO/BOOTCFG multiplexer is switched to to GPIO
mode. The system now checks the state of the SETUPN and IN0N
pins (located on the COM port connector). If both SETUPN and
IN0N are low the recovery utility program is boot-loaded, which is
used for firmware updates and during factory programming. If
SETUPN is found low the DSP reads the Module Configuration File
from the flash memory, which stores user-defined settings like
UART communication parameters. The DSP initializes the UARTs
accordingly and finally boot-loads the Setup utility program. The
Setup utility is used to upload user program and data files to the
flash memory and provides some basic commands to read and
write the DSP memories. At a normal start-up, when both SETUPN
and IN0N pins are not activated, the DSP reads and processes the
Module Configuration File and then boot-loads the program(s) spe-
cified in the Module Configuration File. The application program
finds the DSP and memories readily initialized and configured.

The on-board peripherals are configurable via the Board Logic, a

CPLD which is memory-mapped to the EMIF interface. It imple-
ments several registers to control GPIO multiplexers, UART trans-
ceiver configuration, reset individual peripherals, etc. Direct access
to this CPLD is possible, but the preferred method is using the
D.Module2 board level BIOS functions. DSP internal peripherals
are programmed using the Texas Instruments Chip Support Library
(CSL), some (UART, SPI, I²C, and GPIO) are also supported by the
D.Module2.BIOS.
Five Connectors are used to interface the D.Module2.C6657 to your
system: The COM connector provides communication interfaces:
UART, USB, Ethernet, the PRGIO programmable IO ports, and the
power supply connections. The external Bus Interface and the
McBSP serial ports are available on the BUS1 and BUS2 connect-
ors, the EXP connector carries board specific signals: connection to
a fiber-optic Ethernet Transceiver, SPI, Fan control, etc.). The high-
speed serial signals (PCIe and SRIO) are available on the GTP
connector. An additional 14-pin connector on top of the board is
used to connect a JTAG in-circuit emulator for debugging.
The following block diagram shows the hardware structure of the
D.Module2.C6657:

SRIO PCIe
2 lanes 2 lanes GBT
COM
SRIO PCIe
3.3V
IN
BUS1
AVDD
RS232
CVDD UART0 RS422/485
INT[2:0] GPIO COM
Power CVDD1 Line Driver
Supply DVDD15
Controller DVDD18
VDDR
VDDT SGMII Gigabit ETH
MDIO PHY
VCNTL
D[7:0]
A[19:16] I2C Level Shifter I2C
Core
A[5:0]
CTRL SRIO/SGMII
Clock Synthesizer USB 1.1
PCIe
UART1 Controller USB
DDR3
Bootmode
Timer0 GPIO MUX, CPLD PRGIO
GPIO[1:0]
MUX Timer1
GPIO
BUS2 Flash EXP

SPI 8M Byte
ETH
NAND Flash (LEDs,
GPIO[3:2] Fibre)
Level Shifter SPI
D[31:16] BUS AVR System FAN

Controller EMIF16/UPP
A[15:6] Monitor, RTC
Temperature
RESETs Fan control
Monitor
NMI ALERT
DDR3 - 1333
Board Controller DDR3 512M Bytes
CPLD 32-Bit wide
Level Shifter McBSP0

McBSP0
McBSP1
JTAG/EMU JTAG
McBSP1 Level Shifter
TMS320C6657
Figure 2.1: D.Module2.C6657 Block Diagram

2.2 Hardware Installation
Always use ESD precautions when handling the

D.Module2.C6657!
Remove the D.Module.2 board and the base board from the pack-
age and mount the D.Module2 board on the base board as shown
in the diagram above. Make sure the orientation is correct., do not
use excessive force to insert the module.
+AVCC
-AVCC
AGND
+3.3V
0V
DCIN
GTP
RS232
BUS1
COM
D.Module2 USB
ETH
BUS2
EXP
SETUP / Test
RESET / Pwr
Figure 2.2: D.Module2 Base Board
Connect the 3.3V power supply unit to an AC outlet (100-240 VAC)

and to the DCIN connector on the base board. The PWR LED
should now light up. Connect the RS232 cable: the female con-
nector goes to a free port on your PC, the male connector is
plugged into the RS232 receptacle on the base board.
Start a terminal program on your PC. If you don't have a terminal
program we recommend TeraTerm. Download it from
http://www.heise.de/download/teraterm-pro.html or any other trust-

worthy site on the Internet. Configure the terminal to the COM port
the D.Module2 is connected to, 115200 baud, 8 data bits, 1 stop bit,
no parity.
If your PC is not equipped with a RS232 port you can alternatively
use the USB port. You may need to install the USB drivers from the
support software. The USB driver is a VCP Virtual Com Port driver.
After connecting the D.Module2 a new COM port will be added to
your system. Configure the terminal program to this COM port.
Now hold the SETUP button down, press and release RESET, and
finally release SETUP. The Set-Up utility menu will show up on your
terminal screen.
The sample programs in the support output information, instructions
and results via the RS232 UART connection. You can change this
to USB:
• change line
h_uart = DM2_uartOpen(DM2_UART0);
in main.c to
• rebuild the project
© D.SignT 2013 Doc.Rev. 1.12 10

D.Module.C6657 User Guide Software
3 Software
The default code generation and debugging environment for the
D.Module2.C6657 is the Texas Instruments Code Composer Stu-
dio. The TMS320C6657 is supported from version 5 and above.
Some additional packages might be required, depending on your
application:
• dsplib_c66x – FFTs, Filter, Autocorrelation, etc.
• imglib_c66x – image processing algorithms
• mathlib_c66x – optimized floating point functions
• ipc – inter processor communications
• ndk – network (TCP/IP) library
• mcsdk – multicore software development support
Additional specialized software packages are available from Texas

Instruments, please check the TMS320C6657 product page, Soft-
ware.
The basic programming support is included with the
D.Module2.C6657 support software. Run the installation program
and check the example projects. The D.Module2.BIOS functions
provide initialization and data transfer functions for various peri-
pherals. The BIOS is a memory-resident set of functions which are
boot-loaded from the SPI flash memory at system start-up. These
functions occupy the first 8 Kbytes of the MSMCSRAM (multicore
shared memory). This memory area is excluded in the default linker
command file and must not be overwritten. The BIOS functions are
documented in the support software:
Install_Dir/D.SignT/Boards/DM2C6657/Documentation.
You can use the dm2c6657.bios.chm file, or unzip the dm2c6657-
bios_html.zip folder and open the index.html file with a web
browser. To use the D.Module2.BIOS in your programs include the
header file
Install_Dir/D.SignT/Boards/DM2C6657/BoardSupport/dm2c6657.h
© D.SignT 2013 Doc.Rev. 1.12 11

3.1 Software Installation

Texas Instruments Code Composer Studio is available for down-
load at http://www.ti.com/tool/ccstudio. Follow the installation
instructions and start Code Composer Studio.
To install the D.Module2 support software run the setup.exe pro-
gram and choose your working directory. Linux users copy and
unpack the tar.gz archive.
USB drivers for Windows are included with the support software,
but we recommend to check http://www.ftdichip.com/FTDrivers.htm
for the latest VCP (Virtual Com Port) drivers. Linux drivers are also
available from this site.
To create a JTAG debugging target connection to the D.Module
change to the “Debug” View and
• change to the Debug View and open the Target Configurations
(if not already shown use “view – target configurations”
• right click on “User Defined” and select “New Target Configura-
tion”
• assign a name, e.g. DM2C6657_XDS200.ccxml, a new tab will
open
• in Connection select your JTAG emulator device, e.g. Texas
Instruments XDS2xx USB Emulator
• in Board or Device type 6657. The following selection box will
show the TMS320C6657. Activate the checkbox .
• Change to the “Advanced” tab and select the C66xx_0 core.
• Select the initialization script dm2_c6657.gel from the
support software Install_Dir/D.SignT/Boards/DM2C6657/Board-
Support, click the “Save” button
• Connect the emulator to the D.Module2.C6657 and power-up the
board. Click “Test Connection”
© D.SignT 2013 Doc.Rev. 1.12 12

3.2 Creating a new CCS project

We strongly recommend to keep the directory structure created by
the D.Module2 support software “as is”, and add your own projects
in subfolders below
Install_Dir/D.SignT/Boards/DM2C6657/Projects
To generate your own projects copy one of the existing support
software projects into your new project folder. Copy these files:
.ccsproject
.cproject
.project
dm2c6657.cmd
macros.ini
File macros.ini may have been renamed to macros.ini_initial if the
original project had been opened in CCS. Please rename it to mac-
ros.ini in your new project folder to ensure all paths and include
options are correctly imported.
Open file .cproject with a text editor and change the project name in
line 81:
<project id="PROJECT_NAME.com.ti.ccstudio.....>
and save the file. Open file .project with a text editor and change
the project name in line 3:
<name>PROJECT_NAME</name>
(The line numbers may change with new code Composer Studio
releases.) In CCS finally choose “Project - import existing CCS
eclipse project”. This approach ensures correct project settings.
You can change and tailor the project options later depending on
your requirements.
© D.SignT 2013 Doc.Rev. 1.12 13

3.3 Building a boot-loadable Intel-Hex File

Once development is completed you can build an Intel-Hex boot
file. This can be stored in the D.Module2 flash memory using the
Setup Utility. The program is then automatically started on reset or
power-on. This procedure differs from the description in the Texas
Instruments Bootloader documentation.
The C6657 buillt-in ROM Boot Loader (RBL) provides some fea-
tures to initialize the PLLs and DDR3 memory before starting the
program boot load. This is not required on the D.Module2.C6657,
since the startup procedure already handles all initializations. The
RBL approach requires to exactly specify the DDR3 initialization
parameters when generating the boot file. During product lifetime
these parameters may change because the memory market is
highly fluctuating, and adaptations to newer devices are unavoid-
able. This requires the user to exactly know which devices are used
on a particular board and hinder portability and system mainten-
ance. We therefore included our own boot loader function in the
D.Module2.BIOS: DM2_flashBootload(). This boot loader directly
accepts the output of the hex6x conversion program included with
the Texas Instruments Code Generation Tools. The complex boot
image generation sequence described in the RBL documentation is
not required. A suitable command file for hex6x is included in the
support software:
Install_Dir/D.SignT/Boards/DM2C6657/BoardSupport/hex6x.cmd
Hex6x can be invoked by the post-build command in CCS:
${CG_TOOL_HEX} ../../../BoardSupport/hex6x.cmd -bootorg
0x30000 -o "${ProjName}.hex" "${ProjName}"
This is the predefined setting in the sample projects. You may need
to change the -bootorg address to choose a different start address
of the boot file in the flash memory.
© D.SignT 2013 Doc.Rev. 1.12 14

3.3.1 Dual Core Boot

If both cores are used additional steps are required. Only core 0 is
able to boot load a program. The D.Module2.C6657 startup proced-
ure reads the Module Configuration File, section [DSP] and
searches for the “bootaddr1” entry. If this is specified, the program
is loaded by core 0 and stored in the local memory of core 1. Core
0 also writes the program entry address read from the boot file to
the BOOTORG1 address in the C6657. Then the startup procedure
searches for the “bootaddr0” entry in the Module Configuration File
and boot-loads the specified program to core 0. Core 0 starts pro-
gram execution and can now start core 1 by calling BIOS function
DM2_resetCore(1);
To allow core 0 to access core 1 local memory during bootload you
must use global addresses in the linker command file: Core 1 local
L2RAM must be specified as 0x11800000. Also the core 1 program
entry point must be aligned to a 1024 byte boundary. The default
linker command file from the support software ensures these set-
tings. Please refer to the “dual_core” and “ipc” examples in the sup-
port software for “standard” programming and SYS/BIOS projects.
© D.SignT 2013 Doc.Rev. 1.12 15

D.Module.C6657 User Guide Memory
4 Memory
4.1 Memory Map

Address Name Size Usage
0x0080.0000 – 0x008F.FFFF Local L2 1Mbyte direct-mapped memory
or L2 cache (local address)
0x00E0.0000 – 0x00E0.7FFF Local L1P 32Kbyte Direct-mapped program
memory or
L1 instruction cache
0x00F0.0000 – 0x00F0.7FFF Local L1D 32Kbyte Direct-mapped data memory or
L1 data cache
0x1080.0000 – 0x108F.FFFF L2 Core 0 Image of core 0 local L2 SRAM
(global address)
0x1180.0000 – 0x118F.FFFF L2 Core 1 Image of core 1 local L2 SRAM
(global address)
0x0C00.0000 – 0x0C0F.FFFF MSM 1Mbyte shared memory
0x7000.0000 – 0x73FF.FFFF EMIF16 CE0 NAND Flash
0x7400.0000 – 0x77FF.FFFF EMIF16 CE1 Board Logic CPLD
0x7800.0000 – 0x7BFF.FFFF EMIF16 CE2 External Memory Interface CS0
0x7C00.0000 – 0x7FFF.FFFF EMIF16 CE3 External Memory Interface CS1
0x8000.0000 – 0x9FFF.FFFF DDR3 512MByte DDR3 Memory
Table 4.1: Memory Map
4.2 C6657 on-chip memories

Each DSP core has three local memory areas: L1P, L1D, and
L2.L1D is used for data only, L1P is used only for program code
(instructions). L2 can be used as direct-mapped memory or as
level-2 cache. The MSM is a direct-mapped memory.
© D.SignT 2013 Doc.Rev. 1.12 16

4.2.1 L1D and L1P

By default the L1D and L1P memories are configured as level-1
cache. It is possible to use a part (or the entire) L1P and L1D
memories as direct-mapped memory. This may be useful in applic-
ations with short algorithms processing small amounts of data at a
very high speed. Allocating the critical code and data to L1D and
L1P will prevent this code/data from being flushed out of the cache
by supplemental, non-critical functions.
To reconfigure L1P and L1D please refer to the TMS320C66x DSP
Cache User Guide, Texas Instruments literature number
SPRUGY8, and use the CSL (Chip Support Library) Cache func-
tions.
4.2.2 L2RAM
The L2 memory is mapped to two address areas: At 0x0080.0000 it
is only accessible by the local core. The global addresses
0x1080.0000 and 0x1180.0000 allow to access the other core's L2
memory. These global addresses must also be used for DMA trans-
fers and to allow boot-loading programs. Access to the local
address (0x0080.0000) is not possible for the DMA controllers.
Also, since only core 0 is able to boot-load programs, you must use
the global core 1 addresses to allow core 0 to write core 1 memory
during bootload.
L2 is by default configured as direct-mapped memory. It can be
used for data and program code. It is possible to use a part of the
L2 memory as L2 cache, which may improve performance if large
amounts of DDR3 data are used, e.g. in image processing.
To reconfigure the L2 memory please refer to the TMS320C66x
DSP Cache User Guide, Texas Instruments literature number
SPRUGY8, and use the CSL (Chip Support Library) Cache func-
tions.
© D.SignT 2013 Doc.Rev. 1.12 17

4.2.3 MSM
This is a direct-mapped memory shared by both cores, usable for
code and data. On the D.Module2.C6657 the first 8K bytes of this
memory store the BIOS functions to make them accessible for both
cores. This memory area must be excluded in the linker command
file to prevent the BIOS functions from being overwritten.
4.3 DDR3
DDR3 is also a shared memory available to both cores and is
usable for code and data. It is readily initialized by the system star-
tup procedure. If large amounts of data or program code are alloc-
ated to the DDR3 memory the overall performance may be
increased by configuring a part of the L2 memory as a level-2
cache.
4.4 External Memory-Mapped Devices

The D.Module2.C6657 External Bus Interface can be used to con-
nect external memory-mapped devices, e.g. an FPGA. The
External Bus Interface can operate in two modes: EMIF mode and
uPP mode. Memory-mapped interfaces require the default EMIF
mode. Please refer to the External Bus Interface chapter for
detailed information.
4.5 SPI NOR Flash

The 8M bytes SPI Flash on the D.Module2.C6657 are primarily
used to permanently store application programs and data for boot-
load. Please refer to chapter SPI Flash Memory for detailed inform-
ation.
© D.SignT 2013 Doc.Rev. 1.12 18

4.6 NAND Flash

The NAND flash provides non-volatile storage for large programs
and/or data. The D.Module2.C6657 uses a small page SLC NAND
flash. SLC provides higher reliability (although less capacity) than
MLC. The NAND is organized in pages of 512 bytes. Programming
is done on a page basis. 32 pages form a block (16K bytes). A
block must be erased before a page within this block is (re-)pro-
grammed. The SLC NAND technology allows to erase/program a
block about 100,000 times. Not all blocks in a device are guaran-
teed to be fully functional. A 512Mbit device for example has 4096
blocks, but only 4016 are guaranteed to be fully usable. Bad blocks
are marked during manufacturing, additional bad blocks may
develop during lifetime.
Each page contains 512 data bytes plus 16 spare bytes. The spare
bytes are used to store bad block information and ECC data. The
bad block information is stored in the 6th spare byte (bad if != 0xFF),
3 bytes of 1-bit ECC data are typically stored in the 7 th to 9th byte.
The other bytes can be used for user-specific data, e.g. links to the
next data page if no file system is used.
The NAND project in the support software provides initialization,
erase, read and write functions. 1-bit ECC, as recommended for
SLC NAND devices, is implemented. Before the NAND is used,
function NAND_open must be called. This function maintains the
memory architecture information and a bad block table in a device
information structure, which is used by all other functions. A block
marked as bad must not be erased since this will also erase the
bad block information. If during lifetime additional blocks show
wear-out (programming errors and/or repeated ECC failures), these
blocks should be marked bad by the user:
© D.SignT 2013 Doc.Rev. 1.12 19

uint8_t buffer[16];
int32_t i;
for (i=0; i<16; i++) buffer[i] = 0xFF;

buffer[5] = 0; // bad block marker
NAND_writeSpare
(&NAND_devinfo, BAD_BLOCK_NUMBER, 0, buffer);
NAND_markBadBlock
(&NAND_devinfo, BAD_BLOCK_NUMBER);
If the NAND is excessively used, i.e. erased and programmed fre-

quently, using a dedicated NAND flash file system with garbage col-
lection, block replacement, and wear levelling routines is highly
recommended.
Please refer to the Texas Instruments “KeyStone Architecture
External Memory Interface (EMIF16) User Guide”, literature number
SPRUGZ3 for additional information.
4.7 Cache Coherence

Some operations, especially DMA transfers, require to check the
cache coherence under certain conditions. If a DMA for example
writes to MSM, an invalidate cache operation is required, otherwise
the DSP might continue using old (outdated) data which has been
cached before. A cache writeback operation is required to ensure
data has been written from cache to its “real” location before a DMA
transfer is started. Please refer to the Cache Coherence tables in
the TMS320C66x DSP Cache User Guide SPRUGY8.
© D.SignT 2013 Doc.Rev. 1.12 20

D.Module.C6657 User Guide Board Logic and Configuration Registers
5 Board Logic and Configuration Registers

The D.Module2.C6657 is a jumperless design, all options are con-
trolled via configuration registers at runtime.
The Board Logic implements a set of configuration registers to con-
trol and configure peripheral devices and pin multiplexers. These
control registers are memory-mapped to address 0x7400.0000 to
0x7400.001F. This memory area is configured as 8-bit wide at sys-
tem start-up. Some of these registers are defined for compatibility
with other D.Module2 family members but are not implemented on
the D.Module2.C6657.
Although direct access to these registers is possible, it is recom-
mended to use the associated D.Module2.BIOS functions.
Some of the Board Configuration Settings like bootmode and DSP
resets are reserved for initial configuration and production, do not
change these registers.
© D.SignT 2013 Doc.Rev. 1.12 21

Address Register Usage

0x7400.0000 USBCTRL not implemented
0x7400.0001 UARTCTRL configure UART0 line interface
0x7400.0002 CPLDCTRL not implemented
0x7400.0003 BUSCTRL configure external bus interface
0x7400.0004 WDOGCTRL not implemented
0x7400.0005 DSPCTRL DSP configuration
0x7400.0006 SETUPSTAT state of Setup and INx pins (COM connector)
0x7400.0007 FLASHCTRL flash memory write protection
0x7400.0008 INTMUXLO not implemented
0x7400.0009 INTMUXHI not implemented
0x7400.000A DMAMUXLO not implemented
0x7400.000B DMAMUXHI not implemented
0x7400.000C GPIOMUXLO configure bus interface GPIOx pins
0x7400.000D GPIOMUXHI configure bus interface GPIOx pins
0x7400.000E MUXINTEN not implemented
0x7400.000F MUXINTSRC not implemented
0x7400.0010 ETHCTRL Ethernet PHY configuration
0x7400.0011 EXPMUX not implemented
0x7400.0012 PCIECTRL configure PCIe interface
0x7400.0013 – reserved
0x7400.0015
0x7400.0016 BOOTMODLO Boot Configuration
0x7400.0017 BOOTMODHI Boot Configuration
0x7400.0018 PRGIODATLO PRGIO port data
0x7400.0019 PRGIODATHI not implemented
0x7400.001A PRGIODIRLO PRGIO port direction
0x7400.001B PRGIODIRHI PRGIO port direction
0x7400.001C reserved
– 0x7400.001F
Table 5.1: Board Configuration Registers
© D.SignT 2013 Doc.Rev. 1.12 22

5.1 UARTCTRL
D7..D2 D1, D0
not used, always read 0 Line Driver Configuration:
00 – RS232
01 – RS422
10 – RS484 Receiver
11 – RS485 Transmitter
Reset Value: 0x00
DM2.BIOS function DM2_uartSetLineif
Table 5.2: UARTCTRL Register
5.2 BUSCTRL
D7 D6 D5..D0
RESOUT UPPRESET not used, always read 0
1: RESOUTN asserted 1: TCA6408 in Reset
0: RESOUTN de-asserted 0: TCA6408 active
Reset Value: 0xC0
DM2.BIOS function DM2_busConfig
Table 5.3: BUSCTRL Register

The RESOUTN pin is used to keep external devices in reset until
the 6657 board is readily configured, e.g. avoid unexpected inter-
rupts from an A/D converter. The TCA6408 is an I2C port device
which is used to configure the Bus Interface in uPP mode. Please
refer to chapter “External Bus Interface” for more information.
© D.SignT 2013 Doc.Rev. 1.12 23

5.3 DSPCTRL
D7 D6 D5 D4 D3 D2 D1, D0
RESET unused BOOTMUX unused LRNMIEN LRESET CORESEL
1: reset 0 1: GPIO 0 1: local 1: local 00: core 0

DSP 0: BOOTCFG reset and reset active 01: core1
NMI 0: no local 10: both
0: DSP enabled reset
active 0: disabled
Reset Value: 0x00
DM2.BIOS function DM2_dspConfig
Table 5.4: DSPCTRL Register

This register is mainly used for initial configuration and production
tests.
The BOOTMUX bit is set by the startup procedure after the DSP
has successfully boot-loaded. If any changes are made to this
register, either direct or through BIOS function DM2_dspConfig,
make sure the BOOTMUX bit is set to keep the GPIO pins avail-
able.
Bit 3 LRESETNMIEN is used in combination with the CORESEL
bits 1 and 0 to enable and route NMI events to the desired core(s).
An NMI can be generated by a temperature or fan alarm or by an
external device pulling the D.Module ALERT pin low.
© D.SignT 2013 Doc.Rev. 1.12 24

5.4 SETUPSTAT
D7..D3 D2 D1 D0
unused, 0 SETUPN IN1N IN0N
read only read only read onyl
DM2.BIOS function DM2_dspSetupstat
Table 5.5: SETUPSTAT Register

This register is read only. It reflects the inverted state of the
SETUPN, IN1N and IN0N pins on the COM connector. Similar to
the SETUPN and IN0N usage controlling the C6657 board startup
behaviour, these pins can be used in an application program to
control operation mode (expert mode, user mode), invoke calibra-
tion routines, etc,
5.5 FLASHCTRL
D7..D2 D1 D0
unused, 0 NANDWP SPIWP
1: write protect 1: write protect
0: not protected 0: not protected
Reset Value: 0x01

DM2.BIOS function: DM2_flashWriteProtect
Table 5.6: FLASHCTRL Register

Control write protection of the NAND and SPI NOR flash memories.
At system startup the lower 128K bytes of the SPI NOR flash are
write protected, i.e. program and erase operations in this area are
disabled. The size of the write protected area in the SPI NOR flash
is set in the flash status register by BIOS function DM2_flashSet-
Status.
© D.SignT 2013 Doc.Rev. 1.12 25

5.6 GPIOMUX
This register is split in two parts: GPIOMUXLO controls the usage
of the External Bus Interface GPIO0 and GPIO1 pins, GPIOMUXHI
controls GPIO2 and GPIO3 pins.
Only one GPI pin is allowed to drive the TIMI0 or

TIMI1 DSP timer inputs!
D7..D4 D3.. D0
GPIO1MUX GPIO0MUX
0000: DSP_GPIO[5] in 0000: DSP_GPIO[4] in
0001: DSP_TIMI0 0001: DSP_TIMI0
1000: DSP_GPIO[5] out 1000: DSP_GPIO[4] out
1001: DSP_TIMO0 1001: DSP_TIMO0
1110: low 1110: low
1111: high 1111: high
Reset Value: 0x00
DM2.BIOS function: DM2_gpioMap
Table 5.7: GPIOMUXLO Register
D7..D4 D3.. D0
GPIO3MUX GPIO2MUX
0000: DSP_GPIO[7] in 0000: DSP_GPIO[6] in
1000: DSP_GPIO[7] out 1000: DSP_GPIO[6] out
1110: low 1110: low
1111: high 1111: high
Reset Value: 0x00
DM2.BIOS function: DM2_gpioMap
Table 5.8: GPIOMUXHI Register
© D.SignT 2013 Doc.Rev. 1.12 26

5.7 ETHCTRL
D7 D6..D1 D0
PHYRESET Unused, 0 PHYINT, read only
Reset Value: 0x80
DM2.BIOS function: DM2_phyReset, DM2_phyGetInt
Table 5.9: ETHCTRL Register
5.8 PCIECTRL
D7 D6, D5 D4 D3 D2 D1 D0
PCIE PCIESS CLKSEL SIDE1DIR SIDE0DIR SIDE1DAT SIDE0DAT
SSEN MODE
DSP pin DSP pins 1: internal 1: output 1: output If input: If input:
0: external 0: input 0: input state of pin state of pin
REFCLK in output: in output:
from GTP data driven data driven
connector on pin on pin
Reset Value: 0x00
DM2.BIOS function DM2_pcieConfig, DM2_pcieGetSide
Table 5.10: PCIECTRL Register

D7..D5 are used for production test only. If the PCIE configuration
should be changed use the DSP DEVSTAT register.
The SIDE1 and SIDE0 pins are GPIO signals routed to the GTP
connector. Use these to implement PCIe sideband signalling.
© D.SignT 2013 Doc.Rev. 1.12 27

5.9 BOOTMOD
This register is split in two parts, BOOTMODLO and BOOTMODHI.
It is reserved for production tests and initial configuration and
defines the DSP boot configuration.
D7 D6 D5 D4 D3 D2 D1 D0
BOOT7 BOOT6 BOOT5 BOOT4 BOOT3 BOOT2 BOOT1 BOOT0
Reset Value: 0x06
DM2.BIOS function DM2_dspSetBootmode
Table 5.11: BOOTMODLO Register
D7 D6, D5 D4 D3 D2 D1 D0
LENDIAN Unused, 0 BOOT12 BOOT11 BOOT10 BOOT9 BOOT8
Reset Value: 0x93
DM2.BIOS function DM2_dspSetBootmode
Table 5.12: BOOTMODHI Register
5.10 PRGIODATLO
D7 D6 D5 D4 D3 D2 D1 D0
PRGIO7 PRGIO6 PRGIO5 PRGIO4 PRGIO3 PRGIO2 PRGIO1 PRGIO0
Reset Value: 0x00
DM2.BIOS function DM2_prgioRead, DM2_prgioWrite, DM2_prgioWriteLo
Table 5.13: PRGIODATLO Register

Programmable IO ports PRGIO[7:0] are implemented in the board
logic. These bits are read and written via the PRGIODATLO
register. Writing these bits has no effect if the pin is configured as
an input.
© D.SignT 2013 Doc.Rev. 1.12 28

5.11 PRGIODIR
PRGIO[7:0] are completely implemented in the board logic.
PRGIO[15:8] are connected to the DSP GPIO[15:8] pins, but buf-
fered and level-shifted in the board logic.
This register is split into two parts: PRGIODIRLO controls the direc-
tion of the PRGIO[7:0] pins. PRGIODIRHI controls the buffer direc-
tion of the PRGIODIR[15:8] pins. The data direction of PRGIO[15:8]
must additionally programmed in the DSP GPIO registers. The
BIOS function DM2_prgioConfig takes care of the required configur-
ation and configures both board logic and DSP.
D7 D6 D5 D4 D3 D2 D1 D0
1: port pin is output
0 : port pin is input
Reset Value: 0x00
DM2.BIOS function DM2_prgioConfig
Table 5.14: PRGIODIRLO Register
D7 D6 D5 D4 D3 D2 D1 D0
1: port pin is output
0 : port pin is input
Reset Value: 0x00
DM2.BIOS function DM2_prgioConfig
Table 5.15: PRGIODIRHI Register
© D.SignT 2013 Doc.Rev. 1.12 29

D.Module.C6657 User Guide External Bus Interface
6 External Bus Interface

The D.Module2.C6657 external bus can be used in standard EMIF
mode or in UPP mode. In EMIF mode a 16-bit data bus, a 20-bit
address bus, two pre-decoded chip selects, and control signals are
available to connect memory-mapped peripheral devices. The bus
timing is widely configurable. In UPP mode the external bus inter-
face operates as a one or two channel synchronous fifo interface.
UPP mode allows a direct connection of high-speed peripherals like
data converters, cameras and FPGAs.
In both modes the external bus signals are fully buffered and level-
shifted to 3.3V LVCMOS. After power-on or a board reset, the
board always starts in EMIF mode.
Since the 6657 DSP multiplexes the EMIF and UPP signals, both
modes are exclusive, i.e. you cannot use EMIF and UPP simultan-
eously. This causes some restrictions if using UPP mode:
1. the NAND flash requires EMIF mode and cannot be used after
the bus interface is switched to UPP.
2. the board configuration registers are only accessible in EMIF
mode. Make sure all configurations are completed before
switching to UPP mode. This also applies to the PRGIO[15:8]
direction settings and the GPIO[3:0] multiplexers.
3. PRGIO[7:0] signals are implemented in the board configuration
registers. These PRGIO signals cannot be used in UPP mode.
However, PRGIO[7:0] outputs retain their states and can be
used to configure external devices before switching to UPP
mode.
The following table shows the mapping between the D.Module2

BUS connector pins and the DSP signals:
© D.SignT 2013 Doc.Rev. 1.12 30

Pin Name EMIF16 function UPP function

BUS2-9 D0 - CHA WAIT
BUS2-10 D1 - CHB WAIT
BUS2-11 D2 - CHA ENABLE
BUS2-12 D3 - CHB ENABLE
BUS2-14 D4 - CHA START
BUS2-15 D5 - CHB START
BUS2-16 D6 - CHA CLOCK
BUS2-17 D7 - CHB CLOCK
BUS1-36 D16 D0 DATA0
BUS1-21 A0 A23 -
BUS1-23 A1 A0 XDATA0
© D.SignT 2013 Doc.Rev. 1.12 31

Pin Name EMIF16 function UPP function

BUS1-31 A17 A16 -
BUS1-33 A18 A17 -
BUS1-34 A19 A18 -
BUS1-6 BUSCLK SYSCLKOUT -
BUS1-12 BE2N BE0N -
BUS1-14 BE3N BE1N -
BUS1-13 OEN OEN -
BUS1-15 RDN RDN -
BUS1-17 WRN WRN -
BUS1-18 WAITN WAIT1 X2TXCLK
BUS1-20 CS0N CE2N -
BUS1-22 CS1N CE3N -
Table 6.1: Bus Interface Signals
© D.SignT 2013 Doc.Rev. 1.12 32

6.1 UPP Mode

Because the board configuration registers are not accessible in
UPP mode, the UPP bus driver configuration is done via an I2C
device, a TCA6408.
Port Signal High(1) Low(0)

P0 UPP_N EMIF Mode UPP Mode
P1 DIR_LO DATA[7:0] = transmit DATA[7:0] = receive
XDATA[7:0] = transmit XDATA[7:0] = receive
P2 DIR_HI DATA[15:8] = transmit DATA[15:8] = receive
XDATA[15:8] = transmit XDATA[15:8] = receive
P3 DIR_CHA CHA = transmit CHA = receive
P4 DIR_CHB CHB = transmit CHB = receive
P[7:5] - don't care
Note; P[4:1] are don't care if P0 is high (EMIF Mode)
Table 6.2: TCA6408 Port Pins
The D.Module2.C6657 BIOS provides I2C functions to access this

device. To switch from EMIF to UPP mode proceed as follows:
1. make sure all interrupts and DMA transfers which use EMIF
resources are disabled to avoid unintentional EMIF accesses.
2. make sure all board configurations and initializations are com-
pleted, take TCA6408 device out of reset with BIOS function
DM2_busConfig();
3. configure the UPP bus interface via I2C: enable UPP, set direc-
tions of channel A and B control signals and set the directions
of the DATA and XDATA busses. These directions must match
the UPP peripheral configuration in step 4. A typical program is:
T_Handle h_i2c;
uint8_t i2c_tx[2];
h_i2c = DM2_i2cOpen (DM2_I2C0);

DM2_i2cConfig (h_i2c, 100000, 0);
© D.SignT 2013 Doc.Rev. 1.12 33

// enable TCA6408
DM2_busConfig(0);
// configure TCA6408 outport register to set

// the bus driver directions
// - UPP mode enable
// - Ch.A is output, uses DATA[7:0] and
// XDATA[7:0] drivers
// - Ch.B is input, uses DATA[15:8] and
// XDATA[15:8] receivers
i2c_tx[0] = DM2_I2C_TCA6408OUTPORTREG;
i2c_tx[1] = DM2_I2C_TCA6408OUTPORT_UPP
| DM2_I2C_TCA6408OUTPORT_LOWTX
| DM2_I2C_TCA6408OUTPORT_HIGHRX
| DM2_I2C_TCA6408OUTPORT_CHATX
| DM2_I2C_TCA6408OUTPORT_CHBRX;
DM2_i2cWrite
(h_i2c, DM2_I2C_TCA6408ADDR, i2c_tx, 2);
// configure TCA6408 ports as output,

// now the bus drivers are switched
// to the programmed directions
i2c_tx[0] = DM2_I2C_TCA6408CONFIGREG;
i2c_tx[1] = DM2_I2C_TCA6408CONFIG_DEFAULT;
DM2_i2cWrite
4. configure the 6657 UPP peripheral in the DSP:

- unlock the KICK registers
- write a 1 to PIN_CONTROL_1 register to enable UPP
- select the desired UPP clock source in the UPP_CLOCK
register
- lock the KICK registers
- reset the UPP peripheral (UPPCR register)
- configure the UPCTL,UPICR,UPTCR,and UPDLB
registers
- configure the UPP DMA
© D.SignT 2013 Doc.Rev. 1.12 34

- start UPP transfers by setting the ENABLE bit in the

UPPCR register
Please refer to the sample programs in the support software. If you

need to switch back to EMIF mode, disable UPP by writing the
default EMIF setting to the TCA6408:
i2c_tx[0] = DM2_I2C_TCA6408OUTPORTREG;
i2c_tx[1] = DM2_I2C_TCA6408OUTPORT_EMIF;
DM2_i2cWrite
The UPP peripheral configuration is described in the UPP User

GuideSPRUHG9. Use the CSL functions to configure the interface.
UPP can use one or two ports, each in 8- or 16-bit mode, receiver
and/or transmitter. If configured as a transmitter, the DSP gener-
ates the Clock signal. If an external transmit clock should be used,
this must have twice the desired frequency and is applied to the
X2TXCLK input. A receiver channel always requires an external
clock input. The START, ENABLE, and WAIT signals are used for
synchronization between DSP and peripheral devices. UPP data
transfers are always handled by a dedicated internal DMA control-
ler, it is not possible to access the UPP via CPU data transfers.
For detailed information about uPP mode please refer to the Texas
Instruments KeyStone Architecture Universal Parallel Port (uPP)
User Guide SPRUHG9.
© D.SignT 2013 Doc.Rev. 1.12 35

EN
UPP_CH0_WAIT D0
UPP_CH0_ENABLE D2
UPP_CH0_START D4
UPP_CH0_CLK D6
DIR
EN
UPP_CH1_WAIT D1
UPP_CH1_ENABLE D3
UPP_CH1_START D5
UPP_CH1_CLK D7
DIR
EN
UPP_2XTXCLK WAIT_N
EN
UPPD[7:0] D[23:16]
DIR
EN
UPPD[15:8] D[31:24]
DIR
EN
UPPXD[7:0] A[8:1]
DIR
EN
UPPXD[15:8] A[16:9]
DIR
P0 P3 P4 P1 P2 D.Module2 BUS1,
C6657 I2C BUS2 connector
RESET TCA6408
BUSCONFIG.UPPRES
Figure 6.1: Bus Interface in UPP Mode
© D.SignT 2013 Doc.Rev. 1.12 36

6.2 EMIF Mode

EMIF mode is used for memory-mapped peripherals. Only 16-bit
data bus configurations are supported. Byte-access is supported
via two byte enable signals: BE2_N is activated on access to the
low byte, BE3_N decodes the high byte.
Two pre-decoded chip selects are available: CS0_N is activated if
the memory area 0x78000000..0x7BFFFFFF is accessed, CS1_N
is activated on access to 0x7C000000..0x7FFFFFFF. For each chip
select area the bus timing is individually configurable in the 6657
EMIF16 peripheral controller: for CS0_N write the desired timing to
the AC3R register, CS1_N timing is configured in AC4R. Additional
wait states can be inserted via the WAIT_N input. This signal maps
to DSP signal WAIT1. The ACxR registers also specify if external
wait requests are enabled, the polarity and timeouts are configured
in the AWCCR register. Please refer to the TMS320C6657 EMIF16
User Guide SPRUGZ3, and use CSL functions to configure the
EMIF16 peripheral.
The default configuration of the D.Module2.C6657 defines a 2-5-2
timing (10ns Setup, 24ns Strobe, 10ns Hold) for both chip select
areas, with external wait state requests enabled (WAIT_N low).
Internal latencies and synchronizations in the 6657 processor do
not allow to use the EMIF16 at maximum speed if CPU data trans-
fers are used. For highest throughput use EDMA transfers.
For detailed information about the EMIF please refer to the Texas
Instruments KeyStone Architecture External Memory Interface
(EMIF16) User Guide SPRUGZ3.
© D.SignT 2013 Doc.Rev. 1.12 37

EMIF_CE2 CS0_N
EMIF_CE3 CS1_N
EMIF_OE OE_N
EMIF_RD RD_N
EMIF_WR WR_N
EMIF_R/W
DIR
EMIF_D[15:0] D[31:16]
EN
&
EMIF_A[23] A[0]
EMIF_A[18:0] A[19:1]
EMIF_WAIT1 WAIT_N
SYCLKOUT BUSCLK
BUSCONFIG.RESOUT RESOUT_N
D.Module2 BUS1,
C6657 BUS2 connector
Figure 6.2: Bus Interface in EMIF Mode
© D.SignT 2013 Doc.Rev. 1.12 38

6.3 Auxiliary Bus Interface Signals

Also located on the BUS1 and BUS2 connectors are the following
auxiliary bus interface signals:
RESOUT_N (BUS1-5 and BUS2-60)
Reset output, use to keep external peripherals in reset until the
DSP configuration is completed. This signal is driven active (low) at
power-on or reset. It remains low until explicitly set by BIOS func-
tion DM2_busConfig.
INT[2:0]_N (BUS1-10, 9, and 7)
External interrupt inputs, mapped to the 6657 GPIO[2:0] pins.
These signals can be used as interrupts or EDMA trigger events,
depending on the 6657 configuration. Use the CSL functions to
configure the 6657 interrupt subsystem. These signals use 10K on-
board pullup resistors.
GPIO[3:0] (BUS2-8, BUS2-7, BUS1-58, BUS1-57)
General purpose I/O to be used as additional flags, interrupts,
EDMA triggers or clock signals to/from peripheral devices. A multi-
plexer on the board connects these GPIO pins to various DSP sig-
nals:
- DSP GPIO input (GPIO[7:4])
- DSP GPIO output (GPIO[7:4])
- DSP timer input (TIMI0 or TIMI1)
- DSP timer output (TIMO0 or TIMO1)
It is also possible to drive a high or low level directly without using a
DSP GPIO pin. Each GPIO pin maps to a dedicated DSP GPIO sig-
nal:
- Bus GPIO0 <-> DSP GPIO4
© D.SignT 2013 Doc.Rev. 1.12 39

Care must be taken if the GPIO pins are mapped to DSP timer
inputs: Only one GPIO pin is allowed to drive the DSP timer input,
do not assign more than one GPIO signal to the same timer input! A
timer output may however be mapped to multiple Bus GPIO pins.
Use BIOS function DM2_gpioMap to assign signals to the Bus
GPIO pins. This function will also configure the DSP GPIO peri-
pheral accordingly. Use the CSL functions to read and write DSP
GPIO signals.
GPIO.MUXLO
DSP_GPIO[4]
3.3V
DSP_GPIO[5]
DSP_GPIO[6]
GPIO0
DSP_GPIO[7]
+3.3V
0V
GPIO1
C6657
GPIO2
3.3V
DSP_TIMI0
DSP_TIMI1
GPIO3
DSP_TIMO0
DSP_TIMO1
+3.3V D.Module2 BUS1,

0V BUS2 connector
GPIO.MUXHI
Figure 6.3: Bus GPIO Signals
© D.SignT 2013 Doc.Rev. 1.12 40

BUSCLK (BUS1-6)
In EMIF mode all external bus signals switch synchronously to this
clock output. Can be used to interface synchronous logic, or as a
general purpose clock source. The BUSCLK frequency is fixed to
1/6 CPU Core clock, e.g. 166.67MHz on a 1GHz TMS320C6657
6.4 Usage and Routing Guidelines

The Bus Interface is a master-only device: address and control sig-
nals in EMIF mode are always outputs driven by the DSP. It is not
possible to access on-board memories or devices via the bus inter-
face from an external bus master.
All Bus Interface signals are buffered by AVCH level-translating buf-
fers. These devices use a "bus-hold" circuit to weakly hold the last
level when switched into 3-state mode, and thus avoid floating sig-
nals. If your application requires external pull-up or pull-down resist-
ors on data bus signals, these must be low enough to supply suffi-
cient current to override the bus hold circuit. 30µA minimum are
required.
The bus interface signals are extremely fast with rise and fall times
in order of 1ns. Long connections to the bus interface need to be
properly terminated to avoid transmission line reflections. Use
either series termination resistors (about 33 ohms) located close to
the D.Module2 pins or RC terminations at the end of the line. All
connections should be routed with a characteristic impedance
about 50 ohms. The GND return path is important too: use a solid
GND plane next to the signal layer and avoid GND plane gaps
below the signal traces. If routing requires to swap layers make
sure the associated GND planes are interconnected with a via next
to the signal via. Connect the GND plane to all available SGND pins
on the BUS1 and BUS2 connectors.
© D.SignT 2013 Doc.Rev. 1.12 41

D.Module.C6657 User Guide McBSP
7 McBSP
The two C6657 Multi-Channel Buffered Serial Ports are available
on the BUS-2 and EXP connectors. These ports are buffered by
auto-direction sensing level shifters to achieve 3.3V LVCMOS level
compliance.
Pin Signal DSP-Signal

BUS2-46 DATR0 DR0 (input)
BUS2-47 CLKR0 CLKR0 (in, out)
BUS2-48 FSR0 FSR0 (in, out)
BUS2-49 DATX0 DX0 (output)
BUS2-51 CLKX0 CLKX0 (in, out)
BUS2-52 FSX0 FSX0 (in, out)
EXP-63 CLKS0 CLKS0 (input)
BUS2-54 DATR1 DR1 (input)
BUS2-55 CLKR1 CLKR1 (in, out)
BUS2-56 FSR1 FSR1 (in, out)
BUS2-57 DATX1 DX1 (output)
BUS2-58 CLKX1 CLKX1 (in, out)
BUS2-59 FSX1 FSX1 (in, out)
EXP-64 CLKS1 CLKS1 (input)
Table 7.1: McBSP Signals
The McBSP is programmed using the Texas Instruments Chip Sup-

port Library defines and functions. Please refer to the Texas Instru-
ments KeyStone Architecture Multichannel Buffered Serial Port
(McBSP) User Guide SPRUHH0.
© D.SignT 2013 Doc.Rev. 1.12 42

D.Module.C6657 User Guide SPI
8 SPI
The C6657 provides a single SPI master port with two Slave Select
outputs. SPICS0 is connected to the on-board SPI NOR Flash.
SPICS1 is available to enable external SPI slave devices. SPI slave
select signals are active-low, I.e. a low level activates a slave
device. Slave devices must disable (3-state) their MISO output if
not selected. The external SPI signals are fed through level shifters
and are 3.3V LVCMOS compliant.
The C6657 SPI peripheral uses four SPIFMT registers. These
registers allow to pre-define different formats (clock, phase, polarity,
word-lenght) to match the slave device. SPIFMT0 is reserved for
use with the on-board SPI NOR Flash, no restrictions apply to SPI-
FMT1..3. Please use the DM2.BIOS SPI functions or the Texas
Instruments Chip Support Library to program the SPI port.
If more than one external slave select lines are required, you can
use the PRGIO signals as slave select. These signals must be
enabled before the slave device is accessed, and disabled if the
transfer is complete by using DM2.BIOS function DM2_prgioWrite().
You may add external OR-gates to logically combine a PRGIO sig-
nal with SPICS1 to assure the slave select line is automatically
enabled and disabled with the timing defined in the SPIFMT
register.

EXP-48 SPI_SIMO SPIDOUT
EXP-50 SPI_SOMI SPIDIN
EXP-52 SPI_CLK SPICLK
EXP-56 SPI_SS SPICS1
Table 8.1: SPI Signals
Please refer to the KeyStone Architecture Serial Peripheral Inter-

face (SPI) User Guide SPRUGP2
© D.SignT 2013 Doc.Rev. 1.12 43

D.Module.C6657 User Guide I²C
9 I²C
The I²C bus is available on the COM connector. It is 3.3V LVCMO
compliant.
Pin Signal
COM-37 SCL
COM-39 SDA
Table 9.1: I2C Signals
The DM2.BIOS provides initialization and data transfer functions.

Four on-board I2C devices exist:
• the AVR micro-controller implementing RTC and FAN control, I2C
slave address = 0x49.
• the TMP101 temperature sensor, slave address = 48.
• the TCA6408 port extender, used for the external bus interface
uPP configuration, slave address = 0x20.
• the Si5338 clock synthesizer, slave address = 0x70.
I2C clock must be 100kHz to communicate with the AVR, all other
devices support 400kHz clock.
The Si5338 clock synthesizer is programmed by the AVR at system
start-up. The DSP must not re-program this device.
Please refer to the KeyStone Architecture Inter-IC Control Bus (I2C)

User Guide SPRUGV3.
© D.SignT 2013 Doc.Rev. 1.12 44

D.Module.C6657 User Guide PRGIO
10 PRGIO
The 16 PRGIO signals PRGIO[15:0] on the D.Module2 COM con-
nector can be used for various functions, e.g. read input keys, drive
LEDs, or configure external peripheral devices.
PRGIO[7:0] are controlled by registers in the board logic. Since the
board logic is connected to the DSP EMIF, these PRGIO ports are
not accessible if the DSP uses the UPP peripheral. (please refer to
"External Bus Interface").
PRGIO[15:8] are connected to the DSP GPIO[15:8] signals and can
be used without restrictions in both EMIF and UPP mode.
PRGIO[15:8] can also be used as additional interrupts or EDMA
trigger events if the DSP is configured accordingly.
3.3V
DSP_GPIO[15:8] PRGIO[15:8]
PROGIO.DIRHI
C6657
3.3V
EMIF PRGIO.DATLO PRGIO[7:0]
D.Module2 COM
PRGIO.DIRLO Connector
Figure 10.1: PRGIO Connections
All PRGIO pins use 3.3V LVCMOS I/O levels and have internal pull-
up resistors (approx. 25K). If long connections are used on inputs, it
is advisable to add lower value external pullup resistors for better
noise margin. If an input requires a pull-down resistor, this must be
© D.SignT 2013 Doc.Rev. 1.12 45

externally connected and its value must be low enough to override

the internal pullup. 3K3 is minimum, lower values are recommen-
ded to improve noise immunity.
To configure the PRGIO signals individually as inputs and outputs
use BIOS functions DM2_prgioConfig. This function also configures
the DSP GPIO peripheral accordingly.
To read the state of the pins use function DM2_prgioRead. To write
the PRGIO outputs use BIOS functions DM2_prgioWrite or DM2pr-
gioWriteLo. The WriteLo function will only write to PRGIO[7:0], the
ports implemented in the board logic. DM2_prgioWrite will write all
16 port bits. PRGIO[15:8] can also be read and written in the DSP
GPIO peripheral using CSL functions.
The 6657 DSP multiplexes its GPIO pins with the BOOTMODE
configuration: at device reset the BOOTMODE configuration must
be driven on the GPIO pins to select the desired boot mode. During
this time the PRGIO pins are isolated from the DSP to avoid com-
promising the BOOTMODE settings by external devices already
driving the PRGIO pins.
All PRGIO ports are configured as inputs on power-on or reset. If a
port is to be used as an output later, make sure to add an external
pull-down resistor if the signal is expected to be low at power-on.
The PRGIO signals remain inputs until explicitly configured by BIOS
function DM2_prgioConfig.
© D.SignT 2013 Doc.Rev. 1.12 46

Pin Name Source / Destination

COM-43 PRGIO0 Board Logic
COM-54 PRGIO8 DSP GPIO[8]
COM-56 PRGIO9 DSP GPIO[9}
Table 10.1: PRGIO Routing
© D.SignT 2013 Doc.Rev. 1.12 47

D.Module.C6657 User Guide Interrupts
11 Interrupts
All 6657 GPIO signals are able to generate interrupts and/or EDMA
trigger events. The mapping of the predefined interrupt signals is:
BUS INT0_N -> DSP_GPIO[0]
ETH PHY INT -> DSP_GPIO[3]
Additional interrupts can be generated from BUS GPIO[3:0] if these
are routed to the DSP GPIO signals GPIO[7:4], see "External Bus
Interface" for more information about BUS GPIO pin routing.
It is also possible to use the PRGIO[15:8] pins on the COM con-
nector as interrupt sources if the corresponding input is configured
as an input. The PRGIO[15:8] signals are connected to DSP
GPIO[15:8].
GPIO0 INT0_N
GPIO1 INT1_N
GPIO2 INT2_N
88E1112
GPIO3 ETH PHY D.Module2 BUS1
INT Connector
3.3V
NMI ALERT
D.Module2 EXP
TMP101 ATMega Connector
C6657
ALERT ALERT
I2C
LRESETNMIEN DSP.LRESETNMIEN
CORESEL0 DSP.CORESEL0
CORESEL1 DSP.CORESEL1
Figure 11.1: Interrupts
© D.SignT 2013 Doc.Rev. 1.12 48

D.Module.C6657 User Guide Interrupts
The dedicated BUS INTx pins have 10K pull-up resistors on board,
all others use internal pull-up resistors, approx. 25K. This configura-
tion assumes default falling-edge triggered interrupts. If the interrupt
polarity is reversed to rising-edge triggered, and the signals are
driven from open source or 3-state logic, external pull-down resist-
ors are required. These must be sufficiently low to override the pull-
up resistors: For BUS INT[2:0]_N, the minimum value is 1K, for all
other signals the minimum value is 3K3.
The 6657 NMI (non maskable interrupt) input is connected to the
on-board ALERT signal. An NMI is generated if the board temperat-
ure threshold is exceeded, or if an attached fan fails. The board
temperature threshold is programmed in the TMP101 temperature
sensor. If a fan is used for forced convection cooling, the AtMega
controller on the D.Module2.C6657 board can be instructed to con-
trol the fan speed and monitor the fan tacho output. The ALERT
signal will be asserted if a fan speed > 0 is requested, but no tacho
pulses are detected.
ALERT is an open-drain signal. It is also accessible on the EXP
connector pin 31. The open-drain configuration allows to connect
external sources with open-drain outputs, which can also trigger an
NMI. The NMI must be enabled and routed to one of the two DSP
cores, or to both cores. This is a hardware setting which is done in
the Board Configuration Logic. Use BIOS function DM2_dspConfig:
DM2_dspConfig(
DM2_DSPGPIOENABLE
| DM2_LRESETNMIENABLE
| DM2_CORESEL0);
will enable NMI and route NMI events to Core 0. It is also required
to configure the 6657 interrupt subsystem to handle NMI events.
Use the CSL functions to configure the DSP appropriately. Please
refer to the “temperature” and “fan” support software example pro-
jects. Detailed information is found in the Texas Instruments Key-
Stone Architecture Interrupt Controller (INTC) User Guide
SPRUGW4.
© D.SignT 2013 Doc.Rev. 1.12 49

D.Module.C6657 User Guide SPI Flash Memory
12 SPI Flash Memory

The D.Module2.C6657 is equipped with a 64Mbit (8 Mbytes) serial
NOR Flash, connected to the 6657 SPI port. On power-up or reset
the 6657 boot loads from this Flash memory.
The Flash memory reserves the lower 128K bytes to store the hard-
ware configuration, BIOS, and Recovery and Setup programs.This
area is write protectd by default to prevent accidental data loss.
Address area 0x020000 to 0x02FFFF is intended for the Module
Configuration File. This is a text file which defines configuration set-
tings like UART parameters, TCP/IP network settings, location of
application programs in the Flash Memory, etc. The configuration
file should also be used to store application parameters, configura-
tions, calibration data, etc. This will significantly simplify system
maintenance. The remaining Flash is free for user data and pro-
grams. Write protection settings can be changed in the application
program to protect user data and programs from accidental data
loss.
Address Usage Notes

0x000000 Boot Config Table Write Protected
0x001000 BIOS and Recovery Utility
0x008000 Hardware Configuration Data
0x010000 Setup Utility
0x020000 Module Configuration File Free for user
0x030000 - Free for user programs and data
0x7FFFFF
Table 12.1: SPI Flash Layout
To use the Flash Memory call BIOS function DM2_flashOpen. This

function will also setup the SPI interface. The SPI peripheral has
four format registers to configure four individual timings and data
© D.SignT 2013 Doc.Rev. 1.12 50

formats. Format register 0 is reserved for Flash access and must

not be changed. The 6657 SPI peripheral provides two chip select
lines. CS0 is used for the Flash Memory.
To read data from the Flash Memory use BIOS function
DM2_flashReadBlock. Before data can be written to the Flash, the
destination sector must be erased. The Flash Memory is organized
in 4 Kbyte sectors. If larger amounts of data must be written, it is
also possible to erase 64 Kbyte blocks. Write protected areas can-
not be erased. Use BIOS functions DM2_flashSectorerase or
DM2_flashBlockerase. Once a sector or block is erased write data
using BIOS function DM2_flashWriteBlock. Flash operations are
slow, especially the block erase operations may take up to 1
second to complete. To check the completion status of a Flash
operation call function DM2_flashGetStatus.
To change the write protection settings use BIOS function
DM2_flashSetStatus.
A software update feature can be implemented using function
DM2_flashIhexUpload This function accepts Intel-Hex programming
files. A callback function must be provided which reads the Intel-
Hex file line by line. This makes it possible to receive the program-
ming file from various sources: UART, USB, Ethernet, or via PCIe
interface. DM2_flashIhexUpload decodes the Intel-Hex format and
takes care of sector erase and programming, no further action is
required. An example using the USB-UART (UART 1) to read the
Intel-Hex file is:
© D.SignT 2013 Doc.Rev. 1.12 51

// callback function for DM2_flashIhexUpload

char *uart_readline (void *link)
{
static char dst[128]; // line buffer
return (char *)DM2_uartReadStr (

(T_Handle)link,
dst,
sizeof(dst),
DM2_UART_NOTIMEOUT,
DM2_UART_ECHO);
}
void main (void)

{
int32_t result;
T_Handle h_uart;
T_DM2_uartConfigStruct myUartCfg =
{115200, 8, 'N', 1, 'R', 0, 0};
// use RTS/CTS auto flow control to halt UART

// transfers while Flash is busy
DM2_uartConfig (h_uart, &myUartCfg);
DM2_uartWriteStr (
h_uart,
"Ready, waiting for Intel-Hex File\r\n",
DM2_UART_NOTIMEOUT);
result = DM2_flashIhexUpload(
uart_readline,
h_uart);
switch (result)
{
// evaluate result:
// 0 success
// 1 terminated
// 2 Intel-Hex format error
// 3 Intel-Hex checksum error
// 4 Flash Erase or Write Error
}
}
© D.SignT 2013 Doc.Rev. 1.12 52

To boot-load a program from Flash Memory call function

DM2_flashBootload. If both cores are used, first halt Core 1 (if Core
1 is already running), then boot-load the program for Core 1, finally
boot-load the Core 0 program. Boot-loading Core 0 will automatic-
ally start the execution once the boot-load is complete. The Core 0
program then starts Core 1 by issuing a Core Reset with BIOS
function DM2_resetCore(1).
The Flash lifetime is limited by the number of erase and write
cycles, typically 100000 cycles. This should be considered if the
Flash is used to log events. Use a large amount of Flash Memory
and a round-robbin scheme to minimize erase cycles.
© D.SignT 2013 Doc.Rev. 1.12 53

D.Module.C6657 User Guide UART and USB
13 UART and USB

The C6657 provides two UART ports. UART 0 is connected to a
line driver which is configurable to RS232, RS422 and RS485.
These signals are available on the COM connector:
COM Connector RS232 RS422

19 CTS input B input
21 RxD input A input
20 RTS output Z output
22 TxD output Y output
Table 13.1: UART Connections

Use BIOS function DM2_uartLineif to configure the line interface.
For an RS485 half-duplex system, connect B-Z, and A-Y. In this
half-duplex configuration the line interface must be switched manu-
ally to receive or transmit mode using BIOS function DM2_uart-
Lineif().
UART1 is connected to a USB-UART bridge. A Virtual Com Port

driver is required on the counterpart end.
COM Connector USB

13 VCC
14 D+
15 GND
16 D-
Table 13.2: USB Connections
Please refer to the Texas Instruments KeyStone Architecture Uni-

versal Asynchronous Receiver/Transmitter (UART) User Guide
SPRUGP1.
© D.SignT 2013 Doc.Rev. 1.12 54

D.Module.C6657 User Guide Ethernet
14 Ethernet
The D.Module2.C6657 provides a 1000Base-T Ethernet Port. Mag-
netics are included on-board. Alternatively a fibre-optic transceiver
can be connected. To use the Ethernet port the PHY has to be
taken out of reset by calling BIOS function DM2_phyReset(); The
PHY is a Marvell 88E1112. It is connected to the DSP via the
SGMII and MDIO ports. The PHY address is 0.
The SGMII reference clock on the D.Module2.C6657 is 156.25MHz.
The SGMII port PLL has to be programmed accordingly. Please
refer to the sample software.
The PHY status LEDs are included on board. If you prefer to use
external status LEDs the on-board LEDs should be de-soldered.
Pin Signal Description RJ45 (8P8C)

COM-32 ETH_TX+/TP0+ 10/100: Tx+, 1000: TP0+ (BI_DA+) 1
COM-34 ETH_TX-/TP0- 10/100: Tx-, 1000: TP0- (BI_DA-) 2
COM-31 ETH_RX+/TP1+ 10/100: Rx+, 1000: TP1+ (BI_DB+) 3
COM-33 ETH_RX-/TP1- 10/100: Rx-, 1000: TP1- (BI_DB-) 6
COM-26 ETH_TP2+ 1000: TP2+ (BI_DC+) 4
COM-28 ETH_TP2- 1000: TP2- (BI_DC-) 5
COM_25 ETH_TP3+ 1000: TP3+ (BI_DD+) 7
COM-27 ETH_TP3- 1000: TP3- (BI_DD-) 8
EXP-3 ETH_LED1 connected to PHY STATUS 0
EXP-5 ETH_LED2 connected to PHY STATUS 1
EXP-2 ETH_FIN+ Fibre-Transceiver RX+
EXP-4 ETH_FIN- Fibre-Transceiver RX-
EXP-8 ETH_FOUT+ Fibre-Transceiver TX+
EXP-10 ETH_FOUT- Fibre-Transceiver TX-
EXP-7 ETH_FSD Fibre-Transceiver Signal Detect
Table 14.1: Ethernet Connections
© D.SignT 2013 Doc.Rev. 1.12 55

D.Module.C6657 User Guide Ethernet
If a Fibre-Transceiver is used please refer to its data sheet and

application notes for the recommended interface to the Marvell
88E1112 PHY. Additional level shifting and termination resistors
may be required, depending on the Fibre-Transceiver architecture
and operating voltage:
• The signal detect input ETH_FSD is terminated on-board by a 82
ohms resistor to GND.
• The receiver input ETH_FIN+ / ETH_FIN- is terminated with 100
ohms.
MDI0P ETH_DA_P
MDI0N ETH_DA_N
100Base-Tx
MDI1P ETH_DB_P
CS1_N
MDI1N ETH_DB_N
1000Base-T
MDI2P ETH_DC_P
MDI2N ETH_DC_N
MDI3P ETH_DD_P
MDI3N ETH_DD_N
ETH_GND
ETH.RES RESET D.Module2 COM

Connector
ETH.INT INT
240R
STATUS0 ETH_LED0
240R
STATUS1 ETH_LED1
R1315 R1316
0R 0R
100R
FINP ETH_FIN_P
FINN ETH_FIN_N
R1310 NP
FOUTP ETH_FOUT_P
CS1_N
FOUTN ETH_FOUT_N
R1311 NP
SIGDET ETH_SD
82R
D.Module2 EXP
88E1112 ETH PHY Connector
Figure 14.1: Ethernet Connections
Detailed information is found in the Texas Instruments KeyStone

Architecture Gigabit Ethernet (GbE) Switch Subsystem User Guide
SPRUGV9.
© D.SignT 2013 Doc.Rev. 1.12 56

D.Module.C6657 User Guide PCIe and SRIO
15 PCIe and SRIO

PCI Express and Serial Rapid IO allow high-speed data transfers to
a PC and/or to a FPGA. These signals are available on the GTP
connector.
PCIe cable adapters (PCI Express x 1 Gen2) are available to inter-
face the D.Module2.C6657 to a PC. The PCIe external cable spe-
cification defines additional sideband signals. CPRSNT# and
CPERST# can be implemented using the PCIE_SIDE0 and
PCIE_SIDE1 GPIO signals available on the GTP connector. These
GPIO signals can be configured and written using D.Module2.BIOS
function DM2_pcieConfig() and read via DM2_pcieGetSide().
The reference clock for the PCIe interface is generated on-board
(100MHz) or externally supplied via the GTP connector. BIOS func-
tion DM2_pcieConfig() is used to select the desired reference clock
source.
For SRIO the reference clock is generated on-board and is fixed to
156.25 MHz
The PCIe and SRIO transmit signals are directly connected to the
corresponding C6657 pins, the receive signals are AC-coupled via
100n capacitors.
Detailed information is found in the Texas Instruments KeyStone

Architecture Peripheral Component Interconnect Express (PCIe)
User Guide SPRUGS6 and in the Serial RapidIO (SRIO) User
Guide SPRUGW1.
© D.SignT 2013 Doc.Rev. 1.12 57

SRIO_TX0_P SRIO_TX0_P
SRIO_TX0_N SRIO_TX0_N
SRIO_RX0_P SRIO_RX0_P
SRIO_RX0_N SRIO_RX0_N
SRIO_TX1_P SRIO_TX1_P
SRIO_TX1_N SRIO_TX1_N
SRIO_RX1_P SRIO_RX1_P
SRIO_RX1_N SRIO_RX1_N
PCIE_TX0_P PCIE_PERp0
PCIE_TX0_N PCIE_PERn0
PCIE_RX0_P PCIE_PETp0
PCIE_RX0_N PCIE_PETn0
PCIE_TX1_P PCIE_PERp1
PCIE_TX1_N PCIE_PERn1
PCIE_RX1_P PCIE_PETp1
PCIE_RX1_N PCIE_PETn1
PCIE.SIDE0DAT PCIE_SIDE0
DIR
PCIE.SIDE0DIR
PCIE.SIDE1DAT PCIE_SIDE1
DIR
PCIE.SIDE1DIR
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_CLK_P
PCIE_CLK_N
D.Module2 GTP
Connector
C6657 PCIE.CLKSEL 100MHz
Figure 15.1: PCIe and SRIO Connections
© D.SignT 2013 Doc.Rev. 1.12 58


GTP-A2 PCIe_PETp0 PCIERXP0 via 100n cap
GTP-A3 PCIe_PETn0 PCIERXN0 via 100n cap
GTP-B3 PCIe_PETp1 PCIERXP1 via 100n cap
GTP-B4 PCIe_PETn1 PCIERXN1 via 100n cap
GTP-A5 PCIe_PERp0 PCIETXP0
GTP-A6 PCIe_PERn0 PCIETXN0
GTP-B6 PCIe_PERp1 PCIETXP1
GTP-B7 PCIe_PERn1 PCIETXN1
GTP-A8 PCIe_REFCLKp PCIECLKP via MUX and 100n cap
GTP-A9 PCIe_REFCLKn PCIECLKN via MUX and 100n cap
GTP-B9 PCIe_SIDE0 -
GTP_B10 PCIe_SIDE1 -
GTP-C3 SRIO_RX0P RIORXP0 via 100n cap
GTP-C4 SRIO_RX0N RIORXN0 via 100n cap
GTP-D2 SRIO_RX1P RIORXP1 via 100n cap
GTP-D3 SRIO_RX1N RIORXN1 via 100n cap
GTP-C6 SRIO_TX0P RIOTXP0
GTP-C7 SRIO_TX0N RIOTXN0
GTP-D5 SRIO_TX1P RIOTXP1
GTP-D6 SRIO_TX1N RIOTXN1
Table 15.1: PCIe and SRIO Signals
© D.SignT 2013 Doc.Rev. 1.12 59

D.Module.C6657 User Guide Real-Time Clock
16 Real-Time Clock
The RTC is implemented in the ATmega48 controller on the D.Mod-
ule2.C6657 board. The DSP writes or reads the RTC via I2C.
The slave address is 0x49
The RTC_READ command is 0x10
The RTC_WRITE command is 0x20
Data is transferred in six bytes using the C struct tm format:
sec(ond) 0..59
min(ute) 0..59
hour 0..23
mday 1..31
mon(th) 0..11
year 0..255 offset from 1900
Read RTC:
.---.--------------.--.----------.---.---.---------------.---.
| S | SLAVEADDR +W | a| RTC_READ | a | S | SLAVEADDR + R | a |
'---'--------------'--'----------'---'---'---------------'---'
.-----.--.-----.--.-----.--.-----.--.-----.--.-----.----.---.
| sec | A| min | A| hour| A| mday| A| mon | A| year| NA | P |
'-----'--'-----'--'-----'--'-----'--'-----'--'-----'----'---'
Write RTC:
.---.---------------.--.-----------.---.
| S | SLAVEADDR + W | a| RTC_WRITE | a | ...
'---'---------------'--'-----------'---'
.----.---.----.---.-----.---.-----.---.----.---.-----.---.---.
| SEC| a | MIN| a | HOUR| a | MDAY| a | MON| a | YEAR| a | P |
'----'---'----'---'-----'---'-----'---'----'---'-----'---'---'
Legend:
S = start, generated by master
P = stop, generated by master
A = Acknowledge, generated by master
NA = Not Acknowledge, generated by master
© D.SignT 2013 Doc.Rev. 1.12 60

D.Module.C6657 User Guide Real-Time Clock
a = Acknowledge, generated by slave

DATA = data transmitted by master
data = data transmitted by slave
The RTC sample program in the support software demonstrates

RTC writes and reads using the D.Module2.BIOS I2C functions.
The RTC is not calibrated. Temperature drift and aging of the
32768Hz watch crystal will degrade accuracy. If precise timing is
required the RTC should be synchronized to a reference from time
to time. Daylight saving must be implemented by the user. Backup
power loss can be detected by checking the time: the RTC will then
start at Jan 1, 1900, 00:00:00h.
RTC standby power can be supplied by an external 3V backup bat-
tery connected to pin EXP-51 (RTC_BAT). The current consump-
tion is approx. 2µA at room temperature. Short time power loss (5
to 10 seconds) is buffered by a large capacitor on the 6657 board.
© D.SignT 2013 Doc.Rev. 1.12 61

D.Module.C6657 User Guide Fan Control and Supervision
17 Fan Control and Supervision

The fan control is implemented in the ATmega48 controller on the
D.Module2.C6657 board. The DSP writes or reads the fan control
via I2C.
The I2C slave address is 0x49.
Three commands are implemented:
FAN_SETPWM (0x30): write the PWM output to control fan speed
FAN_GETREV (0x40): read tacho pulse count
FAN_SETALERT (0x50): generate an ALERT (connected to DSP
NMI) if the tacho pulse count falls below
the specified limit.
Each command is followed by one data byte
Read Revolutions:
.---.---------------.--.------------.---.---.---------------.
| S | SLAVEADDR + W | a| FAN_GETREV | a | S | SLAVEADDR + R |
'---'---------------'--'------------'---'---'---------------'
---.-----.----.---.
a | rev | NA | P |
---'-----'----'---'
Write PWM:
.---.---------------.--.------------.---.-----.---.---.
| S | SLAVEADDR + W | a| FAN_SETPWM | a | PWM | a | P |
'---'---------------'--'------------'---'-----'---'---'
Write Alert Limit:

.---.---------------.--.--------------.---.-------.---.---.
| S | SLAVEADDR + W | a| FAN_SETALERT | a | LIMIT | a | P |
'---'---------------'--'--------------'---'-------'---'---'
Legend:
© D.SignT 2013 Doc.Rev. 1.12 62

S = start, generated by master

P = stop, generated by master
A = Acknowledge, generated by master
NA = Not Acknowledge, generated by master
a = Acknowledge, generated by slave
DATA = data transmitted by master
data = data transmitted by slave
A fan can be connected as follows:
+12V
1K
FAN_PWMO (EXP-27)
Figure 17.1: Fan Connection
If the fan has a tacho output connect this signal to FAN_TACHIN

(EXP-29). This input has an on-board pullup resistor to 3.3V. The
signal level at the FAN_TACHIN must never exceed 3.5V.
The PWM can be changed from 0 to 255 = 0..100% duty cycle. The
system always starts at 100% (PWM = 255). The DSP can write the
desired value to control the fan speed via I2C. Fans require a min-
imum value (e.g. PWM > 50) to run - smaller values will stop the
fan. This value will rise with age, so use a safe margin.
If a fan with a tacho output is connected, the current revolution
count can be read via I2C. The fan controller counts the tacho
pulses for ½ second. Typical fans generate either 2 or 4 pulses per
revolution.
An ALERT NMI can be generated if the fan fails: write the minimum
revolution count using the FAN_SETALERT command. A value of 0
will disable the alert function. On system startup or following a reset
alerts are disabled. Additionally a PWM output of 0 will disable
© D.SignT 2013 Doc.Rev. 1.12 63

alerts. Please note that in case of a blocked fan, or if the PWM out-
put is too low to startup the fan, most fans will wobble back and
forth and thereby generate tacho pulses. Do not expect the revolu-
tion count to be exactly 0 if the fan is blocked. Many fans generate
about 16 tacho pulses per second when blocked, so 9 might be a
suitable alert threshold (alert if less than 9 pulses per 1/2 second).
This value might differ with fan type and must be empirically
determined.
The alert function checks the revolution count each second (two
measurement periods) to avoid false alarms caused by sporadic
loss of tacho pulses. If failure recovery is not possible, e.g. by
increasing the PWM output, new NMI events will be generated each
second. Send the FAN_SETALERT command with a value of 0 to
stop further NMIs.
You can use the sample project in the support software to control
your fan and determine the limits for minimum PWM duty cycle and
ALERT threshold.
© D.SignT 2013 Doc.Rev. 1.12 64

D.Module.C6657 User Guide Power Supply
18 Power Supply
The D.Module2.C6657 requires a single 3.3V +/-5% power supply.
The power supply must be connected to the COM connector pins 1-
4 (0V) and 5-8 (+3.3V).
All additionally required power rails for the DSP, Ethernet, DDR3,
etc. are generated on-board. The board logic ensures the proper
power supply sequencing. A power fail will reset the DSP. The
DSP will be re-started if the power supply rises above the minimum
level.
Power consumption mainly depends on the CPU usage and the
amount of external data transfers (e.g. to and from DDR3). In a typ-
ical application it will be 5-6W. Since short term power requirements
may be higher, we recommend to use a power supply which is able
to retain the 3.3V up to 3A peak current.
© D.SignT 2013 Doc.Rev. 1.12 65

D.Module.C6657 User Guide Thermal Considerations
19 Thermal Considerations
In a typical application the DSP itself will dissipate about 3.5W
power. A part of this heat is dissipated via the PCB board, but the
majority is dissipated via the heatsink. The large heatsink used on
the D.Module2.C6657 is suitable for convection cooling up to 55°C
environment temperature. If the environment temperature is higher,
forced cooling is required. Therefore the board provides a PWM
output to control a fan. The fan can be set to a suitable speed to
keep the board temperature within limits while keeping acoustic
noise as low as possible.
The board temperature can be read via I2C from a TMP101 sensor.
This sensor can be programmed to generate an alert signal and
send an NMI interrupt to the DSP if a temperature limit is exceeded.
Please refer to the “temperature” sample project in the support soft-
ware.
We strongly recommend to add temperature supervision to your
projects. High-speed processors are prone to thermal runaway, i.e.
if the CPU temperature rises, the baseline power consumption,
even without any CPU activity, will rise and hence increase the
power dissipation and CPU temperature even more.
© D.SignT 2013 Doc.Rev. 1.12 66

D.Module.C6657 User Guide Reset
20 Reset
On board power-supply supervisors provide a clean power-on reset
and reset the board if a power rail falls below its limit. A manual
reset input is available on the COM connector pin 11. Do not keep
the board in reset for prolonged time (several minutes), the silicon
technology of the 6657 does not allow this.
© D.SignT 2013 Doc.Rev. 1.12 67

D.Module.C6657 User Guide Module Configuration File
21 Module Configuration File

This is an ASCII text file stored in the SPI NOR Flash Memory and
read at system startup to configure the board. The UART configura-
tion and the addresses of the application program(s) stored in the
SPI NOR Flash are read from the Configuration File. The Startup
sequence will initialize and configure the UARTs accordingly. This
allows to use identical settings for all programs and the Setup Util-
ity.
The config file is organized in sections which are characterized with
square brackets, e.g. [UART0]. You can add arbitrary sections as
long as the names are unique. Comments can be added by using a
semicolon. Everything from semicolon to the end of the line is
ignored. A line must not exceed 128 characters,
The default Module Configuration File can be changed and/or
expanded with additional application-specific data. Use file
dm2c6657_cfg.txt from the support software
Install_Dir/D.SignT/Boards/DM2C6657/BoardSupport/
and make the desired modifications with a text editor. Then start the
Setup Utility on the C6657 board and upload the new Config File as
described in chapter “Setup Utility”.
Section [UART0] has two special entries: “line interface” configures
the line interface, similar to using BIOS function
DM2_uartSetLineif(). Setup requires a full-duplex connection, only
RS232 and 422 are supported. If a half-duplex RS485 line interface
is used, or if a sensor or a similar device is permanently connected
to UART0, you can disable UART0 in the Setup Utility by setting
entry “quietsetup” to 1. The Setup Utility then communicates only
via USB (UART1 on USB-UART bridge).
The Module Config File should also be used to specify application-
and user-specific settings, in contrast to including this data in the
source code. This will significantly ease system-maintenance if
parameters need to be changed.
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D.Module.C6657 User Guide Setup Utility
22 Setup Utility
The Setup Utility is a utility program for field maintenance and soft-
ware updates. It is permanently stored in the SPI NOR Flash and
can be invoked by holding the SETUPN input on the COM con-
nector low during a system reset or at power-on. Setup communi-
cates via UART and/or USB. Both interfaces are enabled by
default. Setup uses the communication settings specified in the
Module Configuration File. If the UART port is connected to system
hardware, e.g. a sensor, you can disable UART transfers in Setup
by changing the “quietsetup” parameter in the Module Config file to
'1'.
Data transfers to the Flash Memory require RTS/CTS

hardware flow control to stop data transfers while the
flash is busy. Setup will automatically configure the
UART accordingly, irrespective of the settings in the
Module Configuration File. Make sure your terminal
has RTS/CTS enabled before sending an Intel-Hex
program or Module Configuration file.
The Setup Utility supports the following commands, a command

can be cancelled by pressing <ESC>. Data and addresses are
entered in hexadecimal notation without a leading 0x.
u upload an Intel-Hex file or Module Configuration File to the SPI
NOR Flash. You are prompted for the file type <i> for Intel-Hex,
<c> for Config File. Make sure your terminal is set to RTS/CTS
hardware flow control, and transfer the file using ASCII / text
transfer mode.
d download the Module Config File. The download does start after
a key is pressed.
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D.Module.C6657 User Guide Setup Utility
b boot-load a program from the SPI NOR Flash. You are prompted
for the core number to boot (0 or 1) and the address of the pro-
gram file in the Flash Memory. This command can be used to
start auxiliary programs, e.g. diagnostic or calibration programs.
To test this mode enter 10000 – this will restart the Setup Utility
r read memory. Enter the data format <b>yte (8-bit), <h>alfword
(16-bit) or <w>ord (32-bit), followed by a <,> and the address or
address range. An address range is entered as <start>..<end>.
Example: r ↵ b,800000..8000ff ↵
w write memory. Enter the data format <b>yte (8-bit), <h>alfword
(16-bit) or <w>ord (32-bit), followed by a <,>, the address or
address range, a <,>, and the data. An address range is entered
as <start>..<end>. If an address range is specified, the entire
range is filled with the data pattern.
Example: w ↵ h,800000..8000ff,12ab ↵
i Information. This commands prints serial number, hardware and
firmware revisions and CPU configuration and revision data.
h help, print an overview of the available commands.
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D.Module.C6657 User Guide Getting Support
23 Getting Support
D.SignT Support:
http://www.dsignt.de/support/ or mailto:support@disgnt.de
Code Composer Studio:

http://processors.wiki.ti.com/index.php/Category:CCS
Keystone processors:
http://processors.wiki.ti.com/index.php/Keystone_Device_Architec-
ture
Emulation:
http://processors.wiki.ti.com/index.php/Category:Emulation
© D.SignT 2013 Doc.Rev. 1.12 71

D.Module.C6657 User Guide Getting Support
Document History:
1.0 first release 2013-05-03
1.1 added NAND Flash 2013-05-16
© D.SignT 2013 Doc.Rev. 1.12 72

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D.Module2.

Document Rev. 1.12

phone: +49 2833 / 570977

© D.SignT 2013 Doc.Rev. 1.12 1

© D.SignT 2013 Doc.Rev. 1.12 2

© D.SignT 2013 Doc.Rev. 1.12 3

© D.SignT 2013 Doc.Rev. 1.12 4

• dual-core architecture, 2 x 1.25 GHz clock

© D.SignT 2013 Doc.Rev. 1.12 5

2.1 System Architecture

© D.SignT 2013 Doc.Rev. 1.12 6

The on-board peripherals are configurable via the Board Logic, a

© D.SignT 2013 Doc.Rev. 1.12 7

BUS2 Flash EXP

D[31:16] BUS AVR System FAN

Level Shifter McBSP0

Figure 2.1: D.Module2.C6657 Block Diagram

© D.SignT 2013 Doc.Rev. 1.12 8

2.2 Hardware Installation

Always use ESD precautions when handling the

Figure 2.2: D.Module2 Base Board

Connect the 3.3V power supply unit to an AC outlet (100-240 VAC)

© D.SignT 2013 Doc.Rev. 1.12 9

© D.SignT 2013 Doc.Rev. 1.12 10

Additional specialized software packages are available from Texas

© D.SignT 2013 Doc.Rev. 1.12 11

3.1 Software Installation

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3.2 Creating a new CCS project

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3.3 Building a boot-loadable Intel-Hex File

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3.3.1 Dual Core Boot

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4.1 Memory Map

Table 4.1: Memory Map

4.2 C6657 on-chip memories

© D.SignT 2013 Doc.Rev. 1.12 16

4.2.1 L1D and L1P

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4.4 External Memory-Mapped Devices

4.5 SPI NOR Flash

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4.6 NAND Flash

© D.SignT 2013 Doc.Rev. 1.12 19

for (i=0; i<16; i++) buffer[i] = 0xFF;

If the NAND is excessively used, i.e. erased and programmed fre-

4.7 Cache Coherence

© D.SignT 2013 Doc.Rev. 1.12 20

5 Board Logic and Configuration Registers

© D.SignT 2013 Doc.Rev. 1.12 21

Address Register Usage

Table 5.1: Board Configuration Registers

© D.SignT 2013 Doc.Rev. 1.12 22

Table 5.2: UARTCTRL Register

Table 5.3: BUSCTRL Register

© D.SignT 2013 Doc.Rev. 1.12 23

1: reset 0 1: GPIO 0 1: local 1: local 00: core 0

Table 5.4: DSPCTRL Register

© D.SignT 2013 Doc.Rev. 1.12 24

Table 5.5: SETUPSTAT Register

Reset Value: 0x01

Table 5.6: FLASHCTRL Register