2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) November 9-12, 2015
Architecture and FPGA Implementation of LTE
PSS and SSS Synchronizer
Jason Kurniawan∗ , Nur Ahmadi† , Trio Adiono‡
Department of Electrical Engineering, School of Electrical Engineering and Informatics
Bandung Institute of Technology, Jl. Ganesha No. 10 Bandung, 40132, Indonesia
Email: ∗ jasonkurniawan93@gmail.com, † nurahmadi@stei.itb.ac.id, ‡ tadiono@stei.itb.ac.id
Abstract—This paper presents an architecture of the LTE
signal receiver system to acquire the physical cell identity (PCI).
The PCI plays an important role to determine other reference
signals, which are further used in channel estimation, cell
selection/reselection, and handover procedures. The information
required to determine the PCI is carried by two LTE syn-
chronization signals: Primary Synchronization Signal (PSS) and
Secondary Synchronization Signal (SSS). This paper describes an
architecture of PSS and SSS Synchronizer Blocks for LTE-FDD
4G Baseband Receiver System. The synthesis results using Altera
Quartus software show that the proposed design of each block
consumes 5895 logic gates with the maximum frequency of 114.97
MHz for PSS Synchronizer block and 1332 logic gates with the
maximum frequency of 375.09 MHz for SSS Synchronizer block.
Both designs have been successfully implemented and verified on
Altera DE4 FPGA board.
Index Terms—Physical Cell Identity LTE, Synchronization
Signals, PSS, SSS, FPGA
I. I NTRODUCTION
Nowadays, communication between humans become more
essential in daily life. The development of industrial technol-
ogy in general could not be separated with the need of com-
munication. The close relation between industrial technology
and communication technology had given some contributions
to trigger and accelerate some new ideas for faster and
reliable communication technology. One of the most popular
communication technologies is Long Term Evolution (LTE),
which is a highly flexible radio interface developed by 3GPP
(3rd Generation Partnership Project) [1].
In the LTE system, synchronization signals play an im-
portant role to acquire the physical cell identity (PCI) or
NCellID which can be further used in channel estimation, cell
selection/reselection, and handover procedures. There are two
sinchronization signals which are Primary Synchronization
Signal (PSS) and Secondary Synchronization Signal (SSS).
These two signals for the case of LTE-FDD (channel band-
width 10 MHz, FFT Size 1024, and sampling frequency 15.36
MHz) will be our main interest in this paper as can be seen
in Figure 1 (blue-colored box). The input signals for the PSS
& SSS Synchronizer blocks are assumed to be already in the
frequency domain (baseband signal). The main objective in
this paper is acquire the information of physical cell identity
(PCI) whose value will be updated on each symbol processed.
For the transmitter, there is already a standarized method
by 3GPP to generate the synchronization signals for each
978-1-4673-6499-7/15/$31.00 ©2015 IEEE
235
Timing CP
RF A/D RF
Synchronizer Remover
Data PSS & SSS Equalizer &
Out
Demodulator
Synchronizer Channel Coding
Fig. 1. LTE 4G baseband receiver system
specific PCI number by using certain mathematical equations.
However, for the receiver, it will only receive the sets of
numbers without knowing whether those are PSS, SSS, other
reference signals, or data. The method or algorithm used to
determine the PCI value of one data stream input can be
various depending on the designer of the receiver. Basically,
the idea is the same, which is the reverse of the SSS generation
method. However, how the circuit design is made will be
unique one with another.
In this paper, we propose architectures for PSS and SSS
Synchronizer which are implemented in Verilog HDL. The ref-
erence model is written in MATLAB for verification purpose.
The functional simulation and the synthesis are performed by
using Modelsim tool and Altera Quartus software, respectively.
The performance of our proposed designs is evaluated based
on two metrics, which are the area consumption (resource
utilization) and the maximum frequency.
II. L ITERATURE R EVIEW
A. Synchronization Signals in LTE System
The information of physical cell identity (PCI) is carried by
syncronization signals which are PSS and SSS. PSS carries the
information about NCellID 2 (physical layer ID) while SSS
carries the information about NCellID 1 (cell group ID). There
are 3 variations of NCellID 2 value, which are [0, 1, 2], while
NCellID 1 has 168 variations which are [0 · · · 167]. Therefore,
there are 504 variations of value of PCI (3∗168 = 504). From
the value of NCellID 1 and NCellID 2, the value of PCI can
be determined as follows
P CI = (3 ∗ N CellID1 ) + N CellID2 (1)
According to LTE standards [2], in the Frequency Domain
Duplex (FDD), PSS is located at the seventh symbol of each
half-frame and the SSS is located at the sixth symbol. Their
positions on the frame structure is illustrated in Figure 2.
 the sequence s0 (m0 )(n) and s1 (m1 )(n) are derived from an
m-sequence with two different cyclic shifts as follows.
(m )
s0 0 (n) = s̃ ((n + m0 ) mod 31)
(m ) (5)
s1 1 (n) = s̃ ((n + m1 ) mod 31)
Besides (5), both (3) and (4) also require some other
parameters: c0 (n) and c1 (n). These two equations depend on
the value of PSS Number (NCellID 2 or physical layer ID).
Fig. 2. The location of PSS and SSS in LTE FDD Frame  
(2)
c0 (n) = c̃ (n + NID ) mod 31
  (6)
(2)
c1 (n) = c̃ (n + NID + 3) mod 31
B. Primary Synchronization Signal (PSS) Generation
For the odd index SSS components as in (4), the gen-
PSS values is derived from Zadoff-Chu sequence in the
eration requires other parameters which are z1 (m0 )(n) and
frequency domain, which is a CAZAC (Constant Amplitude
z1 (m1 )(n). Both of the parameters are also derived from an
Zero Auto Correlation) sequence. This Zadoff-Chu sequence
m-sequence with two different cyclic shifts as follows
is used since it has good correlation result as explained long
ago in [3]. Three root index values are defined for PSS, which (m )
z0 0 (n) = z̃ ((n + (m0 mod 8)) mod 31)
are 25, 29, and 34, each of which corresponds to the sector (m ) (7)
z1 1 (n) = z̃ ((n + (m1 mod 8)) mod 31)
ID 0, 1, and 2 [4]. The mathematical equation to obtain the
values of PSS is defined as III. P ROPOSED S YSTEM D ESIGN
⎧ A. Architecture Design Methodology
⎪ πun(n + 1)
⎪
⎨ −j
e 63 n = 0, 1, · · · , 30 To acquire the information of NCellID or PCI, previous
du (n) = (2)
⎪
⎪ πu(n + 1)(n + 2) studies have given several point of views, as described in [6]–
⎩ −j
e 63 n = 31, 32, · · · , 61 [8]. We decide that each PSS and SSS has their own desired
output which is different and tend to be independent one
Where the value u is the root index that differs the PSS as another. The desired output from PSS is NCellID 2 (physical
shown in Table I. layer ID). On the other hand, the desired output from SSS
TABLE I is NCellID 1 (cell group ID). After these two have been
R ELATION B ETWEEN NC ELL ID 2 AND ROOT I NDEX IN PSS G ENERATION acquired, the final calculation can be performed to find PCI
by using (1). Hence, each PSS processing and each SSS
(2)
NID Root Index u processing can be distinguished into two consecutive stages
0 25 or blocks called as “PSS Synchronizer Block” and “SSS
1 29 Synchronizer Block”. As shown in Figure 2, the SSS is located
2 34 at the sixth symbol and PSS at the seventh symbol. Since
the data channel is serial, the sixth symbol (containing the
information about SSS) will arrive first at the receiver and then
The Equation (2) will make 3 sets of PSS value, respectively followed by the PSS symbol. However, the SSS Synchronizer
PSS0, PSS1, and PSS2, each of which has 62 values. Every Block needs the parameter NCellID 2 to operate, which means
set of PSS values corresponds to the NCellID 2 number or PSS Synchronizer Block needs to operate first. Since the
physical layer ID [0, 1, 2]. system is real-time and the data is always moving, all the
values in the sixth symbol (which contains SSS) need to
C. Secondary Synchronization Signal (SSS) Generation
be copied and stored. We need to wait until the parameter
In general, the formula used to generate the values of the NCellID 2 is acquired in order to get the valid value of
SSS is divided into two parts: one for even-indexed values as PCI which belongs to that specific frame. Using the stored
in (3) and another for odd-indexed values as in (4). values of the sixth symbol and the parameter NCellID 2,
 the SSS Synchronizer Block can begin to operate. After SSS
(m )
s0 0 (n)c0 (n) in subframe 0 Synchronizer Block does the work, the NCellID 1 parameter
d(2n) = (m ) (3)
s1 1 (n)c0 (n) in subframe 5 is acquired, and everything needed to find PCI are already
 obtained. Thus, the PCI value can be obtained immediately
(m ) (m )
s1 1 (n)c1 (n)z1 0 (n) in subframe 0 by using (1) as mentioned before.
d(2n + 1) = (m ) (m ) (4)
s0 0 (n)c1 (n)z1 1 (n) in subframe 5
B. Proposed Design of PSS Synchronizer Block
The value m0 and m1 in (3) and (4) are directly related Basically, PSS Synchronizer Block surely needs the data
with the value of the cell group ID or NCellID 1. The at symbol 7 in each half subframe. Determining which one is
relation between those parameters can be seen in [5]. Then, symbol number 7 is carried out by Timing Synchronizer block,

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 Data_out
Data_in
PSS Head_out
Synchronizer NCellID_2
Head_in
Is_PSS
Fig. 3. PSS Synchronizer top-level block diagram
PSS Correlator 0
PSS PSS PSS
PSS Correlator 1
Input Maxfinder Comparator Controller
PSS Correlator 2
Fig. 4. PSS synchronizer submodules flow
as discussed in [9]. This block gives output of NCellID 2 or
physical later ID which is then delivered to SSS Synchronizer
block. The top-level diagram of the proposed PSS Synchro-
nizer block is depicted in Figure 3.
In Figure 3, Data in represents data stream input from FFT
module (see Figure 1), frequency domain, which is a complex
numbers that each consists of in-phase component and quadra-
ture component. Head in indicates input flag control signal
used to mark the beginning of every symbol data in Data in.
Data out refers to data stream output (Complex numbers in
frequency domain) that will be delivered to next module,
which is SSS Synchronizer Block. Head out is an output flag
control signal, used to mark the beginning of every symbol
data in Data out. NCellID 2 denotes the physical layer ID
output value of half of the subframe data that will be delivered
to SSS Synchronizer block. Is PSS indicates an output flag
control signal, used to mark whether the value NCellID 2 is
valid or not.
We propose our design for the PSS Synchronizer block as
can be seen in Figure 4, which consists of several submodules
as follows:
1) PSS Input
PSS Input block is used to retrieve the data which
contains PSS information from the input data set, also
to take the values PSS 0, PSS 1, and PSS 2 from
ROM and simultaneously prepare them to enter the PSS
Correlator.
2) PSS Correlator
PSS Correlator block performs correlation operation
between the data input and each of the PSS reference
values. This block is designed only to correlate two in-
puts, while the system requires three correlation process
being executed at the same time (respectively the input
with each of PSS0, PSS1, and PSS2). Therefore, for
the implementation, there will be 3 identical parallel
correlator blocks working at the same time.
3) PSS Maxfinder
After the correlators, the PSS Maxfinder block is used
to find the biggest value from each of the sets of the
correlation results. There will be three output values
which come from each correlator.
4) PSS Comparator
The three maximum correlation value from each corre-
Data_out
Data_In
Head_out
Head_in SSS
NCellID_2_in NCellID_1_out
Synchronizer
NCellID_2_out
Is_PSS_in Is_PSS_out
Fig. 5. SSS Synchronizer top-level block diagram
PSS
Pre SSS SSS s0(m0) SSS s1(m1) SSS Num
Fig. 6. SSS synchronizer submodules flow
lator that has been obtained from PSS Maxfinder block
then will be processed in this PSS Comparator block to
find the largest of the three. The largest value indicates
that the identity of the PSS input signal matches the
PSS values, which correponds either with PSS0, PSS1,
or PSS2.
5) PSS Controller
When all the computation sequences are finished, then
this block will finalize everything and make the output
ready to be acquired, along with the is PSS flag.
The more detail block diagram of PSS synchronizer is
described in Figure 7a.
C. Proposed Design of SSS Synchronizer Block
From PSS Synchronizer block, the value of NCellID 2 or
physical cell ID is already obtained. This value then will be
used as an input required in determining the value NCellID 1
or cell group ID, for later finding our main goal, the PCI
value. The Top-level block diagram of the proposed SSS
Synchronizer Block shown in Figure 5.
In Figure 5, Data in represents data stream input from PSS
Synchronizer module in frequency domain (complex num-
bers). Head in indicates input flag control signal used to mark
the beginning of every symbol data in Data in. NCellID 2 in
acts as input physical later ID value from PSS Synchronizer
block which is needed in some calculations to obtain the
NCellID 1 value. Is PSS in is the input flag signal to mark
whether the value NCellID 2 in is valid or not. Data out
refers to data stream output that will be delivered to next
module in the receiver part after SSS Synchronizer. Head out
serves as output flag control signal used to mark the beginning
of every symbol data in Data out. NCellID 1 out is the
cell group ID output value obtained from SSS Synchronizer
process. NCellID 2 out is the value of NCellID 2 in will be
given again as the final output together with NCellID 1 out
with some timing calculations in order to make it easier in
obtaining the PCI value. Is PSS out denotes the same flag
signal as is PSS in, but this one is used to mark whether the
value NCellID 2 out is valid, adapted with the correct timing
calculations.
Our proposed design of the SSS Synchronizer block as
illustrated in Figure 6 consists of several submodules as
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 Data_in PSS Input PSS_Data_Out = CORRELATION

PSS_0

mux
Accu Compa
ROM Mag_ reg
Corr0 Head_out
Mag0
PSS_1 PSS PSS_

mux
Compa Mag1
Accu reg Comparator NCellID_2
ROM Mag_ Controller
Corr1 Mag2
is_PSS
PSS_2

mux
Accu Compa
ROM Mag_ reg
Corr2 Data_out

Head_in Counter selector

Data Register
(buffer)

(a) PSS synchronizer block diagram

s0(m0)
SSS_Data_Even MATH
PROCES
ING
s0(m0)_corr_result
s0(m0)
C0 trigger C0 coef ROM C0 data SSS_m0_acq
Sref_Data Correlator
s0(m0)
Sref trigger Sref ROM m0 NCellID_1_out
Controller
Data_in m0 SSS NCellID_2_out
NCellID_2_in Z1 Coef ROM Z1 data Num
NCellID_2_in Data_out
s1(m1)
Head_in Pre SSS s1(m1) MATH
C1 trigger C1 Coef ROM C1 data Head_out
Is_PSS_in Controller PROCESS
ING m1
s1(m1) Is_PSS_out
s1(m1)_corr_result
SSS_Data_Odd Correlator
SSS_m1_acq
Sref trigger Sref ROM Sref_Data

NCellID_2_out
Data_out
Head_out
Is_PSS_out

(b) SSS synchronizer block diagram

Fig. 7. PSS and SSS synchronizer block diagram

follows: been acquired before and finalize it for the system’s

1) SSS Input
SSS Input block is the beginning of the SSS Synchro-
nizer block. This block is used to retrieve the data
that contains SSS information from the input data set,
separate the data by turns according to the odd index
and even index, then give the data sets into next blocks,
which are SSS s0(m0) block and SSS s1(m1) block each.
2) SSS s0(m0)
The block will process the even-indexed SSS data along
with the PSS Num (NCellID 2) information, by using
some reverse-engineering algorithm from the SSS Gen-
eration equations to extract the value m0 from the input
signal.
3) SSS s1(m1)
Almost similiar with SSS s0(m0) block, this
SSS s1(m1) will use the reverse-engineering algorithm
that will process the odd-indexed SSS data along with
the PSS Num (NCellID 2) information to extract the
value m1 from the input signal.
4) SSS Num
This last block will calculate the final value of cell group
ID (NCellID 1) using the inputs m0 and m1 that had
output.
The more detail block diagram of SSS synchronizer is
described in Figure 7b.
IV. V ERIFICATION AND P ERFORMANCE E VALUATION
A. PSS Synchronizer Verification
The result of PSS Synchronizer block verification using
Altera ModelSim software can be seen in Figure 8a. The
input for this simulation has a PSS value = 1. In the input
data, the beginning of a data symbol is marked with flag
head in. Whenever this head in flag is detected, the system
will take the symbol then find the data which contains PSS
information, without knowing whether the symbol contains
the synchronization signals or not. After all symbols are
correlated, then the system will look for the largest value of the
correlation results that shows the PSS, still not sure whether
the value is valid or not. Thus, at the end of the symbol,
the block can issue is PSS which is a flag that indicates the
symbol containing PSS. This is PSS flag is very important
because it determines the following controller to take the data
in the SSS data buffer which is located in front of the PSS
Synchronizer block. SSS data will always come before PSS

238
 (a) PSS synchronizer simulation

(b) SSS synchronizer simulation

Fig. 8. Functional simulation of PSS and SSS synchronizer block

data, but to do SSS processing, the PSS value will have to be also a flag head out which marks the beginning of the data
determined first. Therefore, the timing handling for this case symbol. Thus, in the end, output PSS Num (NCellID 2) and
have to be carefully performed. SSS Num (NCellID 1), which are the main target of the
PSS value can be acquired after the system process 70 system, has been obtain succesfully. This indicates the system
symbols, and that one value shows the PSS identity value has been completed and functioning properly.
for 70 symbols of data. Flag is PSS is generated on the
C. Performance Evaluation
symbol containing information PSS with timing set to match
the dataflow in the buffer, as shown in the graphical simulation Implementation process is carried out by using FPGA
result. However, to shorten the time, the simulation is done Altera DE4 Development Board. The processing time is tested
only for the first 10 symbols of input data only. But, the output for every submodules both in PSS Synchronizer block and
will not be affected because the PSS information is located in SSS Synchronizer block as shown in Table II and Table III,
the 7th symbol of 70 data symbols. By cutting the number of respectively. The maximum clock frequency of each block is
inputs, we could see the PSS value = 1 out after 10 symbols obtained by using TimeQuest Timing Analyzer embedded in
entered the system, and is PSS valued HIGH 6 symbols period Altera Quartus II software.
after PSS Num come out. TABLE II
PSS SYNCHRONIZER BLOCK PROCESSING TIME
B. SSS Synchronizer Verification
Processing Time Delay*
The result of SSS Synchronizer block verification using Submodules
(Clock Cycles) (μS)
Altera ModelSim software could be seen in Figure 8b. When
PSS Input 271 17.64
the flag is PSS is detected by SSS Controller block, then
PSS Correlator 11 0.716
the controller will give command to retrieve the data located
PSS Maxfinder 102 6.64
exactly one symbol in front of the symbol where PSS is
PSS Comparator 2 0.13
located. Those data contains the information about SSS. In
PSS Contoller 31 2.018
this simulation, PSS Num, in which the input equals to 0,
Total 417 27.148
and after the input enters this block, system will process the *
SSS data to obtain the SSS Num value which shows the Delay = Processing Time/Fmax, Fmax = 114.97
MHz
information NCellID 1 of the signal. This SSS Num value
is then taken out of the system along with the data set and

239
 TABLE III
SSS SYNCHRONIZER BLOCK PROCESSING TIME [5] 3GPP LTE Design Library (ADS 2008), Agilent Technologies, 2008.
[Online]. Available: http://cp.literature.agilent.com/litweb/pdf/ads2008/
pdf/3gpplte.pdf
Processing Time Delay* [6] V. Paliwal and I. Lambadaris, “Cell search procedures in lte systems.”
Submodules
(Clock Cycles) (μS) [7] A. N. Gaber, L. D. Khalaf, A. M. Mustafa, and J. YEMEN, “Synchro-
Pre PSS 660 42.969 nization and cell search algorithms in 3gpp long term evolution systems
(fdd mode),” WSEAS Transactions on Communications, vol. 11, no. 2,
SSS s0(m0) 120 7.813 pp. 70–81, 2012.
SSS s1(m1) 137 8.919 [8] S. Srikanth, M. Pandian, and X. Fernando, “Orthogonal frequency
SSS Num 2 0.13 division multiple access in wimax and lte: a comparison,” IEEE Com-
munications Magazine, vol. 50, no. 9, pp. 153–161, 2012.
Total 919 59.831 [9] F. Soewito, “FPGA based timing synchronizer for LTE 4G receiver,”
* Bachelor’s Thesis, Bandung Institute of Technology, 2015.
Delay = Processing Time/Fmax, Fmax =
375.09 MHz [10] T. Innovations, “LTE in a nutshell: The physical layer,” White Paper,
2010.

Both of our proposed PSS and SSS synchronizer designs

have met the requirements of the operating frequency for
LTE Systems. For PSS Synchronizer, the maximum clock
frequency allowed for the block to operate is 114.97 MHz,
while for SSS Synchronizer is 375.09 MHz. These frequencies
are far beyond the LTE FDD with 10 MHz channel bandwidth
working frequency which is 15.36 MHz [10]. In addtion, the
number of the logic elements required to implement the system
is 5895 logic elements for PSS Synchronizer and 1332 logic
elements for SSS Synchronizer.

V. C ONCLUSION
The proposed design of the PSS and SSS Synchronizer
system for LTE 4G Baseband Receiver have been verified,
tested, and implemented successfully on FPGA Altera DE4
Development Board. The implementation of the system re-
quires 5895 and 1332 logic elements, each for PSS Syn-
chronizer block and SSS Synchronizer block, respectively.
The delay and the maximum clock frequency allowed for the
PSS Synchronizer block to operate are each 27.148 us and
114.97 MHz. The delay and the maximum clock frequency for
the SSS Synchronizer block are 59.831 us and 375.09 MHz.
Both the delays are relatively small and the maximum clock
frequencies exceed the 15.36 MHz LTE FDD 10 MHz working
frequency, which indicates that the block should work well for
LTE system.
Further, this system design could also be used for other LTE-
FDD signals with different channel bandwidths with some
necessary modifications. Some other optimizations inside the
system need to be performed to deliver better performance in
terms of speed and area consumption.

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