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5 4 3 2 1

D D

EMI Power
VIO_EMI

U201-A

1uF/6.3V/X5R 1uF/6.3V/X5R
W9 DVDD18_FSRC C101
0402 0402

C105 C106 C114


VCCIO W11 VIO_EMI 0402 0402

VCCIO W16 0.1uF/16V/X7R


C102 VIO18_PMU V9 W18 0.1uF/16V/X7R
DVDD18_PLLGP VCCIO

0402
0.1uF/16V/X7R Y9
VCCIO
VCCIO Y12
VIO18_PMU K2 AVDD18_AP VCCIO Y15
VCCIO Y18
C C
VCCIO Y19
C2215

Power In
VTCXO_PMU K1 AVDD28_DAC VCCIO AA9
0402
0.1uF/16V/X7R

C103 VIO18_PMU J2 AVDD18_MD


0402

0.1uF/16V/X7R VPROC_PMU
Close to BB
C109 REFP F12 REFP
0402

1uF/6.3V/X5R VCCK_CPU M8 VPROC_PMU


VCCK_CPU N8
GND_SIGNAL F13 REFN VCCK_CPU P5

Vcore Power
VCCK_CPU P6
VCCK_CPU P7
GND_SIGNAL D24 AVSS33_USB VCCK_CPU P8
VCCK_CPU R5
VCCK_CPU R6
C113 G26 R7

1uF/6.3V/X5R C119

C125
VUSB_PMU

C137
AVDD33_USB VCCK_CPU
0402

C127
1uF/6.3V/X5R R8

C112
0.1uF/16V/X7R C111

0.1uF/16V/X7R C110

0.1uF/16V/X7R C107

1uF/6.3V/X5R C124
F13 should connect to C109.2 first, VCCK_CPU
VCCK_CPU T8 0402 0402 0402

than connect to GND by via. C115 F26 T9

1uF/6.3V/X5R
VIO18_PMU

2.2uF/6.3V/X5R
AVDD18_USB VCCK_CPU
0402 0402 0402 0402 0402 0402
0402

0.1uF/16V/X7R

0.1uF/16V/X7R

1uF/6.3V/X5R
[1,2,3,5,9] R105 C108 P26
VIO18_PMU DVDD18_MIPI
0402

0402

0R U101 0.1uF/16V/X7R
MIC5219-3.3BM5 [3,4,6,8,12]
[3] R106 VBAT N24 DVSS18_MIPI
EXT_PMIC_EN 0402 /SHDN VIN
0R
R23 DVSS18_MIPI
GND
Close to BB R26
BP VOUT DVSS18_MIPI
R109 51K

R103
C134 U26 K9

IO Power
IC_LDO_BL8568CB5ATR33 0402 DVSS18_MIPI VCCK VPROC_PMU
0402
C133 K10
0402

22nF C132 0R VCCK


R108 33K 0402

K14
2.2uF VCCK
0402

0402
2.2uF R104
C128 22pF VIO18_PMU 0402 H25 DVDD18_CM VCCK K15
K16
0402

0R VCCK

MT8312D_ABB
VCCK K17
VIO18_PMU G9 DVDD18_BPI VCCK L8

C136
VCCK L17
R107 0R M17 4.7uF/6.3V/X5R
[8] LCD_VDD VCCK
B
0402 C2216 VIO28_PMU B13 R17 0603 0603 0603 0603
B
DVDD28_BPI VCCK
0402
0402

C135C116C123
C138

2.2uF/6.3V/X5R
0.1uF/16V/X7R VCCK T17
VCCK U10
C104 150mil VIO18_PMU W1 U11 default NC 0603
DVDDIO_MC0 VCCK
0402

0.1uF/16V/X7R U12 C126


VCCK
VCCK U13
C131 150mil VMC_PMU G25 U14
DVDDIO_MC1 VCCK
0402

1uF/6.3V/X5R U15
VCCK
VCCK U16
C118 VIO18_PMU T1 DVDD18_VIO
0402

0.1uF/16V/X7R

Reserve for eMMC VIO18_PMU A23 DVDD18_VIO2


Close to BB
V8 DVDDIO_NF
reserve for de-sense
100nF C121
Y26 DVDD18_LP
0402

Close to BB
SIM1_SCLK M3 SIM1_SCLK
R101
SIM1_SIO R4 N4 VPROC_FB
SIM

SIM1_SIO RS_VDD 0402


0R
R102 4mil - defferential - GND shielding
SIM2_SCLK K3 SIM2_SCLK RS_VSS P4 0402 GND_VPROC_FB
0R
SIM2_SIO T4 SIM2_SIO
Based on your system level design , if better
desense performance is needed on your
32K

system. CLK32K_BB M2 CLK32K_IN Vproc remote sense :


differential 4mil with good shielding, from the BB to PMIC

NC_AE26

NC_AF25
NC_AF26
NC_A25
NC_A26

NC_B26
NC_AE1

NC_AF1
NC_AF2
NC_A1
NC_A2

NC_B1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MT8312D
C23
K11
K12
K13
K21
K26
L4
L11
L12
L13
L14
M9
M10
M13
M15
M16
N9
N10
N11
N12
N13
N14
N15
N16
N17
P9
P11
P13
P15
P16
R9
R10
R11
R12
R13
R14
R15
R16
T11
T13
T15
U1
U17
V5
W13
W14
Y24
AA5
AA11
AA20
AA23
AB2
AC7
AC16
AC19
AD1
AD12
AD14
AD26
AE9
AE20
AE22
AE24
AF3
AF5

A1
A2
A25
A26
B1
B26
AE1
AE26
AF1
AF2
AF25
AF26
A A

Title
Power
Size Document Number Rev
D MT8312D TABLET V1.0

Date: Tuesday, April 22, 2014 Sheet 1 of 13

5 4 3 2 1
5 4 3 2 1

VIO18_PMU
R201 0
0402

R202 0
0402 [9] EINT_ACC
[9] EINT_MAG

SCL1 [2,9,12]
SDA1 [2,9,12]

R220 0 Close to BB KROW0 [12]


GPIO_FLASH_EN [12]
Reserved for DRAM co-layout config detection.
0402

0.1UF C223 C224 C225 C226 GPIO_FLASH_SEL [12]


When x16 bit x2 pcs: AUX_XM==0
0402 0402 0402 0402 0402

C222

100pF

100pF
100pF

100pF
[4,12] USB_DP KCOL0 [12]
When x16 bit x1 pcs: AUX_XM==1

eMMC/MLC NAND
[4,12] USB_DM KCOL1 [12]
90-ohm differential
GPIO_CTP_PWREN [12]
[4] GPIO_USB_DRVVBUS
[4] EINT5_EAR
D [3] CHD_DP
D
[3] CHD_DM
Symbol eMMC NAND Default
Please reserve 100pF bypass
NFI11 H (1K) L (No Pull) PD

D25

D26

H19

H18

G20
C13

B12

C25
C24
A24
E25

F20

F21
L19

L18
cap near BB when using these

K7

K8
K5
K6
L7
U201-C
pins for decouple RF noise.

PWM_A
CHG_DP

USB_DP
CHG_DM

PWM_B

AUX_YP
AUX_XP
USB_DM

USB_VRT

AUX_IN0
AUX_YM

AUX_XM

SCL_1

SDA_1

KROW0
KROW1
KROW2

KCOL0
KCOL1
KCOL2
VIO18_PMU

EA0 [5] AB12 EA0 NFI0 W2 PWM [8]


EA1 [5] AD17 EA1 NFI1 W8 DPI_R1 [8]
EA2 [5] AF12 EA2 NFI2 V1 DPI_R0 [8]
EA3 [5] AD11 EA3 NFI3 V3 DPI_G1 [8]
EA4 [5]
EA5 [5]
AF16
AA12
EA4
EA5
BC 1.1 PWM USB ADC I2C Double Key NFI4
NFI5
V2
V4
DPI_G0 [8]
DPI_B1 [8]
EA6 [5] AE16 EA6 NFI6 V6 DPI_B0 [8] R211

0402
EA7 [5] AF14 EA7 NFI7 W3 VLCD_AVDD_EN [8] 1K
EA8 [5] AE15 EA8 NFI8 W4 LCD_3.3V_EN [8]
EA9 [5] AE12 EA9 NFI9 V7 VBAT_EN [8]
EA10 [5] AF13 EA10 NFI10 W7 GPIO38_M_SENSOR_REST[9]
EA11 [5] AD16 EA11 NFI11 Y2 NFI11
EA12 [5] AE18 EA12
EA13 [5] AE14 EA13
EA14 [5] AE17 EA14 MC0_RSTB AA2 MC0_RSTB [5]
EA15 [5] AF18 EA15 MC0_DAT7 AA3 MC0_DAT7 [5]
MC0_DAT6 AB1 MC0_DAT6 [5]
MC0_DAT5 AC2 MC0_DAT5 [5]
ED0 [5] AD4 ED0 MC0_DAT4 AC1 MC0_DAT4 [5]
ED1 [5] AF7 ED1 MC0_DAT3 W6 MC0_DAT3 [5]
ED2 [5] AE4 ED2 MC0_DAT2 AA4 MC0_DAT2 [5]
ED3 [5] AE6 ED3 MC0_DAT1 W5 MC0_DAT1 [5]
ED4 [5] AE5 ED4 MC0_DAT0 Y3 MC0_DAT0 [5]
ED5 [5] AF6 ED5 MC0_CK AB3 MC0_CK [5]
ED6 [5] AD5 ED6 MC0_CMD AC3 MC0_CMD [5]
ED7 [5] AD6 ED7
ED8 [5] AF9 ED8
ED9 [5] AD3 ED9
ED10 [5] AD10 ED10
ED11 [5] AE2 ED11 LPCEB AB23 EINT9_CTP [12]
ED12 [5] AE7 ED12 LPTE W20 DPI_CK [8]
ED13 [5] AD2 ED13 LRSTB AB24 LRSTB [8]
ED14 [5] AE8 ED14 LPRDB V23 DPI_HSYNC [8]
C C
ED15 [5] AE3 ED15 LPA0 Y25 DPI_DE [8]
ED16 AD21 ED16 LPWRB AA24 DPI_VSYNC [8]
ED17 AF24 ED17
ED18 AE21 ED18

LCD
ED19 AD23 ED19 LPD9 AA25 DPI_G5 [8]

EMI - PCDDR3(16x2)
ED20 AF22 ED20 LPD8 V24 DPI_G4 [8]
ED21 AE23 ED21 LPD7 AC25 DPI_G3 [8]
ED22 AC22 ED22 LPD6 AC26 DPI_G2 [8]
ED23 AD22 ED23 LPD5 Y23 DPI_B7 [8]
ED24 AC24 ED24 LPD4 V19 DPI_B6 [8]
ED25 AF19 ED25 LPD3 V18 DPI_B5 [8]
ED26 AD25 ED26 LPD2 W23 DPI_B4 [8]
ED27 AE19 ED27 LPD1 V20 [8]

MT8312D_BB
DPI_B3
ED28 AD24 ED28 LPD0 V22 DPI_B2 [8]
ED29 AD20 ED29
ED30 AE25 ED30
ED31 AF20 ED31 TDN2 W25 DPI_G7 [8]
TDP2 W26 DPI_G6 [8]
TDN0 R24 DPI_R3 [8]
ERESET [5] AB15 ERESET TDP0 R25 DPI_R2 [8]
TDN1 U25 DPI_R5 [8]
TDP1 T25 DPI_R4 [8]
EBA0 [5] AF10 BA0 TCN V25 DPI_R7 [8]
EBA1 [5] AA15 BA1 TCP V26 [8]
DDRVREF DPI_R6
EBA2 [5] AD15 BA2 R221 0
MIPI_VRT P25 MIPI_VRT 0402
DDRVREF Y11 VREF0
VIO18_PMU
DDRVREF Y16 VREF1
Close to BB
C55 C39 L21
SCL_0 SCL0 [2,11,12]
R2243

0402 0402

NC 0.1uF/16V/X7R ECS0 [5] AE11 ECS0_B SDA_0 L20 SDA0 [2,11,12]


ECS1 [5] AC15 ECS1_B
CMPCLK K20 [11,12]
CMPCLK
K22 CMMCLK
0402

CMMCLK CMMCLK [12]


EDQM0 [5] AD8 EDQM0
AC6 R22
EDQM1 [5] EDQM1 RDN0 C227
reserve for de-sense
0

EDQM2 AB22 EDQM2 RDP0 R21 0402

SIM1_SCLK AD19 P20 100nF

Camera
1,3 SIM1_SCLK [1,3] EDQM3 EDQM3 RDN1
RDP1 P19
EDQS0 [5] AA7 EDQS0 RCN R19
Reserve R footprint for JTAG EDQS1 [5] AC8 EDQS1 RCP R20
AB18
B
debugging EDQS2
AC20
EDQS2
J26
B
EDQS3 EDQS3 CMRST GPIO_CMRST [12]
HW trapping PIN for JTAG debug from KP(serial) CMPDN J25 GPIO_CMPDN [12] Based on your system level
AA6
(please refer to HW design notice) EDQS0_B [5]
EDQS1_B [5] AB8
EDQS0_B
EDQS1_B design , if better desense
EDQS2_B AA18 EDQS2_B CMDAT0 L26 CMDAT0 [11,12]
EDQS3_B AB20 M25 performance is needed on
EDQS3_B CMDAT1 CMDAT1 [11,12]
CMDAT2 L25 CMDAT2 [11,12] your system.
CMDAT3 L23 CMDAT3 [11,12]
ERWE [5] AC12 EWR_B CMDAT4 M26 CMDAT4 [11,12]
ERAS [5] AF11 ERAS_B CMDAT5 L24 CMDAT5 [11,12]
ECAS [5] AE10 ECAS_B
ECKE [5] AE13 ECKE RDN0_A N26 CMHSYNC [11,12]
Power by CTP, Sensor, Charger IC RDP0_A N25 CMVSYNC [11,12]
VIO18_PMU RDN1_A P23 CMDAT6 [11,12]
RDP1_A P24 CMDAT7 [11,12]
ECLK0 [5] AC11 EDCLK0 RCN_A P21
ECLK0_B [5] AB11 EDCLK0_B UART SPI MSDC SYS Ctrl RCP_A P22

CMRST2 K25 GPIO_CMRST2 [12]


R223 R224
0402

0402

AA16 L22
AUD_DAT_MOSI

ECLK1
AUD_DAT_MISO

PMIC_SPI_MOSI

PMIC_SPI_MISO
2.2K EDCLK1 CMPDN2 GPIO_CMPDN2 [12]
AUD_CLK_MOSI

2.2K

PMIC_SPI_CSN

PMIC_SPI_SCK
ECLK1_B AB16 EDCLK1_B

WATCHDOG

TESTMODE
MC1_DAT0
MC1_DAT1
MC1_DAT2
MC1_DAT3

SRCLKENA
MC1_CMD
SPI_MOSI
SPI_MISO

[2,9,12] SDA1

SYSRSTB
SPI_SCK

MC1_CK
SPI_CS
URXD1

URXD2
UTXD1

UTXD2

[2,9,12] SCL1

EINTX
MT8312D
C26
B23

B25
B24

E21
F24
F22
F23

K23
G22
G21
G23
G24
K24

K4

T3

L5

N1

T2

P3

R3

N2

M1

N3

L3

L6
Power by CAM_IO
VCAM_IOPMU

UART1 : AP UART
HOLE1.2
R222 R215
0402

0402

WATCHDOG [3]
4.7K 4.7K
[4] ENIT_IDDIG HOLE3 FIDUCIAL FIDUCIAL
R2232 NC
0402 1 1
[2,11,12] SDA0 RESETB [3]

A [2,11,12] SCL0 HOLE1 MARK3 MARK4 A


EINT_PMIC [3]
[11] I2S_IN_DAT HOLE1.2
HOLE6 FIDUCIALMARK_1MM
FIDUCIALMARK_1MM
[11] I2S_IN_CK HOLE1.6
[11] I2S_IN_WS PMIC_SPI_CS [3,5]
FIDUCIAL FIDUCIAL
HOLE5
[9] MC1CMD PMIC_SPI_MOSI [3] HOLE1.2 HOLE7 1 1
[9] MC1CK AUD_CLK [3] HOLE1.6
[9] MC1DAT0 MARK1 MARK2
AUD_MISO [3] HOLE2
[9] MC1DAT1 AUD_MOSI [3,5] HOLE1.2 FIDUCIALMARK_1MM
FIDUCIALMARK_1MM
[9] MC1DAT2 HOLE4
[9] MC1DAT3 HOLE1.6
Title
BB
Size Document Number Rev
D MT8312D TABLET V1.0

Date: Tuesday, April 22, 2014 Sheet 2 of 13

5 4 3 2 1
5 4 3 2 1

U300

VBAT B301
L1 5 1 +
SPK_P C300
M1 5 0402 2 - SPK300
SPK_N 100pF B303
R1 VBAT_SPK
C301
L2 H4 SPEAKER
GND_SPK AU_HSP AU_HSP[4]
0402

2.2uF H3
AU_HSN AU_HSN[4] C302 C303 VR300
0402 0402
VR301
J2 33pF 33pF
AU_HPL AU_HPL[4]
D MICBIAS0 H1 AU_MICBIAS0 AU_HPR K2 AU_HPR[4] D
MICBIAS1 H2 AU_MICBIAS1

C304
Power output Trace Width trace Notes
0402

AU_VIN0_P[4] D3 AU_VIN0_P ISINK0 C10 PCB rule (mils) length/width


AUDIO DRIVER

1uF
AU_VIN0_N[4] D4 AU_VIN0_N ISINK1 C11
ISINK2 D11
AU_VIN1_P[4] G1 AU_VIN1_P ISINK3 B11 VPROC >=70
AU_VIN1_N[4] G2 AU_VIN1_N

AU_VIN2_P E2 AU_VIN2_P VSYS >=20


AU_VIN2_N E1 AU_VIN2_N
VA_PMU

C305
J1 AVDD28_ABB
0402
D2 AVDD28_AUXADC
VPA >=30 =< 370
F3 GND_ABB
K4

1uF
GND_ABB
L300 VRF18 >=15 =< 150
L_MIP25202R2MBE
ACCDET[4] G3 ACCDET BUCK OUTPUT E15
VPROC VPROC_PMU
CLK4_AUDIO
[6] CLK4_AUDIO F2 CLK26M VPROC C15 4.7uF VM >=35 =< 35
VPROC D15 0603

C307
VMCH >=12
VPROC_FB C13 VPROC_FB[1]
CHARGER D13
GND_VPROC_FB GND_VPROC_FB[1]
[1,3,4,6,8,12]
VBAT P13 BATSNS
[3] ISENSE R13 ISENSE VPA A15 VEMC_3v3 >=15 =< 100 4 mil if no use
[3] BAT_ON K3 BATON VPA B15
[3] VCDT A13 VCDT
P14 VDRV VPA_FB B13 VCN33 >=12 =< 310
[3] VDRV
L302

Charger [3]CHR_LDO CHR_LDO R14 CHRLDO L_MIP25202R2MBE


VIO18 >=12

C309

C310
VSYS H15 VSYS_SW VSYS_PMU
0402

0402
CONTROL SIGNAL 4.7uF
VGP3 >=15 =< 315

1uF
R303 1 2 1K P1
0603

NC
[12]PWRKEY 0402 PWRKEY C311
[2] WATCHDOG A1 SYSRSTB
VBUS M3
[2]RESETB RESETB
A10 FSOURCE
ALDO OUTPUT
VA M4 VA_PMU VCAMD >=15 =< 330
1. Close to Battery Connector. C7
Close to PMIC EINT_PMIC
[1] [2]
P12
INT
P2 VCN_2V8_PMU
(Rsense (R328) <10mm) EXT_PMIC_EN EXT_PMIC_EN VCN28
N3
VCAMA_PMU VA_PMU
VTCXO VTCXO_PMU VCAMA >=12 =< 310
2. Main path should be 40mil. N2 PMU_TESTMODE
VCAMA R3 VCAMA_PMU
(VBUS -> U303's E, -> U303's C -> R328 -> VBAT)

C312

C313
AUD_MOSI [2,5] B8 AUD_MOSI VCN33 N7 VCN_3V3_PMU
C9 C1 VRTC
3. Star connection from R328 to BAT Connector AUD_CLK [2]
A6
AUD_CLK AVDD33_RTC 0402 0402

R304 AUD_MISO [2] AUD_MISO

1uF

1uF
0402 VCDT [3] A2
PMIC_SRCLKENA SRCLKEN DLDO OUTPUT
330K VCDT rating: 1.268V N1 FCHR_ENB
R305 VM J15 VIO_EMI

VIBRATOR
0402
PMIC_SPI_SCK B10 SPI_CLK VRF18 K12 VRF18_PMU
C 39K VIBR_PMU C
PMIC_SPI_CS[2,5] B7 SPI_CSN VIO18 L12 VIO18_PMU PMU side
VBAT
PMIC_SPI_MOSI[2] D9 SPI_MOSI VIO28 P3 VIO28_PMU
VEMC_3V3_PMU
Vbat should connect to C341 first, PMIC_SPI_MISO B9 SPI_MISO VCN18 K14 VWCN_1V8_PMU VRTC VRTC VEMC_3V3_PMU
40mils VCAMD L15 VCAMD_PMU
then star-connetion to MT6323 E14 VBAT INPUT M13
Star-connection VBAT_VPROC VCAM_IO VCAM_IOPMU
G15 VBAT_VPROC
50mil 50mil 30mil F14 VBAT_VPROC
R308

R307

0R
0402
F15 VBAT_VPROC VEMC_3V3 R6 VEMC_3V3_PMU
0402 CHR_LDO [3] 30mil A14 M6 VMC_PMU
VBAT_VPA VMC
3.3K B14 R4 VMCH_PMU
20mil H13
VBAT_VPA
VBAT_VSYS
VMCH
VUSB N6 VUSB_PMU 15mil
R7 VBAT_LDOS3 VSIM1 R8 VSIM1_PMU

1
C314
20mil P7 VBAT_LDOS3 VSIM2 P8 VSIM2_PMU +
C333 MT300
R5 N8 VGP1_PMU 100NF 100NF
0603 0402

30mil R2
VBAT_LDOS2 VGP1 VGP1 3.3V LCM 0402 0402 0402
100NF 100NF VIBRATOR
Close to battery connector VBAT_LDOS1
0402

1uF C355 C356 C315 A


D_PZ3D4V2H
C316

2.2uF
M8 VIBR_PMU C354
2 VIBR
1

0402

VSYS_PMU K15 L8 VGP2 2.8V CTP 100nF


D300

PNP AVDD22_BUCK VGP2


3

U301 N15 M15


T_WPT2E33 Q300 AVDD22_BUCK VGP3 VGP3 1.2V MT8193 -
VCAM_AF P6 VCAM_AFPMU
1 3 2 VDRV [3]

2
1

MOS_SSM3K35MFV
SOD123 VF : 4.85V~5.36V
DVDD18_DIG A8 DVDD18_DIG
2

40mils 4mil
500mW VIO18_PMU A5 DVDD18_IO dedicate VSS ball, must return to cap then to main GND:
ISENSE [3] P15 GND_VREF(R15) => C311
VREF
Rsense

0402
AUXADC_REF C2 AUXADC
AUXADC_REF[3,6] AUXADC_VREF18 C317
0.2R 1% R316 Differential THERM_ADC [6] B1 R15
0805
1206

AUXADC_AUXIN_GPS GND_VREF 100nF


R317 0.2R B2 AVSS28_AUXADC GND_LDO K7 ==> for longer RTC time sustain after battery remove,
GND_LDO L6
4mil
VBAT [1,3,4,6,8,12]
L9 please refer to RTC design notice

C358
C318

100nF
1uF
GND_LDO
C322 must to be close
0402 0402

40mils GND_LDO L11


BC 1.1 M12
to PMIC AUXADC_TSX pin GND_LDO
CHD_DM[2] A11 CHG_DM GND_LDO N13
VA_PMU AUXADC_REF [6] [3,6]
BATTERY AUXADC_REF GND_AUXADC
CHD_DP[2] A12 CHG_DP GND_LDO
GND_LDO
K10
K11

CONNECTOR R318 SIM LVS RTC


RTC_32K1V8 D6
C5
CLK32K_BB[1]
Close to MT6323
RTC_32K2V8
0402

R310 [6] GND_AUXADC C8 A3 32K_IN


40mils NC SIM1_SCLK[1,2]

0R
SIM1_AP_SCLK XIN
0402

3.3K SIM1_SIO[1] P11 A4 32K_OUT


SIMLS1_AP_SIO XOUT
40mils SIM1_SRST D8 SIM1_AP_SRST

R325 0402
J300 80mil
PAD-2.5X4 VBAT [1,3,4,6,8,12]
SIM2_SCLK[1] B6 SIM2_AP_SCLK GND_ISINK E11

2
R319 1K

C326

C327
J301 SIM2_SIO[1] R11 SIMLS2_AP_SIO GND_VSYS J12
PAD-2.5X4 BAT_ON [3] C332C319C320 C321 C322 C323 C324 C325

X201
0402
SIM2_SRST D7 SIM2_AP_SRST GND_VPA G13

22pF

22pF
C328

C329
0402
0603 0603 0603 0603 0603 0402

F12
0402 0402 0402

C330 C331 GND_VPROC


Connect TSX/XTAL GND
0402 0402

1uF 4.7uF4.7uF 4.7uF 4.7uF 4.7uF 2.2uF 2.2uF

1uF

1uF
J302 19 SIM1_CARD_SCLK[9] N11 SIMLS1_SCLK GND_VPROC F11

4
0603 0402

PAD-2.5X4 100nF
22uF R320 to AVSS28_AUXADC first 19 SIM1_CARD_SIO[9] N12 SIMLS1_SIO GND_VPROC G11
0402

NC 19 SIM1_CARD_SRST[9] P10 SIMLS1_SRST GND_VPROC E13


VR303 VR302
than connect to main GND GND_LDO K6
M10 K8
R334,R335 must to be close to SIM2_CARD_SCLK[9]
R10
SIMLS2_SCLK GND_LDO
B3
SIM2_CARD_SIO[9] SIMLS2_SIO GND_LDO
PMIC AUXADC_REF pin SIM2_CARD_SRST[9] N10 SIMLS2_SRST GND_LDO F5 < 32K - Less>
GND_LDO F6
GND_LDO D5 1. MT6323 XOUT connect to MT6166 32KHz output
B GND_LDO E6 B
2. MT6323 XIN connect to GND

GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO F9
GND_LDO J5
GND_LDO G6
NC R321
0402 DCXO_32K
[6]

J11
J9
J8
J7
H11
H10
E9
H8
G10
H6
H5
G9
G8
G7
MT6323

A A

Title
03 MT6582 - Power & MT6323
Size Document Number Rev
D MT8382 TABLET V1.0

Date: Thursday, June 06, 2013 Sheet 3 of 13

5 4 3 2 1
5 4 3 2 1

Handset Microphone 1 Earphone RECEIVER 靠近耳机看口


[4] HP_MIC_R

close to IC

VR402
VR401
VR400
MICBIAS0

D C400 D
Close to MIC Close to BB C401
R400
0402
close to connector 0402
B400
33pF 33pF
0402 C440 22uF R401 33R HP_MP3L B401
[3] AU_HPL 0402 J401

0603
1K C441 22uF R403 33R B402
[3] AU_HPR 0402 CON_AJ_DIMA

0603
HP_MP3R C405 C406 C407

R402

1.5K
0402
C402 C403
Digital Microphone is reserved
0402 0402 0402

NC
0402
0603
33pF C404 NC NC
10uF 0402

33pF
1
AU_VIN0_P [3] [7] FM_ANT 0402 GND

0402
1 R407
0402
0R R406
0R L400

C408
100nF
MICP 2
MIC400 100pF [11] FM_ANT1 MIC
2
0402

0805
MICN
MIC_PAD C409 0402 3

2
R422

TV400
NC CH-L
AU_VIN0_N [3]

0402
0402
R408 22uH 4
0R

C410
100nF
CH-R

1
0R R409
[7] FM_RX_N_6627 0402 5
33pF C412
Analog MIC R410

0402
0402 0402

C411 33pF 1.5K 6 NC

Microphone: 6k~13k Ohm


TV402
TV401

R411 TV: 75 Ohm [2] EINT5_EAR R412 0402


47K 7018的耳机口

0402
1K VIO28_PMU 0402
R413 470K
tie together and single via to GND plane

VR403
IO400
CON_IO_MCB03-5K12004

C
HANDSET RECEIVER USB C
1 [3,4,12]
VCHG VBUS
6
7 2 [2,4,12]
D- USB_DM
3 [2,4,12]
D+ USB_DP

USB OTG Power


8
9 4 [2,4]
NC 0402
ENIT_IDDIG
R414 0R L401
5 U400
COM
close to connector RB551V-30
C413
0603 1 SW VOUT 5 VBUS
7018的耳机口 1uF
6 4 D400
[3]AU_HSN [1,3,6,8,12] VBAT VCC FB

R415
AU_OUT0_N_OUT

0402

1M
BEAD403
[2] GPIO_USB_DRVVBUS 3 EN GND 2
+
C2 C415
-
0402
0603
100pF RT9293BJ6 (TSOT-23)

R418

100K
4.7uF C416

0402
0603
REC1

R417

100K
10uF

0402
[3]AU_HSP
BEAD405

ENIT_IDDIG [2,4]
C418 C3
[3,4,12]
VR411

VBUS
VR412

0402 0402

33pF 33pF
USB_DM [2,4,12]

USB_DP [2,4,12]

TV405

TV406
TV403

TV404
B B

Earphone MICPHONE [3] MICBIAS1


AB类SPK
1K

GND of C454(10uF) and headset


0402
R419

Close to BB Close to MIC


should tie together and single
via to GND plane
C421
1uF

AU_VIN1_N1
0603

AU_VIN1_N [3]
0402

1.5K

10uF
C422

C423
Close to CON401
0402
0402

33pF
R421

C424
0402

100pF

C429 tie together and single via to GND plane


C428
1uF

0402

33pF HP_MIC_R
AU_VIN1_P [3] HP_MIC_R [4]
0402

A A
ACCDET [3] 0402
33pF (NC)
1k R425
0402

C434

Title
04 Audio,I/O,USB
Size Document Number Rev
D MT6575 PHONE V1.0

Date: Sunday, December 18, 2011 Sheet 4 of 13


5 4 3 2 1
Symbol PCDDR3 LPDDR2 Default

R533
BPI_BUS9 L (No Pull) L (No Pull) PD
BPI_BUS10 [6] BPI_BUS10 0402
4.7K VIO18_PMU
BPI_BUS10 H (4.7K) L (No Pull) PD
AUD_MOSI [2,3] AUD_MOSI 0402 VIO18_PMU
R544 4.7K Symbol PCDDR3L/1.35V LPDDR2 Default
PMIC_SPI_CS [2,3] PMIC_SPI_CS SPI_CSN L (4.7K) H (No Pull) PU
eMMC
R545
0402
1. VCC : Core Voltage 2.7v ~ 3.6v
4.7K
AUD_MOSI H (4.7K) L (No Pull) PD 2. VCCQ : IO Voltage 1.7v~1.95v (low voltage range)
VEMC_3V3_PMU VEMC_3V3_PMU
2.7v~3.6v(high voltage range)
VIO18_PMU VIO18_PMU
U503
U5
MC0_DAT0 [2] H3 DAT0 VCC M6
H4 N5

220NF

100NF
MC0_DAT1 [2] DAT1 VCC
ED0 E3 DQ0 A0 N3 EA0
H5 T10
MC0_DAT2 [2]

4.7uF
4.7uF
ED1 F7 P7 EA1 DAT2 VCC
DQ1 A1 MC0_DAT3 [2] J2 U9

0.1uF

0.1uF
DAT3 VCC

C546

C545
ED2 F2 DQ2 A2 P3 EA2
MC0_DAT4 [2] J3 DAT4 0402

ED3 F8 N2
0402
0603 0402 0402

DQ3 A3 EA3 0603

MC0_DAT5 [2] J4 K6

C555

C548
DAT5 VCCQ

C549
C547
ED4 H3 DQ4 A4 P8 EA4
J5 W4
MC0_DAT6 [2] DAT6 VCCQ
ED5 H8 DQ5 A5 P2 EA5
MC0_DAT7 [2] J6 DAT7 VCCQ Y4
ED6 G2 DQ6 A6 R8 EA6
VCCQ AA3
ED7 H7 DQ7 A7 R2 EA7
K2 AA5
ED8 D7 DQ8 A8 T8 EA8 VDDI VCCQ Close to Memory

C513
ED9 C3 DQ9 A9 R3 EA9
K4 VSSQ CMD W5 MC0_CMD [2]
ED10 C8 DQ10 A10/AP L7 EA10
Y2 W6
ED11 C2 R7 EA11 VSSQ CLK EMMC_CLK_R [5]
DQ11 A11 Y5
0402

ED12 A7 N7 EA12 VSSQ

1uF
DQ12 A12/BC# AA4 VSSQ RST#_/_NC U5
ED13 A2 T3 EA13 MC0_RSTB [2]
DQ13 A13 AA6 VSSQ A1_INDEX_/_NC L4
ED14 B8 DQ14 A14 T7 EA14
ED15 A3 DQ15 A15 M7 EA15
M7 K7
VSS NC
P5 VSS NC K8
CS1# L1 ECS1
R10 K9
EDQS1 C7 L9 VSS NC
UDQS ZQ1 U8 VSS NC K10
EDQS1_B B7 UDQS# CKE1 J9 ECKE
EMMC_CLK_R R504 27 5%

R525
NC K11 0402 MC0_CK [2]
EDQS0 F3 LDQS ODT1 J1 RODT_R
A4 K12
EDQS0_B G3 NC NC
LDQS# A6 K13

0402
EDQM1 D3 M2 EBA0 NC NC
UDM BA0 A9 NC NC K14
EDQM0 E7 LDM BA1 N8 EBA1
A11 L1
M3 EBA2 NC NC
BA2 B2 NC NC L2
DDRVREF CK J7 ECLK0
B13 L3
DDRVREF H1 K7 ECLK0_B NC NC
VREFDQ CK# D1 NC NC L12
M8 VREFCA CS# L2 ECS0
D14 L13
ERESET T2 K3 ECAS NC NC
C541 RESET# CAS# H1 NC NC L14
L8 ZQ ODT K1 RODT_R
H2 M1
0402

NC J3 ERAS NC NC
RAS# H8 NC NC M2
WE# L3 ERWE
H9 M3
K9 ECKE NC NC
CKE H10 NC NC M12
R565
0402

R573 H11 NC NC M13

0402
H12 NC NC M14
VSSQ_0 B1 H13 N1
VIO_EMI B9 NC NC
VSSQ_1 H14 NC NC N2
VSSQ_2 D1
J1 NC NC N3
A1 VDDQ_0 VSSQ_3 D8 J7 N12
A8 E2 NC NC
VDDQ_1 VSSQ_4 J8 NC NC N13
C1 VDDQ_2 VSSQ_5 E8
J9 NC NC N14
C9 VDDQ_3 VSSQ_6 F9 J10 P1
D2 G1 NC NC
VDDQ_4 VSSQ_7 J11 NC NC P2
E9 VDDQ_5 VSSQ_8 G9 J12 P12
F1 NC NC
VDDQ_6 J13 NC NC P13
H2 VDDQ_7 VSS_0 A9 J14 P14
H9 B3 NC NC
VDDQ_8 VSS_1 K1 NC NC T1
VSS_2 E1 K3 T2
B2 G8 NC NC
VDD_0 VSS_3 R1 NC NC T3
D9 VDD_1 VSS_4 J2 R2 T12
G7 J8 NC NC
VDD_2 VSS_5 R3 NC NC T13
K2 VDD_3 VSS_6 M1 R12 T14
K8 M9 NC NC
VDD_4 VSS_7 R13 NC NC V1
N1 VDD_5 VSS_8 P1 R14 V2
N9 P9 NC NC
VDD_6 VSS_9 U1 NC NC V3
R9 VDD_8 VSS_10 T1 U2 V12
R1 T9 NC NC
VDD_7 VSS_11 U3 NC NC V13
U12 NC NC V14
U13 NC NC Y1
U14 NC NC Y3
W1 NC NC Y6
W2 NC NC Y7
IC DDR3 x16 FBGA-96 W3 NC NC Y8
FBGA96/SMD/P0.8/10X14/DDR3L/16B W7 NC NC Y9
W8 NC NC Y10
W9 NC NC Y11
ECLK0 W10 Y12
NC NC
W11 NC NC Y13
W12 NC NC Y14
R501 W13 AE1
0402

NC NC
W14 NC NC AG2
AA1 NC NC AH4
VIO_EMI AA2 NC NC AH6
ECLK0_B AA8 AH9
NC NC
AA9 NC NC AH11
AA11 NC NC AG13
AA12 NC NC AE14
C557 C558 C560 C559 NC
0603 0603 0603 0603
0603 AA13 NC
4.7uF/6.3V/X5R 4.7uF/6.3V/X5R NC NC C561 AA14 NC
RFU H6
AA7 RFU RFU H7
DRAM VREF AA10 K5
VIO_EMI RFU RFU
U10 RFU RFU M5
U7 RFU RFU M8
U6 RFU RFU M9
T5 RFU RFU M10
R5 RFU RFU N10
C584 R572 P10 P3
0402

0402
DDRVREF RFU RFU
0.1uF/16V/X7R 1K_1%
Samsung KLM2G1HE3F-B001

R575
C585
C65
0402

0402
1K_1%
0.1uF/16V/X7R 0402

VIO_EMI 1uF/6.3V/X5R

Place between Main chip & DRAM


C567
C566 0402 C568 C569 C570 C571 C572
0402
0.1uF/16V/X7R 0402 0402 0402 0402 0402

0.1uF/16V/X7R NC NC NC NC NC
D D

SKY77590 control logic table RF_TX_ASM


Enable VctC VctB VctA 2G_HB [6]

2G_LB [6]
LB_GMSK_TX H L L H
HB_GMSK_TX H L H H
LB_EDGE_TX H H L H
HB_EDGE_TX H H H H
TRX1 L H L L

12

11

10

7
TRX2 L H H L

RX1

RX0

NC

GND

GND

GND
1

1
R716 0R
TRX3 L H L H E701 E700 0402
13

1
NC

C740
ANTENNA

22pF
ANTENNA
TRX4 L H H H C733 L712 0R 3x3x1.76mm J700 C732 GND 6
R712
0402
27R
GGE_PA_LB_IN [6]

0402
14
TRX5 L L H L ANTENNA

0402

0402
PA / RF7170
0402

0R C718 33pF C719 0402 GGE_PA_HB_IN [6]

0402
C734 C735 U702 5

C741
TRX6 L L L H RFIN_LB 56R L710 L711
0402

47pF
0402

R713
0402 0402

NC/22pF 39nH 15 GND


NC NC

0402

0402
GND 4
NM NM
16 GND 3

TX_ENABLE
RFIN_HB

GPCTRL1

GPCTRL0
2

VRAMP
GND

VBATT

GND
1

NC
GND

17

18

19

20

21

22

23
R703
0402 GGE_PA_VRAMP [6]
C714 R705 10K

0402
0402

220pF 24K

C701
0402

22pF
0402
GGE_PA_ENABLE [6]
0R 1K R701
R702 0402
ASM_VCTRL_A [6]
R704 0R
0402
ASM_VCTRL_B [6]

22pF
C742

22pF
0402

0402

C723
C C

VBAT [1,3,4,8,12]
C706 C707 C708 C710
0402 0402 0402
0603
5.6pF 22pF 0.1uF 22uF

U201-D

VTCXO_PMU

Power
B9 VM0 AVDD28_VTCXO D1
A9 VM1 0.1UF 0402

C642
VRF18_PMU
GGE_PA_VRAMP G8 APC

AVDD18_LF H1
ASM_VCTRL_A C11 BPI_BUS0

26M & CLK Buffer


Symbol eMMC/NAND Default ASM_VCTRL_B B11 0.1UF
BPI_BUS1 0402

ASM_VCTRL_C C9 BPI_BUS2 C644


BPI_BUS4 L (No Pull) PD GGE_PA_ENABLE C10 BPI_BUS3
HW trapping PIN BPI_BUS4
AVDD18_HF_TRX A8
Must be sure BPI_BUS4 is under R601 10K A12
0402 BPI_BUS4 0.1uF/16V/X7R
R602 10K A11
0.2*DVDD28_BPI during booting BPI_BUS4
0402

0402 BPI_BUS5 C645


Symbol Normal Mode Default R603 10K C12
BPI_BUS5 0402 BPI_BUS6
(please refer to HW design notice) BPI_BUS6 [7]GPIO_GPS_LNA_EN
BPI_BUS5 L (No Pull) PD [11] GPIO_ATV_EN
F9 BPI_BUS7 AVDD18_HF_DCO C1

GSM & TD
BPI_BUS6 L (No Pull) PD HW trapping PIN BPI_BUS5 and 6 CTP_RST

MT8312D_Cell RF
0.1UF
Must be sure BPI_BUS5 and 6 are under GPIO_ATV_RSTN
D12
0402

BPI_BUS8 C646
R604 10K E11
0.2*DVDD28_BPI during booting 0402 BPI_BUS9
BPI_BUS10 D9 BPI_BUS10
Symbol PCDDR3_16x2 Default (please refer to HW design notice) BPI_BUS9 E9 BPI_BUS11 XTAL1 E1 XTAL1
BPI_BUS10
BPI_BUS9 L (No Pull) PD XTAL2 F1 XTAL2
GGE_PA_HB_IN B6 TXO_HB
BPI_BUS10 H (4.7K) PD HW trapping PIN BPI_BUS9
A7 TXO_B40 CLK2 G6 CLK2_WIFI
Must be sure BPI_BUS9 is under
0.2*DVDD18_BPI during booting GGE_PA_LB_IN B7 TXO_LB Route ball G6 to
H2 CLK3_ATV
BPI_BUS10 pull high resistor is located CLK3_TP3
(please refer to HW design notice) ball H13 directly
B in page "06_Memory(eMMC+PCDDR3)" RX_900INP A4 RX_LBINN B
CLK4_TP4 G4 CLK4_AUDIO for better desense
RX_900INN B4 RX_LBINP
performance.
RX_DCSINP A3 RX_HBINN OUT_32K G5 DCXO_32K DCXO_32K

RX_DCSINN B2 RX_HBINP
XMODE_TP2 G2 VTCXO_PMU
VTCXO_PMU VTCXO_PMU
A5 RX_B40INN
G1 DCXO_32K_EN R632 0
DCXO_32KEN_TP1 0402 VTCXO_PMU
B5 RX_B40INP

R658

0402
NC

GND_CELL
GND_CELL
GND_CELL
GND_CELL
GND_CELL
GND_CELL
GND_CELL
GND_CELL
GND_CELL
GND_CELL
GND_CELL
GND_CELL
GND_CELL
GND_CELL
GND_CELL
GND_CELL
籔 R632 co-lay
MT8312D B3
B8
C2
C4
C5
C6
C7
D2
E2
F2
F4
F5
F6
F7
G3
G7
Put away from RF

Refer to page "03_MT6323L_PMIC" for 32K setting


CLK2,CLK4 should be on L2 with good ground shielding

Two Application Circuit Conditions,


1.TSX Circuit : X600=TSX, R653=R656=NC, R654=100K+-1%, R655=R657=0ohm
2.XTAL Circuit :X600=Mobile XTAL, R653=R656=0ohm, R654=R655=R657=NC
L605 12nH
0402 RX_900INP [6]
connect to main GND
L609
[3] AUXADC_REF
Route AUXADC_REF with 4mil trace width
39nH
L610
0402

0402

NC

NC
C613

10
22pF

L612 Z600 0402 R608 R609

0402

0402
C622 NC
[6]2G_LB
GND

L613 12nH 0R
0402

0402
1 9 X600
A NC LBIN LBOUT RX_900INN [6] R610
NC 0402
A
0402
2.2nH 0402

[3] THERM_ADC
Route AUXADC_TSX with 4mil trace width 4 GND HOT 3
C615 C616 2 GND LBOUT 8 0402
XTAL1 [6]
NC
3 GND HBOUT 7
C617
22pF

L614
L615 5.1NH/6.2nH [6] XTAL2 1 HOT GND 2
[6] 2G_HB 4 HBIN HBOUT 6 RX_DCSINP [6] R611
0402

GND

0402 0402

NC 3nH NC Connect TSX/XTAL GND Route AUXADC_GND with 24mil trace width 0402 1008002511/26MHZ
0402 [3] GND_AUXADC
900 1800MHz under AUXADC_REF/AUXADC_TSX trace
0402

C618 C619 to GND_AUXADC first NC


5

L616
7.5nH

R612
L617

0402
than connect to main GND
0402
0402

NC 0R
Close to each other
and nearby X600
L618
RX_DCSINN [6]
5.1NH/6.2nH
Route AUXADC_REF/AUXADC_TSX as differential trace with well GND shielding
0402

connect to main GND


and route AUXADC_GND with 24mil trace width under
Title
AUXADC_TSX/AUXADC_REF trace to provide return current path. RF-2G
Size Document Number Rev
D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 6 of 13

5 4 3 2 1
BT & WIFI
U201-B

GPS_RX_IP B16 GPS_RX_IP WB_RX_IP A22 WB_RXIP

GPS_RX_IN A16 GPS_RX_IN WB_RX_IN A21 WB_RXIN

GPS
GPS_RX_QP B15 GPS_RX_QP WB_RX_QP B20 WB_RXQP

GPS_RX_QN A15 GPS_RX_QN WB_RX_QN A20 WB_RXQN

WB_TX_IP A19 WB_TXIP

WB_TX_IN B19 WB_TXIN


D
FM_CLK E14 CONN_F2W_CLK WB_TX_QP A18 WB_TXQP

FM
FM_DATA E15 CONN_F2W_DAT WB_TX_QN B18 WB_TXQN

X800 7L26002015 CONN_WB_CTRL0 E19 WB_CTRL0

2
GND OUTPUT
3 MT8312D_CONN RF CONN_WB_CTRL1 D21 WB_CTRL1

CONN_WB_CTRL2 D17 WB_CTRL2


1 4
GND VCC
CONN_XO_IN H13 CONN_XO_IN CONN_WB_CTRL3 F17 WB_CTRL3

CLK
VCN_2V8_PMU

CONN_WB_CTRL4 D19 WB_CTRL4


0R R800
4 3 E17 WB_CTRL5
C801 VCC OUT 0402
CONN_WB_CTRL5
0402

1uF 1 2 F15 CONN_SCLK


NC GND CONN_SCLK

XTAL_16MHZ_3225 VWCN_1V8_PMU CONN_SDATA F14 CONN_SDATA

Power
R801 A14 AVDD18_WBG
0R F16 CONN_SEN
[6]CLK2_WIFI 0402 CONN_XO_IN [7] CONN_SEN
X801 NC 0.1uF/16V/X7R 0402

C900 CONN_RSTB H16 CONN_RSTB

GND_CONN
GND_CONN
GND_CONN
GND_CONN
GND_CONN
GND_CONN
GND_CONN
GND_CONN
GND_CONN
GND_CONN
GND_CONN
GND_CONN
Close to BB MT8312D

A17
B14
B17
B22
C15
C16
C17
C19
C20
C21
H14
H15
C WIFI/BT/GPS Single ANT Ref. WB_CTRL3 [7]
C

WB_CTRL2 [7]

[7] WB_CTRL4
ANT800 ANT801 [7]
WB_CTRL1
NA NA

WB_CTRL0 [7]
[7] WB_CTRL5

WB_RXIP [7]

R804 R1007
0402 0402 WB_RXIN [7]

29 AVDD18_WB
0R 0R
C803 C804

U801
0402 0402

NC NC

30

28

27

26

25

24

23

22

21
W_LNA_EXT

WB_CTRL5

WB_CTRL4

WB_CTRL3

WB_CTRL2

WB_CTRL1

WB_CTRL0
AVDD18_WBT

WB_RX_IN
WB_RX_IP
Optional: L1004 for better ESD performance
50 Ohm 31 WB_GPS_RF_IN WB_RX_QP 20 WB_RXQP [7]

R807 0R
R808 [7] AVDD18_WB 0402 VWCN_1V8_PMU
GPS_RF 50 Ohm 0402 32 GPS_DPX_RFOUT WB_RX_QN 19 WB_RXQN [7]
NC
R809 0R
[7] AVDD18_GPS 0402 VWCN_1V8_PMU

33 AVDD33_WBT WB_TX_IP 18 WB_TXIP [7]


[3,7]
VCN_3V3_PMU Star Conn
34 17
[7] for WB/GPS/WBG 1V8
NC WB_TX_IN WB_TXIN
50 Ohm 100nF 100pF
0402 0402 C810
C808 C809
0402

4.7nF
B [7] 1uF
35 16 B
0402

NC WB_TX_QP WB_TXQP C807

ANT802 ANT803
[3,7]
VCN_2V8_PMU 36 AVDD28_FM
MT6627PN_QFN40 WB_TX_QN 15 WB_TXQN
[7]
NA NA
R2
0402

0R
FM [4] 37 FM_LANT_N GPS_RX_IP 14 GPS_RX_IP
[7]

C14 C15 FM_RX_N_6627


0402

[4]
0402

NC NC L800 82nH
FM_ANT 0402 [7]
38 FM_LANT_P GPS_RX_IN 13 GPS_RX_IN

Same pad
R810 [7]
L801

GPS_RFIN 50 Ohm 39 12
NC

0402 GPS_RFIN GPS_RX_QP GPS_RX_QP


0402

NC
[7]
AVDD18_GPS [7]
40 AVDD18_GPS GPS_RX_QN 11 GPS_RX_QN CLose PIN36
R811

0R
0402

[3,7]
AVDD28_FSOURCE

41 DVSS VCN_2V8_PMU VCN_2V8_PMU

10nF

F2W_DATA
0402

F2W_CLK
C812
FM_DBG
HRST_B

SDATA

XO_IN
CEXT
SCLK
VCN_2V8_PMU

SEN
MT6627 SMD QFN40
1

10
Close to ANT
Close to MT6627
C1051
1uF

[7] CONN_RSTB [3,7] VCN_3V3_PMU VCN_3V3_PMU


NC
CONN_XO_IN[7]
0402

0402

A C826 C814 A
U1005 C815 4.7uF C819
100pF C818
0402 0603 0402
0402 0402

IC_SAW_SAFEB1G57KE0F00
0402

U1010
C816 C817 2.2uF
220nF
1 4 C1052 L1006 7.5nH [7] FM_DATA 1uF 100pF
3 RFIN VCC 4
IN OUT
0402

18pF 0402
2 GND SHDN 5
1 6
G
2 G
3 G

GND RFOUT [7] FM_CLK


5

IC_SAW_MAX2659 50 Ohm

[7] CONN_SCLK
[6] Title
GPIO_GPS_LNA_EN
[7] CONN_SDATA Wireless Connectivity
Size Document Number Rev
[7] CONN_SEN D MT6572 REF PHONE V1.0

Date: Friday, December 28, 2012 Sheet 7 of 13


5 4 3 2 1
VBAT [1,3,4,6,8,12] LCD_VDD[1,8]

C25
1uF C26
C848 1
LED-A

10K

R850
0402

0402
0402 0402

1uF [8] LEDA LED-A

1uF
3
LED-K
[8] LEDK 4
LED-K
5
GND
[8] VCOM 6
VCOM
[1,8]
LCD_VDD 7
DVDD
Q802 [8] MODE 8
MODE
[2] DPI_DE 9
T_DTC114EE DE
10

C
S
[2] [2] DPI_VSYNC VS
G B [2] DPI_HSYNC 11
VBAT_EN HS
12
[2] DPI_B7 B7
13

D
[2] DPI_B6 B6

MOS_SI2305
[2] DPI_B5 14
B5

E
15

Q801
[2] DPI_B4 B4
[2] DPI_B3 16
B3
17

AVDD
[2] DPI_B2 B2
18

[8]
[2] DPI_B1 B1
19

LX [8]
[2] DPI_B0 B0
[2] DPI_G7 20