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Data TA Distributio
LNCEL name Period start timeSum
300 - 0-78m Sum - 78-156m
212787_Lanraki_4G-2 1.38 2.29
03.30.2019 0.12 0.29
250
03.31.2019 0.28 0.29
04.01.2019 0.39 0.53
04.02.2019 200 0.19 0.45
04.03.2019 0.11 0.25
04.04.2019 0.18 0.25
150
04.05.2019 0.12 0.23
213823_DMT_TELKOMAS_4G-1 1.35 3.94
03.30.2019 100 0.12 0.45
03.31.2019 0.22 0.47
04.01.2019 0.11 0.49
50
04.02.2019 0.16 0.52
04.03.2019 0.19 0.69
04.04.2019 0 0.28 0.59
LNCEL na me 212787_Lanra ki _4G-2
04.05.2019 0.28 0.73
Total Result 2.73 6.24
TA Distribution
Sum - 156-312m Sum - 312-468m Sum - 468-624m Sum - 624-780m
44.04 181.71 283.79 127.19
5.98 26.12 42.49 14.62
Col umn B
5.41 30.54 40.27
Data
14.89
7.40 25.69 41.20
Col umn D 16.61
9.29 27.43 39.26
Col umn E 16.60
5.21 21.83 Col umn F
39.18 24.09
Col umn G
5.60 25.28 40.41 19.81
Col umn H
5.15 24.82 40.99
Col umn I
20.57
55.28 90.10 107.84
Col umn J 145.50
6.98 13.89 17.83
Col umn K 16.75
7.25 14.08 Col umn L
15.93 16.37
6.92 10.73 15.26 25.56
5.88 11.23 15.21 25.28
10.43 13.49 13.37 22.91
9.68 12.16 16.35 19.90
Lanra ki _4G-2
8.13 14.52 13.88 18.74
99.32 271.81 391.63 272.69
Sum - 780-1092m Sum - 1092-1404m Sum - 1404-1794m Sum - 1794-2262 Sum - +2262m
51.92 3.00 1.66 0.70 2.31
8.09 0.99 0.64 0.29 0.37
7.34 0.41 0.20 0.07 0.29
6.96 0.48 0.28 0.10 0.37
5.91 0.23 0.23 0.12 0.29
8.60 0.20 0.11 0.01 0.42
7.37 0.55 0.11 0.08 0.35
7.64 0.13 0.09 0.05 0.21
162.49 58.00 41.89 18.29 15.32
23.60 9.62 7.02 1.54 2.19
24.16 10.61 6.94 2.10 1.87
24.58 7.56 5.77 1.19 1.83
26.27 8.12 4.97 1.24 1.11
20.58 8.00 5.10 2.79 2.44
20.83 6.89 5.91 4.64 2.77
22.46 7.20 6.17 4.80 3.10
214.40 61.00 43.55 18.99 17.62
Sum - +2262m
Data

Period start time Check MRBTS/SBTS name LNBTS type

03.30.2019 Before MRBTS-212787_Lanraki_4G MacroBTS


03.30.2019 Before MRBTS-212787_Lanraki_4G MacroBTS
03.30.2019 Before MRBTS-212787_Lanraki_4G MacroBTS
03.31.2019 Before MRBTS-212787_Lanraki_4G MacroBTS
03.31.2019 Before MRBTS-212787_Lanraki_4G MacroBTS
03.31.2019 Before MRBTS-212787_Lanraki_4G MacroBTS
04.01.2019 Before MRBTS-212787_Lanraki_4G MacroBTS
04.01.2019 Before MRBTS-212787_Lanraki_4G MacroBTS
04.01.2019 Before MRBTS-212787_Lanraki_4G MacroBTS
04.02.2019 Before MRBTS-212787_Lanraki_4G MacroBTS
04.02.2019 Before MRBTS-212787_Lanraki_4G MacroBTS
04.02.2019 Before MRBTS-212787_Lanraki_4G MacroBTS
04.03.2019 After MRBTS-212787_Lanraki_4G MacroBTS
04.03.2019 After MRBTS-212787_Lanraki_4G MacroBTS
04.03.2019 After MRBTS-212787_Lanraki_4G MacroBTS
04.04.2019 After MRBTS-212787_Lanraki_4G MacroBTS
04.04.2019 After MRBTS-212787_Lanraki_4G MacroBTS
04.04.2019 After MRBTS-212787_Lanraki_4G MacroBTS
04.05.2019 After MRBTS-212787_Lanraki_4G MacroBTS
04.05.2019 After MRBTS-212787_Lanraki_4G MacroBTS
04.05.2019 After MRBTS-212787_Lanraki_4G MacroBTS
03.30.2019 Before MRBTS-213823_DMT_TELKOMASMacroBTS
03.30.2019 Before MRBTS-213823_DMT_TELKOMASMacroBTS
03.30.2019 Before MRBTS-213823_DMT_TELKOMASMacroBTS
03.31.2019 Before MRBTS-213823_DMT_TELKOMASMacroBTS
03.31.2019 Before MRBTS-213823_DMT_TELKOMASMacroBTS
03.31.2019 Before MRBTS-213823_DMT_TELKOMASMacroBTS
04.01.2019 Before MRBTS-213823_DMT_TELKOMASMacroBTS
04.01.2019 Before MRBTS-213823_DMT_TELKOMASMacroBTS
04.01.2019 Before MRBTS-213823_DMT_TELKOMASMacroBTS
04.02.2019 Before MRBTS-213823_DMT_TELKOMASMacroBTS
04.02.2019 Before MRBTS-213823_DMT_TELKOMASMacroBTS
04.02.2019 Before MRBTS-213823_DMT_TELKOMASMacroBTS
04.03.2019 After MRBTS-213823_DMT_TELKOMASMacroBTS
04.03.2019 After MRBTS-213823_DMT_TELKOMASMacroBTS
04.03.2019 After MRBTS-213823_DMT_TELKOMASMacroBTS
04.04.2019 After MRBTS-213823_DMT_TELKOMASMacroBTS
04.04.2019 After MRBTS-213823_DMT_TELKOMASMacroBTS
04.04.2019 After MRBTS-213823_DMT_TELKOMASMacroBTS
04.05.2019 After MRBTS-213823_DMT_TELKOMASMacroBTS
04.05.2019 After MRBTS-213823_DMT_TELKOMASMacroBTS
04.05.2019 After MRBTS-213823_DMT_TELKOMASMacroBTS

Page 5
Data

UE distance to base station


LNBTS name LNCEL name Cell size Avg UE dist 0-78m
LTE_1340A LTE_1339A LTE_1341A
212787_Lanraki_4G 212787_Lanraki_4G-1 2.100 0.534 0.07
212787_Lanraki_4G 212787_Lanraki_4G-2 2.100 0.570 0.12
212787_Lanraki_4G 212787_Lanraki_4G-3 2.100 0.535 0.39
212787_Lanraki_4G 212787_Lanraki_4G-1 2.100 0.536 0.11
212787_Lanraki_4G 212787_Lanraki_4G-2 2.100 0.549 0.28
212787_Lanraki_4G 212787_Lanraki_4G-3 2.100 0.518 0.20
212787_Lanraki_4G 212787_Lanraki_4G-1 2.100 0.551 0.25
212787_Lanraki_4G 212787_Lanraki_4G-2 2.100 0.551 0.39
212787_Lanraki_4G 212787_Lanraki_4G-3 2.100 0.523 0.33
212787_Lanraki_4G 212787_Lanraki_4G-1 2.100 0.554 0.12
212787_Lanraki_4G 212787_Lanraki_4G-2 2.100 0.538 0.19
212787_Lanraki_4G 212787_Lanraki_4G-3 2.100 0.535 0.23
212787_Lanraki_4G 212787_Lanraki_4G-1 2.100 0.525 0.14
212787_Lanraki_4G 212787_Lanraki_4G-2 2.100 0.574 0.11
212787_Lanraki_4G 212787_Lanraki_4G-3 2.100 0.525 0.24
212787_Lanraki_4G 212787_Lanraki_4G-1 2.100 0.544 0.16
212787_Lanraki_4G 212787_Lanraki_4G-2 2.100 0.560 0.18
212787_Lanraki_4G 212787_Lanraki_4G-3 2.100 0.538 0.29
212787_Lanraki_4G 212787_Lanraki_4G-1 2.100 0.553 0.08
212787_Lanraki_4G 212787_Lanraki_4G-2 2.100 0.557 0.12
212787_Lanraki_4G 212787_Lanraki_4G-3 2.100 0.522 0.34
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.798 0.12
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.749 0.42
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.705 0.64
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.818 0.22
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.793 0.26
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.664 0.71
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.802 0.11
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.775 0.11
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.721 0.91
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.780 0.16
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.752 0.18
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.699 0.57
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.783 0.19
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.898 0.31
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.587 0.65
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.829 0.28
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.958 0.08
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.515 0.55
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.843 0.28
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.930 0.10
213823_DMT_TELKOMAS_213823_DMT_TELKOMAS_4G 2.100 0.516 0.62

Page 6
Data

UE distance distribution in 2.1km cells


78-156m 156-312m 312-468m 468-624m 624-780m 780-1092m 1092-1404m 1404-1794m
LTE_1342A LTE_1343A LTE_1344A LTE_1345A LTE_1346A LTE_1347A LTE_1349A LTE_1350A
0.17 5.96 40.24 20.29 23.87 9.20 0.19 0.01
0.29 5.98 26.12 42.49 14.62 8.09 0.99 0.64
0.72 11.29 26.22 25.35 28.99 6.28 0.53 0.14
0.19 6.31 39.73 20.46 24.08 8.60 0.28 0.17
0.29 5.41 30.54 40.27 14.89 7.34 0.41 0.20
0.40 13.54 28.55 23.68 27.50 5.73 0.35 0.04
0.17 6.87 35.37 18.74 27.06 11.32 0.20 0.01
0.53 7.40 25.69 41.20 16.61 6.96 0.48 0.28
0.59 13.88 26.63 25.28 26.56 6.03 0.54 0.06
0.35 5.33 35.40 18.96 27.87 11.91 0.06 0.00
0.45 9.29 27.43 39.26 16.60 5.91 0.23 0.23
0.59 11.30 26.77 25.43 28.55 6.24 0.72 0.08
0.52 5.62 41.21 20.11 23.92 8.30 0.15 0.02
0.25 5.21 21.83 39.18 24.09 8.60 0.20 0.11
0.56 12.79 26.66 29.30 24.03 5.75 0.49 0.08
0.28 4.56 36.93 21.49 27.89 8.43 0.24 0.02
0.25 5.60 25.28 40.41 19.81 7.37 0.55 0.11
0.57 12.01 28.02 21.80 29.03 7.22 0.75 0.24
0.15 5.43 36.37 19.89 27.62 10.18 0.25 0.03
0.23 5.15 24.82 40.99 20.57 7.64 0.13 0.09
0.82 15.77 24.21 25.69 27.53 4.80 0.72 0.06
0.45 6.98 13.89 17.83 16.75 23.60 9.62 7.02
2.45 8.45 12.78 20.48 18.08 25.20 4.41 0.86
2.11 13.90 21.94 17.93 12.85 13.79 6.05 7.14
0.47 7.25 14.08 15.93 16.37 24.16 10.61 6.94
1.42 5.76 9.74 20.33 19.33 31.18 3.86 1.12
1.82 15.93 21.74 19.72 13.61 10.34 6.50 7.08
0.49 6.92 10.73 15.26 25.56 24.58 7.56 5.77
1.20 6.72 9.03 19.66 19.15 33.50 3.75 0.93
2.23 12.60 21.07 15.46 14.41 13.31 6.11 10.60
0.52 5.88 11.23 15.21 25.28 26.27 8.12 4.97
1.43 8.57 9.05 24.35 19.20 26.51 2.90 0.90
1.93 12.61 20.33 18.18 16.09 14.82 5.14 6.36
0.69 10.43 13.49 13.37 22.91 20.58 8.00 5.10
1.25 4.92 8.29 18.07 16.03 25.66 5.31 1.38
2.44 17.43 30.40 18.80 10.04 8.95 4.74 4.77
0.59 9.68 12.16 16.35 19.90 20.83 6.89 5.91
0.72 4.46 8.18 16.99 15.60 28.75 5.81 2.70
2.54 17.72 34.44 19.48 12.00 7.28 2.66 2.70
0.73 8.13 14.52 13.88 18.74 22.46 7.20 6.17
0.89 4.30 8.53 15.66 17.40 31.71 4.46 2.12
2.51 19.73 33.19 19.01 10.54 7.41 2.63 3.51

Page 7
Data

UE distance distribution in 5km cells


1794-2262m +2262m 0-0.5km 0.5-1.0km 1.0-1.5km 1.5-2.0km 2.0-2.7km 2.7-3.4km
LTE_1351A LTE_1352A LTE_1353A LTE_1354A LTE_1355A LTE_1357A LTE_1359A LTE_1360A
0.00 0.01
0.29 0.37
0.07 0.02
0.07 0.00
0.07 0.29
0.00 0.02
0.01 0.01
0.10 0.37
0.05 0.04
0.00 0.00
0.12 0.29
0.04 0.05
0.00 0.00
0.01 0.42
0.01 0.09
0.00 0.01
0.08 0.35
0.06 0.02
0.00 0.00
0.05 0.21
0.05 0.00
1.54 2.19
5.60 1.28
1.93 1.74
2.10 1.87
5.78 1.22
1.83 0.72
1.19 1.83
5.16 0.80
1.84 1.46
1.24 1.11
5.96 0.97
2.18 1.80
2.79 2.44
15.20 3.57
1.22 0.58
4.64 2.77
13.91 2.81
0.26 0.36
4.80 3.10
11.98 2.86
0.27 0.58

Page 8
Data

ution in 5km cells UE distance distribution


3.4-4.1km 4.1-4.8km 4.8-5.6km +5.6km 0-1.0km 1.0-2.0km 2.0-3.0km 3.0-4.0km
LTE_1361A LTE_1362A LTE_1363A LTE_1364A LTE_1365A LTE_1366A LTE_1367A LTE_1368A

Page 9
Data

UE distance distribution in 10km cells


4.0-5.3km 5.3-6.9km 6.9-8.6km 8.6-9.5km 9.5-11.1km +11.1km 0-1.5km 1.5-3.0km
LTE_1369A LTE_1370A LTE_1371A LTE_1372A LTE_1373A LTE_1374A LTE_1375A LTE_1376A

Page 10
Data

UE distance distribution in 15km cells


3.0-4.5km 4.5-6.0km 6.0-8.0km 8.0-10.4km 10.4-12.9km 12.9-14.6km 14.6-16.6km +16.6km
LTE_1377A LTE_1378A LTE_1379A LTE_1380A LTE_1381A LTE_1382B LTE_1383A LTE_1384A

Page 11
Data

UE distance distribution in 30km cells


0-3.0km 3.0-6.0km 6.0-9.0km 9.0-12km 12-16km 16-21km 21-26km 26-33km
LTE_1385A LTE_1386A LTE_1387A LTE_1388A LTE_1389A LTE_1390A LTE_1391A LTE_1392A

Page 12
Data

UE distance distribution in 60km cells


+33km 0-6.0km 6.0-12km 12-15km 15-18km 18-24km 24-32km 32-41km
LTE_1393A LTE_1394A LTE_1395A LTE_1396A LTE_1397A LTE_1398A LTE_1399A LTE_1400A

Page 13
Data

m cells UE distance distribution in 100km cells


41-52km 52-63km +63km 0-10km 10-20km 20-30km 30-40km 40-53km
LTE_1401A LTE_1402A LTE_1403A LTE_1404A LTE_1405A LTE_1406A LTE_1407A LTE_1408A

Page 14
Data

istribution in 100km cells


53-69km 69-87km 87-105km +105km
LTE_1409A LTE_1410A LTE_1411A LTE_1412A

Page 15
Documentation

Report Title RSLTE058 - Timing advance


NOP Report Release Version RSLTE LTE17SP
RS Report Release Version 17.3.2-545
Report ID rslte_LTE17A/reports/RSLTE058.xml
Report Description Timing advance
Start Time 03.30.2019 00:00:00
End Time 04.06.2019 00:00:00
Objects Level: RSLTE-LNBTS-2; 212787_Lanraki_4G ('20853284'), 213823_DMT_T
Object Aggregation Level PLMN/LNBTS_parent/LNBTS/LNCEL
Time Aggregation Level day
Threshold none
Data Source pmrPool
Advanced Filter none

KPI ID KPI Alias KPI Title


LTE_1340a Cell size Expected cel
LTE_1339a Avg UE dist Average UE
LTE_1341a 0-78m % UEs with d
LTE_1342a 78-156m % UEs with d
LTE_1343a 156-312m % UEs with d
LTE_1344a 312-468m % UEs with d
LTE_1345a 468-624m % UEs with d
LTE_1346a 624-780m % UEs with d
LTE_1347a 780-1092m % UEs with d
LTE_1349a 1092-1404m % UEs with d
LTE_1350a 1404-1794m % UEs with d
LTE_1351a 1794-2262m % UEs with d
LTE_1352a +2262m % UEs with
LTE_1353a 0-0.5km % UEs with d
LTE_1354a 0.5-1.0km % UEs with d
LTE_1355a 1.0-1.5km % UEs with d
LTE_1357a 1.5-2.0km % UEs with d
LTE_1359a 2.0-2.7km % UEs with d
LTE_1360a 2.7-3.4km % UEs with d
LTE_1361a 3.4-4.1km % UEs with d
LTE_1362a 4.1-4.8km % UEs with d
LTE_1363a 4.8-5.6km % UEs with d
LTE_1364a +5.6km % UEs with
LTE_1365a 0-1.0km % UEs with d
LTE_1366a 1.0-2.0km % UEs with d
LTE_1367a 2.0-3.0km % UEs with d
LTE_1368a 3.0-4.0km % UEs with d
LTE_1369a 4.0-5.3km % UEs with d

Page 16
Documentation

LTE_1370a 5.3-6.9km % UEs with d


LTE_1371a 6.9-8.6km % UEs with d
LTE_1372a 8.6-9.5km % UEs with d
LTE_1373a 9.5-11.1km % UEs with d
LTE_1374a +11.1km % UEs with
LTE_1375a 0-1.5km % UEs with d
LTE_1376a 1.5-3.0km % UEs with d
LTE_1377a 3.0-4.5km % UEs with d
LTE_1378a 4.5-6.0km % UEs with d
LTE_1379a 6.0-8.0km % UEs with d
LTE_1380a 8.0-10.4km % UEs with d
LTE_1381a 10.4-12.9km % UEs with d
LTE_1382b 12.9-14.6km % UEs with d
LTE_1383a 14.6-16.6km % UEs with d
LTE_1384a +16.6km % UEs with
LTE_1385a 0-3.0km % UEs with d
LTE_1386a 3.0-6.0km % UEs with d
LTE_1387a 6.0-9.0km % UEs with d
LTE_1388a 9.0-12km % UEs with d
LTE_1389a 12-16km % UEs with d
LTE_1390a 16-21km % UEs with d
LTE_1391a 21-26km % UEs with d
LTE_1392a 26-33km % UEs with d
LTE_1393a +33km % UEs with
LTE_1394a 0-6.0km % UEs with d
LTE_1395a 6.0-12km % UEs with d
LTE_1396a 12-15km % UEs with d
LTE_1397a 15-18km % UEs with d
LTE_1398a 18-24km % UEs with d
LTE_1399a 24-32km % UEs with d
LTE_1400a 32-41km % UEs with d
LTE_1401a 41-52km % UEs with d
LTE_1402a 52-63km % UEs with d
LTE_1403a +63km % UEs with
LTE_1404a 0-10km % UEs with d
LTE_1405a 10-20km % UEs with d
LTE_1406a 20-30km % UEs with d
LTE_1407a 30-40km % UEs with d
LTE_1408a 40-53km % UEs with d
LTE_1409a 53-69km % UEs with d
LTE_1410a 69-87km % UEs with d
LTE_1411a 87-105km % UEs with d
LTE_1412a +105km % UEs with

Page 17
Documentation

20853284'), 213823_DMT_TELKOMAS_4G ('26316701')

KPI Formul Unit


lmac_ext.av[km]
lmac_ext.ue[km]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]

Page 18
Documentation

100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]

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Cache handler
Evaluation method
Init duration
Sql generation
Execution duration
Load from cache
Create tmp Tables
Drop tmp Tables
Load data db
Load data and write to cache

Start Time
2019-04-06 15:30:53.495

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2019-04-06 15:31:01.297

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Report Execution

2019-04-06 15:31:02.85

2019-04-06 15:31:02.98

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com.nokia.oss.qengine.support.CacheAwareEngine
tmp tables(1)
0.104
0.066
9.136
none
8.603
none
none
none

End Time Note Sql


2019-04-06 15:31:01.296 creating tmp table: jf_LMAC_ext_0614311376
create global temporary table jf_LMAC
select
trunc( p.period_start_time, 'dd' )
"lncel".co_gid lncel_gid,
AVG(TIMING_ADV_SET_INDEX
AVG(decode(TIMING_ADV_SET_
AVG(DECODE((TIMING_ADV_BI
from

utp_common_objects "plmn",
utp_common_objects "vloflnbts
utp_common_objects "lnbts",
utp_common_objects "lncel",
ctp_common_objects bts_type,
NOKLTE_PS_LMAC_MNC1_RA
where
"lnbts".co_gid in ( '20853284','26
and period_start_time >= to_dat
and period_start_time < to_date
and "plmn".co_oc_id = 16

and "vloflnbtsparent".co_parent_
and "vloflnbtsparent".co_gid = p.mr
and ( "vloflnbtsparent".co_oc_id
and "lnbts".co_gid = p.lnbts_id
and "lnbts".co_parent_gid = "vlof
and "lnbts".co_oc_id = 3129
and "lncel".co_gid = p.lncel_id
and "lncel".co_parent_gid = "lnbt
and "lncel".co_oc_id = 3130

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Report Execution

and "lnbts".co_gid = bts_type.co_g


group by
trunc( p.period_start_time, 'dd' ),
"lncel".co_gid
2019-04-06 15:31:02.84 creating tmp table: jf_LMAC2_0682515099
create global temporary table jf_LMAC
select
a.period_start_time,
a.lncel_gid,
SUM(TIMING_ADV_BIN_1) TIMING_A
SUM(TIMING_ADV_BIN_2) TIMIN
SUM(TIMING_ADV_BIN_3) TIMIN
SUM(TIMING_ADV_BIN_4) TIMIN
SUM(TIMING_ADV_BIN_5) TIMIN
SUM(TIMING_ADV_BIN_6) TIMIN
SUM(TIMING_ADV_BIN_7) TIMIN
SUM(TIMING_ADV_BIN_8) TIMIN
SUM(TIMING_ADV_BIN_9) TIMIN
SUM(TIMING_ADV_BIN_10) TIM
SUM(TIMING_ADV_BIN_11) TIM
SUM(TIMING_ADV_BIN_12) TIM
SUM(TIMING_ADV_BIN_13) TIM
SUM(TIMING_ADV_BIN_14) TIM
SUM(TIMING_ADV_BIN_15) TIM
SUM(TIMING_ADV_BIN_16) TIM
SUM(TIMING_ADV_BIN_17) TIM
SUM(TIMING_ADV_BIN_18) TIM
SUM(TIMING_ADV_BIN_19) TIM
SUM(TIMING_ADV_BIN_20) TIM
SUM(TIMING_ADV_BIN_21) TIM
SUM(TIMING_ADV_BIN_22) TIM
SUM(TIMING_ADV_BIN_23) TIM
SUM(TIMING_ADV_BIN_24) TIM
SUM(TIMING_ADV_BIN_25) TIM
SUM(TIMING_ADV_BIN_26) TIM
SUM(TIMING_ADV_BIN_27) TIM
SUM(TIMING_ADV_BIN_28) TIM
SUM(TIMING_ADV_BIN_29) TIM
SUM(TIMING_ADV_BIN_30) TIM
from
(
select
trunc( p.period_start_time, 'dd' )
"vloflnbtsparent".co_gid vloflnbtsp
decode(substr(bts_type.co_sys_v

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"lnbts".co_gid lnbts_gid,
"lncel".co_gid lncel_gid,
SUM(TIMING_ADV_BIN_1) TIM
SUM(TIMING_ADV_BIN_2) TIMIN
SUM(TIMING_ADV_BIN_3) TIMIN
SUM(TIMING_ADV_BIN_4) TIMIN
SUM(TIMING_ADV_BIN_5) TIMIN
SUM(TIMING_ADV_BIN_6) TIMIN
SUM(TIMING_ADV_BIN_7) TIMIN
SUM(TIMING_ADV_BIN_8) TIMIN
SUM(TIMING_ADV_BIN_9) TIMIN
SUM(TIMING_ADV_BIN_10) TIM
SUM(TIMING_ADV_BIN_11) TIM
SUM(TIMING_ADV_BIN_12) TIM
SUM(TIMING_ADV_BIN_13) TIM
SUM(TIMING_ADV_BIN_14) TIM
SUM(TIMING_ADV_BIN_15) TIM
SUM(TIMING_ADV_BIN_16) TIM
SUM(TIMING_ADV_BIN_17) TIM
SUM(TIMING_ADV_BIN_18) TIM
SUM(TIMING_ADV_BIN_19) TIM
SUM(TIMING_ADV_BIN_20) TIM
SUM(TIMING_ADV_BIN_21) TIM
SUM(TIMING_ADV_BIN_22) TIM
SUM(TIMING_ADV_BIN_23) TIM
SUM(TIMING_ADV_BIN_24) TIM
SUM(TIMING_ADV_BIN_25) TIM
SUM(TIMING_ADV_BIN_26) TIM
SUM(TIMING_ADV_BIN_27) TIM
SUM(TIMING_ADV_BIN_28) TIM
SUM(TIMING_ADV_BIN_29) TIM
SUM(TIMING_ADV_BIN_30) TIM
from

utp_common_objects "plmn",
utp_common_objects "vloflnbts
utp_common_objects "lnbts",
utp_common_objects "lncel",
ctp_common_objects bts_type,
noklte_ps_lmac_lncel_day p
where
"lnbts".co_gid in ( '20853284','26
and period_start_time >= to_dat
and period_start_time < to_date
and "plmn".co_oc_id = 16

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Report Execution

and "vloflnbtsparent".co_parent_
and "vloflnbtsparent".co_gid = p.mr
and ( "vloflnbtsparent".co_oc_id
and "lnbts".co_gid = p.lnbts_id
and "lnbts".co_parent_gid = "vlof
and "lnbts".co_oc_id = 3129
and "lncel".co_gid = p.lncel_id
and "lncel".co_parent_gid = "lnbt
and "lncel".co_oc_id = 3130
and "lnbts".co_gid = bts_type.co_g
group by
trunc( p.period_start_time, 'dd' ),
"vloflnbtsparent".co_gid,
decode(substr(bts_type.co_sys_v
"lnbts".co_gid,
"lncel".co_gid
)a
group by
a.period_start_time,
a.lncel_gid
2019-04-06 15:31:02.98 creating tmp table: jf_ALLTABLES_0617319017
create global temporary table jf_ALLTA
select
period_start_time,
lncel_gid
from
(
(
select
period_start_time, TO_CHAR(lnce
from
jf_LMAC2_0682515099
)
UNION
(
select
period_start_time, TO_CHAR(lnce
from
jf_LMAC_ext_0614311376
)
)p
2019-04-06 15:31:02.631 report from tmp tables
select
ALLTABLES.period_start_time pe

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Report Execution

case "vloflnbtsparent".co_oc_id w
decode(substr(bts_type.co_sys_v
nvl("lnbts".co_name, nvl("lnbts".co
nvl("lncel".co_name, nvl("lncel".co
ALLTABLES.lncel_gid, nvl("lncel".
to_number(lmac_ext.avg_tim_adv
to_number(lmac_ext.ue_dist_avg
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext

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Report Execution

to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
to_number(100*decode(lmac_ext
from
utp_common_objects "vloflnbtspa
utp_common_objects "lnbts",
utp_common_objects "lncel",
ctp_common_objects bts_type
,
jf_ALLTABLES_0617319017 ALLTA
jf_LMAC2_0682515099 LMAC2,
jf_LMAC_ext_0614311376 LMAC_
where
"lnbts".co_parent_gid = "vloflnbtsp
"lncel".co_parent_gid = "lnbts".co_
ALLTABLES.lncel_gid = "lncel".co
and "lnbts".co_gid = bts_type.co_

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Report Execution

and ALLTABLES.period_start_tim
and ALLTABLES.period_start_tim

order by
2,1,3,4,5

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Report Execution

MAC_ext_0614311376
al temporary table jf_LMAC_ext_0614311376 on commit preserve rows as

( p.period_start_time, 'dd' ) period_start_time,


co_gid lncel_gid,
TIMING_ADV_SET_INDEX) TIMING_ADV_SET_INDEX,
ecode(TIMING_ADV_SET_INDEX ,1,2.1 ,2,5 ,3,10 ,4,15 ,5,30 ,6,60 ,7,100 ,NULL)) AVG_TIM_ADV_INDEX,
ECODE((TIMING_ADV_BIN_1+TIMING_ADV_BIN_2+TIMING_ADV_BIN_3+TIMING_ADV_BIN_4+TIMING_ADV_BIN_5+TIM

common_objects "plmn",
common_objects "vloflnbtsparent",
common_objects "lnbts",
common_objects "lncel",
mmon_objects bts_type,
LTE_PS_LMAC_MNC1_RAW p

s".co_gid in ( '20853284','26316701' )
eriod_start_time >= to_date('2019/03/30 00:00:00', 'yyyy/mm/dd hh24:mi:ss')
eriod_start_time < to_date('2019/04/05 23:59:59', 'yyyy/mm/dd hh24:mi:ss')
plmn".co_oc_id = 16

vloflnbtsparent".co_parent_gid = "plmn".co_gid
flnbtsparent".co_gid = p.mrbts_id
"vloflnbtsparent".co_oc_id = 3128 or "vloflnbtsparent".co_oc_id = 739 )
nbts".co_gid = p.lnbts_id
nbts".co_parent_gid = "vloflnbtsparent".co_gid
nbts".co_oc_id = 3129
ncel".co_gid = p.lncel_id
ncel".co_parent_gid = "lnbts".co_gid
ncel".co_oc_id = 3130

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Report Execution

ts".co_gid = bts_type.co_gid

( p.period_start_time, 'dd' ),

MAC2_0682515099
al temporary table jf_LMAC2_0682515099 on commit preserve rows as

G_ADV_BIN_1) TIMING_ADV_BIN_1,
TIMING_ADV_BIN_2) TIMING_ADV_BIN_2,
TIMING_ADV_BIN_3) TIMING_ADV_BIN_3,
TIMING_ADV_BIN_4) TIMING_ADV_BIN_4,
TIMING_ADV_BIN_5) TIMING_ADV_BIN_5,
TIMING_ADV_BIN_6) TIMING_ADV_BIN_6,
TIMING_ADV_BIN_7) TIMING_ADV_BIN_7,
TIMING_ADV_BIN_8) TIMING_ADV_BIN_8,
TIMING_ADV_BIN_9) TIMING_ADV_BIN_9,
TIMING_ADV_BIN_10) TIMING_ADV_BIN_10,
TIMING_ADV_BIN_11) TIMING_ADV_BIN_11,
TIMING_ADV_BIN_12) TIMING_ADV_BIN_12,
TIMING_ADV_BIN_13) TIMING_ADV_BIN_13,
TIMING_ADV_BIN_14) TIMING_ADV_BIN_14,
TIMING_ADV_BIN_15) TIMING_ADV_BIN_15,
TIMING_ADV_BIN_16) TIMING_ADV_BIN_16,
TIMING_ADV_BIN_17) TIMING_ADV_BIN_17,
TIMING_ADV_BIN_18) TIMING_ADV_BIN_18,
TIMING_ADV_BIN_19) TIMING_ADV_BIN_19,
TIMING_ADV_BIN_20) TIMING_ADV_BIN_20,
TIMING_ADV_BIN_21) TIMING_ADV_BIN_21,
TIMING_ADV_BIN_22) TIMING_ADV_BIN_22,
TIMING_ADV_BIN_23) TIMING_ADV_BIN_23,
TIMING_ADV_BIN_24) TIMING_ADV_BIN_24,
TIMING_ADV_BIN_25) TIMING_ADV_BIN_25,
TIMING_ADV_BIN_26) TIMING_ADV_BIN_26,
TIMING_ADV_BIN_27) TIMING_ADV_BIN_27,
TIMING_ADV_BIN_28) TIMING_ADV_BIN_28,
TIMING_ADV_BIN_29) TIMING_ADV_BIN_29,
TIMING_ADV_BIN_30) TIMING_ADV_BIN_30

( p.period_start_time, 'dd' ) period_start_time,


btsparent".co_gid vloflnbtsparent_gid,
e(substr(bts_type.co_sys_version,1,3),'FLF','FlexiZoneMicroBTS','TLF','FlexiZoneMicroBTS','FLC','FlexiZoneControllerBTS','TL

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Report Execution

co_gid lnbts_gid,
co_gid lncel_gid,
TIMING_ADV_BIN_1) TIMING_ADV_BIN_1,
TIMING_ADV_BIN_2) TIMING_ADV_BIN_2,
TIMING_ADV_BIN_3) TIMING_ADV_BIN_3,
TIMING_ADV_BIN_4) TIMING_ADV_BIN_4,
TIMING_ADV_BIN_5) TIMING_ADV_BIN_5,
TIMING_ADV_BIN_6) TIMING_ADV_BIN_6,
TIMING_ADV_BIN_7) TIMING_ADV_BIN_7,
TIMING_ADV_BIN_8) TIMING_ADV_BIN_8,
TIMING_ADV_BIN_9) TIMING_ADV_BIN_9,
TIMING_ADV_BIN_10) TIMING_ADV_BIN_10,
TIMING_ADV_BIN_11) TIMING_ADV_BIN_11,
TIMING_ADV_BIN_12) TIMING_ADV_BIN_12,
TIMING_ADV_BIN_13) TIMING_ADV_BIN_13,
TIMING_ADV_BIN_14) TIMING_ADV_BIN_14,
TIMING_ADV_BIN_15) TIMING_ADV_BIN_15,
TIMING_ADV_BIN_16) TIMING_ADV_BIN_16,
TIMING_ADV_BIN_17) TIMING_ADV_BIN_17,
TIMING_ADV_BIN_18) TIMING_ADV_BIN_18,
TIMING_ADV_BIN_19) TIMING_ADV_BIN_19,
TIMING_ADV_BIN_20) TIMING_ADV_BIN_20,
TIMING_ADV_BIN_21) TIMING_ADV_BIN_21,
TIMING_ADV_BIN_22) TIMING_ADV_BIN_22,
TIMING_ADV_BIN_23) TIMING_ADV_BIN_23,
TIMING_ADV_BIN_24) TIMING_ADV_BIN_24,
TIMING_ADV_BIN_25) TIMING_ADV_BIN_25,
TIMING_ADV_BIN_26) TIMING_ADV_BIN_26,
TIMING_ADV_BIN_27) TIMING_ADV_BIN_27,
TIMING_ADV_BIN_28) TIMING_ADV_BIN_28,
TIMING_ADV_BIN_29) TIMING_ADV_BIN_29,
TIMING_ADV_BIN_30) TIMING_ADV_BIN_30

common_objects "plmn",
common_objects "vloflnbtsparent",
common_objects "lnbts",
common_objects "lncel",
mmon_objects bts_type,
e_ps_lmac_lncel_day p

s".co_gid in ( '20853284','26316701' )
eriod_start_time >= to_date('2019/03/30 00:00:00', 'yyyy/mm/dd hh24:mi:ss')
eriod_start_time < to_date('2019/04/05 23:59:59', 'yyyy/mm/dd hh24:mi:ss')
plmn".co_oc_id = 16

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Report Execution

vloflnbtsparent".co_parent_gid = "plmn".co_gid
flnbtsparent".co_gid = p.mrbts_id
"vloflnbtsparent".co_oc_id = 3128 or "vloflnbtsparent".co_oc_id = 739 )
nbts".co_gid = p.lnbts_id
nbts".co_parent_gid = "vloflnbtsparent".co_gid
nbts".co_oc_id = 3129
ncel".co_gid = p.lncel_id
ncel".co_parent_gid = "lnbts".co_gid
ncel".co_oc_id = 3130
ts".co_gid = bts_type.co_gid

( p.period_start_time, 'dd' ),
btsparent".co_gid,
e(substr(bts_type.co_sys_version,1,3),'FLF','FlexiZoneMicroBTS','TLF','FlexiZoneMicroBTS','FLC','FlexiZoneControllerBTS','TL

LLTABLES_0617319017
al temporary table jf_ALLTABLES_0617319017 on commit preserve rows as

_start_time, TO_CHAR(lncel_gid) lncel_gid

C2_0682515099

_start_time, TO_CHAR(lncel_gid) lncel_gid

C_ext_0614311376

BLES.period_start_time period_start_time,

Page 34
Report Execution

vloflnbtsparent".co_oc_id when 3128 then 'MRBTS-' when 739 then 'SBTS-' end || nvl("vloflnbtsparent".co_name, nvl("vloflnbtsp
e(substr(bts_type.co_sys_version,1,3),'FLF','FlexiZoneMicroBTS','TLF','FlexiZoneMicroBTS','FLC','FlexiZoneControllerBTS','TL
bts".co_name, nvl("lnbts".co_object_instance, 'NN('||"lnbts".co_gid||')')) "LNBTS name",
cel".co_name, nvl("lncel".co_object_instance, 'NN('||"lncel".co_gid||')')) "LNCEL name",
BLES.lncel_gid, nvl("lncel".co_ext_dn, "lncel".co_dn) "DN",
mber(lmac_ext.avg_tim_adv_index) LTE_1340a,
mber(lmac_ext.ue_dist_avg) LTE_1339a,
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin

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mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin


mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin
mber(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timin

mmon_objects "vloflnbtsparent",
mmon_objects "lnbts",
mmon_objects "lncel",
ommon_objects bts_type

ABLES_0617319017 ALLTABLES,
C2_0682515099 LMAC2,
C_ext_0614311376 LMAC_ext

co_parent_gid = "vloflnbtsparent".co_gid and


co_parent_gid = "lnbts".co_gid and
BLES.lncel_gid = "lncel".co_gid
bts".co_gid = bts_type.co_gid

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Report Execution

LTABLES.period_start_time = LMAC2.period_start_time (+) and ALLTABLES.lncel_gid = LMAC2.lncel_gid (+)


LTABLES.period_start_time = LMAC_ext.period_start_time (+) and ALLTABLES.lncel_gid = LMAC_ext.lncel_gid (+)

Page 37
Report Execution

_ADV_INDEX,
BIN_4+TIMING_ADV_BIN_5+TIMING_ADV_BIN_6+TIMING_ADV_BIN_7+TIMING_ADV_BIN_8+TIMING_ADV_BIN_9+TIMING

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LC','FlexiZoneControllerBTS','TLC','FlexiZoneControllerBTS','MacroBTS') LNBTS_type,

Page 39
Report Execution

LC','FlexiZoneControllerBTS','TLC','FlexiZoneControllerBTS','MacroBTS'),

Page 40
Report Execution

sparent".co_name, nvl("vloflnbtsparent".co_object_instance, 'NN('||"vloflnbtsparent".co_gid||')')) "MRBTS/SBTS name",


LC','FlexiZoneControllerBTS','TLC','FlexiZoneControllerBTS','MacroBTS') "LNBTS type",

2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6


2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6

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2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6


2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6
2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6

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C2.lncel_gid (+)
MAC_ext.lncel_gid (+)

Page 43
Report Execution

_8+TIMING_ADV_BIN_9+TIMING_ADV_BIN_10+ TIMING_ADV_BIN_11+TIMING_ADV_BIN_12+TIMING_ADV_BIN_13+TIMI

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Report Execution

) "MRBTS/SBTS name",

_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi


_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi

Page 45
Report Execution

_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi


_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi
_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin_9 + lmac2.timi

Page 46
Report Execution

_12+TIMING_ADV_BIN_13+TIMING_ADV_BIN_14+TIMING_ADV_BIN_15+TIMING_ADV_BIN_16+TIMING_ADV_BIN_17+TIM

Page 47
Report Execution

c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b


c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b

Page 48
Report Execution

c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b


c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b
c2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_b

Page 49
Report Execution

N_16+TIMING_ADV_BIN_17+TIMING_ADV_BIN_18+TIMING_ADV_BIN_19+TIMING_ADV_BIN_20+ TIMING_ADV_BIN_21+

Page 50
Report Execution

dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l


dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l

Page 51
Report Execution

dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l


dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l
dv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + l

Page 52
Report Execution

BIN_20+ TIMING_ADV_BIN_21+TIMING_ADV_BIN_22+TIMING_ADV_BIN_23+TIMING_ADV_BIN_24+TIMING_ADV_BIN_25

Page 53
Report Execution

5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim


5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim

Page 54
Report Execution

5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim


5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim
5 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.tim

Page 55
Report Execution

V_BIN_24+TIMING_ADV_BIN_25+TIMING_ADV_BIN_26+TIMING_ADV_BIN_27+TIMING_ADV_BIN_28+TIMING_ADV_BIN_

Page 56
Report Execution

2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_


2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_

Page 57
Report Execution

2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_


2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_
2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_

Page 58
Report Execution

DV_BIN_28+TIMING_ADV_BIN_29+TIMING_ADV_BIN_30),0,NULL, (DECODE(TIMING_ADV_SET_INDEX, 1,(39*TIMING_A

Page 59
Report Execution

adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +


adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +

Page 60
Report Execution

adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +


adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +
adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 +

Page 61
Report Execution

V_SET_INDEX, 1,(39*TIMING_ADV_BIN_1+117*TIMING_ADV_BIN_2+195*TIMING_ADV_BIN_3+273*TIMING_ADV_BIN_4+

Page 62
Report Execution

25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim


25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim

Page 63
Report Execution

25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim


25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim
25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.tim

Page 64
Report Execution

N_3+273*TIMING_ADV_BIN_4+351*TIMING_ADV_BIN_5+429*TIMING_ADV_BIN_6+507*TIMING_ADV_BIN_7+585*TIMING

Page 65
Report Execution

c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_


c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12) / (lmac2.timin
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing

Page 66
Report Execution

c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing


c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30) / (lmac2.timin
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing
c2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30) / (lmac2.timin

Page 67
Report Execution

MING_ADV_BIN_7+585*TIMING_ADV_BIN_8+663*TIMING_ADV_BIN_9+741*TIMING_ADV_BIN_10+819*TIMING_ADV_BIN

Page 68
Report Execution

ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +


ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin
iming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin
iming_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23) / (lmac2.timing_adv_b
iming_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin
timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15) / (lmac2.timing_adv_bi
iming_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin
iming_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin
timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
iming_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin
iming_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin
timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12 + lmac2.timing_adv_bin_13) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_

Page 69
Report Execution

iming_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin


iming_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29) / (lmac2.timing_adv_b
timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin
iming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin
iming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
iming_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
ming_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 +
ming_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4
ming_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin
iming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
iming_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4

Page 70
Report Execution

_BIN_10+819*TIMING_ADV_BIN_11+897*TIMING_ADV_BIN_12+975*TIMING_ADV_BIN_13+1053*TIMING_ADV_BIN_14+1

Page 71
Report Execution

n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...


n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
dv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...
dv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...
v_bin_23) / (lmac2.timing_adv_bin_1 + lmac2.timing_ad...
v_bin_28 + lmac2.timing_adv_bin_29) / (lmac2.timing_a...
bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
v_bin_15) / (lmac2.timing_adv_bin_1 + lmac2.timing_ad...
v_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv...
v_bin_28 + lmac2.timing_adv_bin_29) / (lmac2.timing_a...
bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_b...
v_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv...
v_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv...
bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
v_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_...

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v_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv...


v_bin_29) / (lmac2.timing_adv_bin_1 + lmac2.timing_ad...
bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
dv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...
v_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv...
bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
dv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...
v_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv...
_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_b...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
n_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
dv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...
v_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv...
_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_b...

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Report Execution

3+1053*TIMING_ADV_BIN_14+1131*TIMING_ADV_BIN_15+1209*TIMING_ADV_BIN_16+1287*TIMING_ADV_BIN_17+1365*

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Report Execution

87*TIMING_ADV_BIN_17+1365*TIMING_ADV_BIN_18+1443*TIMING_ADV_BIN_19+1521*TIMING_...

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Report Execution

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