What

 EDA  Needs  to  Change  for  

2020  Success  

Jim  Hogan  and  Paul  McLellan  

November  2009  
 Paul  McLellan  

My  website:  www.greenfolder.com  

My  blog:  www.edn.com/blog/920000692.html  

Follow  me  on  TwiFer:  paulmclellan  

Email  me:  paul@greenfolder.com  

 Jim  Hogan  

Email  me:  jim@tela-­‐inc.com  

 The  Market  is  FragmenPng  

•  More  and  more  electronic  systems  in  lower  

and  lower  volumes  
•  AggregaPng  into  larger  and  larger  total  volume  
AdopPon  Ramps  are  Steep  
 COST  FOR  TYPICAL  65nm  DESIGN  

SW  is  increasing  the  Largest    single  

component  of  SoC  Design  Cost    

Source  IBS     IBS  

 $50M!  
But  over  50%  is  soZware  –  Where’s  the  EDA  opportunity?    
But  not  many  markets  
need  150-­‐200M  chips  
 Mismatch  

•  End-­‐product  markets  are  fragmenPng  

– Smaller  volumes  per  chip  

•  Design/mask  costs  exploding  

– Larger  volumes  per  chip  
 AggregaPon,  Re-­‐configurability    and  
Programmability  Fabrics  

•  FPGAs  
–  With  processors  

•  Programmable/Reconfigurable    SoCs  

•  Plaborms  
–  Mostly  wireless  
 FPGA  Market  Segments  
Quarter  ended  June  2009    
$M  Altera  and  Xilinx  Revenue  

Mature/Base      -­‐42%  Y-­‐T-­‐Y  

$186  
$256  
Mainstream      -­‐33%  Y-­‐T-­‐Y  
Mainstream  

Mature/Base   $194   New      +29%  Y-­‐T-­‐Y  

The  “New”  or  complex  CPU  based  segment  generates  40%  of  total  FPGA  
revenue  with  robust  growth.      

It  represents  approximately  12%  of  90,000  projected  total  design  starts.      

Nearly 700 Million PSoC® Units
Shipped by End of 2009
MILLIONS OF UNITS SHIPPED (CUMULATIVE)

14
The  System  Market  is  Moving  

EDA  will  need  to  follow…  

             SoZware  Signoff  
 EDA  Tool  Meta  Model  
SW  ApplicaEon    
Design  AbstracEon    

IntegraPon/ Simulate  
Measure   Model   OpPmize    
Analysis     Verify    
Complexity  
Accuracy  

Transistor  
Tool  Value  $    
 Transistor  Ecosystem  Example    
SW  ApplicaEon    
Design  AbstracEon    

IntegraPon/ Simulate  
Measure   Model   Analysis     OpPmize    
Verify    
Complexity  
Accuracy  

Test/Measurement  
Foundries:   Layout/Electrical     Simulators:   CiraNova  
and   Cockpit   Solido  
CharacterizaEon:   TSMC   SNPS  –HSPICE    
UMC   CDN  _  Virtuoso   CDNS  –Spectre  
Agilent  
Global    Foundries   SNPS  –       Mentor  –  ELDO  
NaPonal   Samsung   Custom  Designer   BDA  -­‐FASTSpice  
Instruments   Intel   SpringsoZ  -­‐    Laker   Agilent  –  GoldenGate  
Accelecon    

Transistor  
Tool  Value  $    
 Tool  Value  ProposiPons  

BeRer  –  opPmize  for  cost,  performance  or  power  

Faster  –  faster  total  run  Pme,  but  don’t  bet  against  Moore’s  law  

Cheaper  –  the  least  expensive  choice  

For  a  tool  to  be  successful  it  must  have  at  least  two  out  of  three  value  
ProposiPons,  for  example  :  

 Most  likely  is  all  three  –  BeRer,  Faster,  Cheaper  –  hard  to  beat  

 SPll  got  a  chance  with  BeRer  and  Faster  

 Just  ugly  is  Cheaper