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Contents Pag

Cyclical Program Execution …........................................................................................................... 2


Process Images .................................................................................................................................... 3
Program Structure ................................................................................................................................ 4
Types of Program Blocks ................................................................................................................... 5
Normally Open and Normally Closed Contacts. Sensors and Symbols............................................... 6
Exercise .............................................................................................................................................. 7
Addressing of S7-300 Modules ………................................................................................................ 8
DI/DO Addressing in Multi-Tier Configurations ................................................................................. 9
Binary Logic Operations: AND, OR ................................................................................................... 10
Binary Logic Operations: Exclusive OR (XOR) ................................................................................ 11
Result of Logic Operation, First Check. Examples…............................................................................. 12
Assignment, Setting, Resetting............................................................................................................. 13
Setting / Resetting a Flip Flop ........................................................................................................... 14
Connector ............................................................................................................................................. 15
Instructions that Affect the RLO …………............................................................................................ 16
Master Control Relay Function ............................................................................................................ 17
Unconditional Jump (Independent of RLO) ........................................................................................... 18
Conditional Jump (Dependent on RLO) .............................................................................................. 19
RLO Edge Detection …........................................................................................................... ........... 20
Signal Edge Detection ….................................................................................................................... 21
Exercise: Program for a Bottling Plant (Mode Selection) …………. ................................................... 22

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Starting The CPU carries out a complete restart (with OB100) when switching on or when
switching from STOP --> RUN. During a complete restart, the operating system
deletes the non-retentive bit memories, timers and counters, deletes the interrupt
stack and block stack, resets all stored hardware interrupts and diagnostic
interrupts and starts the scan cycle monitoring time.

Scan Cycle The cyclical operation of the CPU consists of three main sections, as shown in the
diagram above:

• The CPU checks the status of the input signals and updates the process-
image input table.

• It executes the user program with the respective instructions.

• It writes the values from the process-image output table into the output
modules.

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Introduction The CPU checks the status of the inputs and outputs in every cycle. There are
specific memory areas in which the module‘s binary data are stored: PII and PIQ.
The program accesses these registers during processing.

PII The process-image input table is found in the CPU‘s memory area. The signal state
of all inputs is stored there.

PIQ Th process-image
The i output
t t table
t bl contains
t i th
the output
t t values
l that
th t resultlt from
f the
th
program execution. These are sent to the actual outputs (Q) at the end of the cycle.

User Program When you check inputs in the user program with, for example, A I 2.0, the last state
from the PII is evaluated. This guarantees that the same signal state is always
delivered when there is multiple checking of the input within one cycle.

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Linear Program The entire program is found in one continuous program block.
This model resembles a hard-wired relay control, that was replaced by a
programmable logic controller. The CPU processes the individual instructions one
after the other.

Partitioned The program is divided into blocks, whereby every block only contains the
Program program for solving a partial task. Further partitioning through networks is possible
within a block. You can generate network templates for networks of the same type.
The organization
Th i ti blblock
k OB 1 contains
t i iinstructions
t ti th
thatt callll th
the other
th blocks
bl k iin a
defined sequence.

Structured A structured program contains blocks with parameters, so-called parameter


Program assignable blocks. These blocks are designed in such a way that they can be used
universally.
When a parameter assignable block is called, it is given current parameters (the
p
exact addresses of inputs and outputs
p as well as pparameter values).
)
Example:
• A "pump block" contains instructions for the control of a pump.
• The program blocks, that are responsible for the control of special pumps,
call the "pump block" and give it information about which pump is to be
controlled with which parameters.
• When the "pump block" has completed the execution of its instructions, the
program returns to the calling block (e.g. OB 1), which continues with the
processing of its instructions.

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User Blocks User blocks contain the program code and the user program data.
In a structured user program, some blocks are called and processed cyclically,
others only as required.

System Blocks System blocks are pre-defined functions or function blocks that are integrated in the
CPU‘s operating system. These blocks do not occupy additional space in the user
memory.
System blocks are called from the user program. These blocks have the same
interface the same identifier and the same number throughout the entire system
interface, system.
The user program is thus easily transportable between various CPUs or
programmable controllers.

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Process The use of normally open or normally closed contacts for the sensors in a controlled
process depends
d d on th
the safety
f t regulations
l ti ffor the
th process.
Normally closed contacts are always used for limit switches and safety switches, so
that dangerous conditions do not arise if a wire break occurs in the sensor circuit.
Normally closed contacts are also used for switching off machinery for the same
reason.

Symbols In LAD, a symbol with the name "NO contact" is used for checking for signal state
"1" and a symbol with the name "NC contact" to check for signal state "0".
It makes no difference whether the process signal “1”
1 is supplied by an activated
NO contact or a non-activated NC contact.

Example The result of check for the "NO contact" symbol is "1" if an NC contact in the
machine is not activated.

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Exercise Complete the programs above to obtain the following functionality: When switch S1
i activated
is ti t d and
d switch
it h S2 iis nott activated,
ti t d ththe lilight
ht should
h ld bbe ON iin allll th
three cases.

Note ! The terms "NO contact" and "NC contact" have different meanings depending on
whether they are used in the process hardware context or as symbols in the
software.

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Slot Numbers The slot numbers in the rack of an S7-300 simplify addressing within the
S7 300 environment.
S7-300 i t Th
The fifirstt address
dd on a module
d l iis d
determined
t i db by th
the position
iti off
the module in the rack.

Slot 1 Power supply. This is the first slot by default.


A power supply module is not absolutely essential. An S7-300 can also be supplied
with 24V direct.

Slot 2 Slot for the CPU.

Slot 3 Logically reserved for an interface module (IM) for multi-tier configurations using
expansion racks. Even if no IM is installed, it must be included for addressing
purposes.
You can physically reserve the slot (e.g. for installation of an IM at a later date) by
inserting a DM370 dummy module.

Slots 4-11 Slot 4 is the first slot that can be used for I/O modules, communications processors
((CP)) or function modules ((FM). )
Addressing examples:
• A DI module in slot 4 begins with the byte address 0 .
• The top LED of a DO module in slot 6 is called Q8.0 .

Note 4 byte addresses are reserved for each slot. When using 16-channel DI/DO
modules, two byte addresses are lost in every slot!

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Multi-Tier The slots also have fixed addresses in a multi-tier configuration.
C fi
Configurations
ti
Examples:
• Q7.7 is the last bit of a 32-channel DO module plugged into slot 5 of rack 0.
• IB105 is the second byte of a DI module in slot 6 of rack 3.
• QW60 is the first 2 bytes of a DO module in slot 11 of rack 1.
• ID80 is all 4 bytes of a 32-channel DI module in slot 8 in rack 2.

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Logic Tables

AND I 0.0 I 0.1 Q 8.0


0 0
0 1
1 0
1 1

OR I 0.2 I 0.3 Q 8.2


0 0
0 1
1 0
1 1

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L i Table
Logic T bl

XOR I 0.4 I 0.5 Q 8.0


0 0
0 1
1 0
1 1

Rule The following rule is valid for the logic operation of two addresses after XOR:
the output has signal state "1", when one and only one of the two checks is
fulfilled ("one and only one of two" ).

Attention! This rule cannot be generalized to "one and only one of n" ! for the logic
operation of several addresses after XOR !!
As of the third XOR instruction, the old RLO is gated with the new result of
check after XOR.

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Signal State A logic operation is made up of a series of instructions to check the states of signals
(i
(inputs
t (I),
(I) outputs
t t (Q),
(Q) bit memories
i (M)
(M), titimers (T)
(T), counters
t (C) or d
data
t bit
bits (D) )
and instructions to set Q,M,T,C or D.

Result of Check When the program is executed, the result of check is obtained. If the check
condition is fulfilled, the result of check is “1”. If it is not fulfilled, the result of check is
“0”.

First Check The result of the first check is stored as the result of logic operation (RLO).

Result of Logic When the next check instructions are executed, the result of logic operation is
Operation gated with the result of check and a new RLO is obtained.
When the last check instruction in a logic operation has been executed, the RLO
remains the same. A number of instructions using the same RLO can follow.

Note The result of the first check is stored without being subjected to a logic operation. It
therefore makes no difference whether you program the first check with an AND or
an OR instruction in STL. To enable your program to be converted into one of the
other
th programming i llanguages, you should,
h ld hhowever, always
l program using
i ththe
correct instruction.

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Assignment An assignment passes the RLO on to the specified address (Q, M, D). When the
RLO changes, the signal state of that address also changes.

Set If RLO= "1", the specified address is set to signal state "1" and remains set until it is
reset by another instruction.

Reset If RLO= "1", the specified address is reset to signal state "0" and remains in this
state until it is set again by another instruction.

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Flip Flop A flip flop has a Set input and a Reset input. The memory bit is set or reset,
depending on which input has an RLO=1.
If there is an RLO=1 at both inputs at the same time, the priority must be
determined.

Priority In LAD and FBD there are different symbols for Dominant Set and Dominant Reset
functions.
In STL, the instruction that was programmed last has priority.

Note If an output is set with a Set instruction, it is reset on a complete restart of the CPU.
If M 0.0 in the example above has been declared retentive, it will remain in the set
state after a complete restart of the CPU and the reset output Q 9.3 will be be
assigned the set state again.

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Connector A connector is an intermediate assignment element that stores the current RLO at a
specified
ifi d address.
dd
When connected in series with other elements, the "Connector" instruction is
inserted in the same way as a contact.
A connector must never:
• be connected to a power rail
• directly follow a branch
• be used at the end of a branch.
You can program a negated connector with the "NOT"
NOT element.
element

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NOT The NOT instruction inverts the RLO.

CLR The CLEAR instruction changes the RLO to "0" (only available in STL at present!).

SET The SET instruction changes the RLO to "1" (only available in STL at present!).

SAVE The SAVE instruction saves the RLO as "BR" in a register (status word).

BR The statement “A BR" can be used to recheck the saved RLO.

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MCR The Master Control Relay is a logical master switch for activating and deactivating
power flow.
fl A
An iinterrupted
t t d path
th represents
t a sequence that
th t writes
it a zero value
l in i
place of a calculated value or a sequence that does not change the existing memory
value.
Examples If the MCR condition is not fulfilled:
• "0" is assigned via the output coils
• the "Set Coil" and "Reset Coil" instructions do not change the existing value
• the “MOVE” instruction transfers the value zero to the specified destination.

MCRA The MCRA instruction activates the Master Control Relay function.

MCR( “MCR(“ opens an MCR area and triggers an instruction that shifts the RLO to
(for STL) the MCR stack. The stack can have up to eight entries. This means that up to eight
individual control areas can be nested between the “MCRA” and “MCRD”
instructions.

)MCR The “)MCR“ instruction marks the end of an MCR area.


(for STL)

MCRD The "Deactivate Master Control Relay” instruction deactivates the MCR function. No
more MCR areas can be opened until another “MCRA” instruction is given.

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Jump Instruction In LAD/FBD, the label is entered as an identifier above the coil symbol or
assignment symbol. In STL it comes after the Jump instruction.
The label can have up to four characters, the first of which must be a letter or the “_”
character.
The label marks the point where execution of the program is to continue. Any
instructions or networks between the jump instruction and the label are not
executed.
Jumps can be made both forwards and backwards.
Th jjump iinstruction
The t ti and d th
the jjump d
destination
ti ti mustt both
b th be
b in
i the
th same block
bl k ((max.
jump length = 64kbyte). The jump destination must only be present once in the
block.
Jump instructions can be used in FBs, FCs and OBs.

Inserting In LAD aund FBD, you use the Program Elements browser to insert a label:
a Label Program Elements -> Logic Control / Jump -> Label.

In STL,
STL you enter the label to the left of the statement,
statement from which program
exeuction is to continue.

JMP An unconditional jump instruction causes a program jump to a label regardless of


the RLO.

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JC The conditional jump “JC” is only executed if the RLO is “1”.
If the
th RLO is
i “0”,
“0” th
the jjump iis nott executed,
t d th
the RLO iis sett tto “1” and
d program
execution continues with the next instruction.

JCN The conditional jump “JCN” is only executed if the RLO is "0".
If the RLO is "1", the jump is not executed and program execution continues with
the next instruction.

Note STL provides additional jump operations, which are discussed in another
programming
p g g course.

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RLO Edge An "RLO edge" is when the result of a logic operation changes.

Positive Edge When the RLO changes from “0” to “1”, the "FP" check instruction results in signal
state "1" (e.g. at M 8.0) for one cycle.
To enable the system to detect the edge change, the RLO must also be saved in an
FP bit memory, or data bit (e.g. M 1.0).

Negative Edge When the RLO changes from “1” to “0”, the "FN" check instruction results in signal
state “1”
1 (e.g.
(e g at M 8
8.1)
1) for one cycle
cycle.
To enable the system to detect the edge change, the RLO must also be saved in an
FN bit memory, or data bit (e.g. M 1.1).

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Signal Edge A "signal edge" is when a signal changes its state.

Example Input I 1.0 acts as a static Enable. Input I 1.1 is to be monitored dynamically and
every signal change is to be detected.

Positive Edge When the signal state at I 1.1 changes from “0” to “1”, the "POS" check instruction
results in signal state "1" at output Q for one cycle, provided input
I 1.0 also has signal state "1" (as in the example above).
To enable the system to detect the edge change, the signal state of I 1.1 must also
be saved in an MM_BIT
BIT (bit memory or data bit) (e
(e.g.
g M1 1.0).
0)

Negative Edge When the signal state at I 1.1 changes from “1” to “0” , the "NEG" check instruction
results in signal state "1" at output Q for one cycle, provided input
I 1.0 has signal state "1" (as in the example above).
To enable the system to detect the edge change, the signal state of I 1.1 must also
be saved in an M_BIT (bit memory or data bit) (e.g. M 1.1).

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Task Write a mode section of a program for a bottling plant to meet the following
specifications:
ifi ti
• Input I 0.0 (momentary-contact switch with NO function) switches the plant
ON.
• Input I 0.1 (momentary-contact switch with NC function) switches the plant
OFF.
• When the plant is ON, the indicator at output Q 8.1 (Q 4.1) is lit.
• When the plant is ON, the operating mode can be selected:
- Manual mode is selected when I 0.4=0 and automatic mode when
I 0.4=1.
04 1
- The selected mode is adopted with a pulse at input I 0.5 .
• The indicators for the selected mode are as follows:
Manual = Q 8.2 (Q 4.2), Automatic = Q 8.3 (Q 4.3).
• When the mode is changed or the plant is switched off, the mode previously
selected must be deselected.
• In manual mode, the conveyor can be jogged forwards with the momentary-
contact switch I 0.2 (Q 20.5 / Q 8.5) and backwards with I 0.3
(Q 2020.6
6/Q8 8.6).
6)

What to Do 1. Draft out the program for controlling the operating modes.
Use the I/O addresses and field devices shown in the diagram.
2. Create an S7 program with the name "FILL" in the project "My Project".
3. Write the mode section of the program for the bottling plant in block FC 15.
4. Open (off-line) the OB1 and enter a call to FC15
(in STL with the statement “CALL FC 15”).
5 Save
5. S your program, ddownload
l d it and
d ttestt it on th
the ttraining
i i unit.
it

Result It should work.

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