UTS Solution ELS3202 Sistem Mikroprosesor

1. Difference between Microprocessor and Microcontroller

Microprocessor Microcontroller
CPU is standalone. Memory, timer and I/O are A microcontroller already contains all
separate. It cannot operate standalone. components which allow it to operate
standalone
Communication via data bus through external Directly interface with its environments since it’s
devices, peripheral interfaces are added as already have all components that are needed
external devices
Not assigned to ado a particular task – general Assigned to do a particular task – single purpose
purpose

A microcontroller exists because its simplicity and its specific task that can be assigned to. A
complete components to do a particular task is an advantage that microprocessor do not have.
Microprocessor cannot operate stand alone makes it more expensive.

2. Microcontroller architecture
a. Microcontroller components
- Processor Core
- Memory (SRAM, EEPROM)
- Analog/Digital Interfaces Module
- Interrupt Controller
- Timer/Counter Module
b. Difference between EEPROM and Flash-EEPROM

EEPROM Flash-EEPROM
Usually used for data storage Usually used for program
Possible to erase single byte Not possible to erase single byte, erase
completely.
More expensive, write/lifecycle approximately Cheaper because usually you will not erase
100000 cycles program more than 100000 times

3. A task requires 18 inputs, 15 outputs, and 2 analog inputs; 512 bytes to store data
18 inputs and 15 outputs = 33 I/O  at least 33 I/O pins
2 analog inputs  at least 2 analog inputs
512 bytes data storage  at least 512 bytes EEPROM

From table 1
ATmega128 – 4096 bytes EEPROM, 53 I/O pins, 8 A/D channels
ATmega169 – 512 bytes EEPROM, 53 I/O pins, 8 A/D channels
4. Bus Diagram ATmega815
a. Function of signal
- AD7:0 – AVR Address/Data register 0 – 7
- ALE : Address Latch Enable
- A15:8 => AVR address register 8 – 15
- RD : Read enable (control bus read)
- WR : Write enable (control bus write)
- D[7:0] : Memory data register 0 – 7
- A[7:0] : Memory address register 0 – 7
b. Latch role: buffer to isolate system address bus and local address bus
Output Q follows input D where G is enable. Vice versa.

5. Address Decoder