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A scalable, broadband, and physics-based compact model for on-chip spiral inductors with rectangular outline shape is
demonstrated for the first time in this paper. A simple dc inductance model is developed based on the current sheet approximation.
The reduction in inductance due to the flow of eddy current in a back metal plate is considered using the method of images. A three-
ladder network is shown to be sufficient to accurately model skin effect caused due to the magnetic field setup at high frequencies.
Geometry-dependent expression suitable for rectangular cross-sectional metal strips is presented to predict the proximity effect.
Physics-based expression for the substrate capacitance is derived. The proposed model is also shown to have a good correlation in
the presence of a patterned ground shield. The proposed model is verified across CMOS process parameters that affect the inductor
performance, such as metal thickness, substrate resistivity, and substrate thickness. Furthermore, model accuracy is also validated
across design parameters such as spiral width, spacing between turns, number of turns, and diameter. The model is shown to have
a good agreement with both EM simulations and measurements.
Index Terms— CMOS, patterned ground shield (PGS), proximity effect, quality factor, radio frequency integrated circuits,
rectangular spiral, skin effect, spiral inductor.
Fig. 1. (a) Top view of a rectangular spiral inductor and (b) corresponding
view using current sheet approximation.
Fig. 3. Image inductor at a distance 2(tox + tsub ) from the real inductor.
The arrow shows the direction of current flow. tox and tsub are the thickness
of the oxide and substrate, respectively.
SATHYA SREE et al.: SCALABLE, BROADBAND, AND PHYSICS-BASED MODEL FOR ON-CHIP RECTANGULAR SPIRAL INDUCTORS 3
TABLE I
D IMENSIONS FOR THE I NVESTIGATED T EST S TRUCTURES
resistance and inductance in the ladder circuit change in a 1 −1 2 (0.2235 (w + t)) 2
constant ratio, such that [11] d ≈ sin 1− . (12)
π w+s
Ri L1 To show the accuracy of the three-ladder circuit, the resistance
Ri+1 = , i = 1, 2 and L 2 = (8)
R L of all the layouts listed in Table I is plotted in Fig. 6. It proves
that the three-ladder circuit captures the resistive nature of
where the constants R (> 1) and L (< 1) for a three-ladder
the spiral inductor accurately over a wide range of frequency.
circuit have to be determined. R is obtained by solving
To ensure scalability, our model is tested for various metal
widths, spacings, and thicknesses. Fig. 7 shows that our model
R1
R + R + 1 −
2
=0 (9) predicts skin and proximity effects accurately for various width
Rdc
and spacing.
with Rdc as the dc resistance of the metal strip and R1 as Increasing the spiral thickness reduces the dc resistance,
the resistance at the maximum operating frequency. Equating thereby increasing the quality factor (Q) at lower frequencies.
the low-frequency inductance of the circuit to the internal However, due to accentuated proximity effect losses, resistance
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ρ ⎢ √ ⎜ b− b2 −4a 2
as shown in Fig. 8. = ⎣− 2a ⎝ √
πsub b − b2 − 4a 2
C. Oxide and Substrate Elements √ √ ⎞ ⎤2tt
tanh−1 √ 2√b+z
2
Fig. 9 shows the equivalent circuit of the on-chip spiral b+ b −4a ⎟
2 2
−1 a ⎥
inductor including the substrate effects. The displacement + √ ⎠ +z tan √ ⎦
2
b + b − 4a
2 2 z b+z
current in the oxide is modeled using Cox and C p is the 0
underpass capacitance. Cox and C p can be calculated using the (16)
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SATHYA SREE et al.: SCALABLE, BROADBAND, AND PHYSICS-BASED MODEL FOR ON-CHIP RECTANGULAR SPIRAL INDUCTORS 5
Fig. 10. Variation in quality factor for layouts as displayed in Table I. Fig. 12. Variation in quality factor for layout #4 with and without PGS.
TABLE II
VALID R ANGE OF G EOMETRIC AND P ROCESS PARAMETERS
Fig. 11. Equivalent circuit of on-chip inductor with PGS. Cild’ is the
capacitance between the underpass and the shield. The dashed rectangular
box shows the modeling of skin and proximity effect as shown in Fig. 5.
Q ρ Dout,x Dout,y
C1 = = (17) This can be modeled by using a resistance, Rpgs = ρs l/wpgs ,
V1 V1 where ρs is the sheet resistance of the PGS and wpgs is the
yielding width of the fingers in PGS. Fig. 12 shows the comparison
of our model (Fig. 11) for PGS with EM simulated data.
Csub = C1 − C2 (18) It also compares the quality factor for layout #4 with substrate
where C2 is calculated using the above-mentioned procedure resistivity of 1000 and 20 ·cm without PGS. The broadband
for the inner rectangular plate shown in Fig. 3 with dimensions nature of the quality factor is accurately modeled. Use of
Din,x and Din,y . Finally, Rsub can be calculated using the PGS increases the capacitive coupling which reduces the
relation self-resonant frequency (SRF). Our model accurately predicts
sub the SRF.
Rsub = . (19)
σsub Csub
III. C OMPARISON W ITH M EASUREMENTS
Fig. 10 shows the variation of quality factor for all the layouts
listed in Table I. A good agreement is observed between the The process and geometric parameters over which our
model and EM simulated data. model is valid are listed in Table II. To validate the accuracy
of our model, we fabricated a set of inductors as mentioned
in Table I. The chosen test structures have a wide range of
D. Patterned Ground Shield inductance densities and also have low-to-high L dc values
Fig. 11 shows the equivalent circuit of the on-chip induc- at different frequency bands. A 0.13 μm BiCMOS technol-
tor using PGS [19], [20]. The capacitance between the top ogy [21], [22] using a single thick metal is used for hardware
metal and the shield can be obtained using [18] with length validation. The top metal is 4 μm thick aluminum and the
as n cr wpgs , where n cr is the number of crossovers and wpgs is bottom metal (used for underpass connection) is 1.4 μm thick
the width of the fingers in PGS. The displacement current aluminum with a 4 μm silicon dioxide inter-layer dielectric.
flows through a smaller distance before it reaches the ground. The bottom metal is almost 6 μm away from the substrate.
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Fig. 14. Comparison of measured, EM simulated, and model data for layout #2. (a) Inductance. (b) Resistance. (c) Quality factor.
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