Power Semiconductor Devices

EE8552-Power Electronics Department of EEE 2019-2020
UNIT - I
POWER SEMICONDUCTOR DEVICES
CONSTRUCTION, VI & SWITCHING CHARACTERISTICS OF BI-POLAR
JUNCTION TRANSISTOR.
A Bi-Polar Junction Transistor is a 3 layer, 3 terminals device. The 3 terminals are base,
emitter and collector. It has 2 junctions’ collector-base junction (CB) and emitter-base
junction (EB). Transistors are of 2 types, NPN and PNP transistors.
The different configurations are common base, common collector and common emitter.
Common emitter configuration is generally used in switching applications.
IB
IC
R C V CE 1 V CE 2
R B V >V
CE2 CE1
V V CC
CE
IB
V CC V BE
IE
V BE
Fig: NPN Transistor Fig: Input Characteristic
IC
IB 1
IB 2 I B 1> I B 2> I B 3
IB 3
Fig: Output / Collector V CE
Characteristics
Transistors can be operated in 3 regions i.e., cut-off, active and saturation.
In the cut-of region transistor is OFF, both junctions (EB and CB) are reverse biased. In the
cut-off state the transistor acts as an open switch between the collector and emitter.
In the active region, transistor acts as an amplifier (CB junction is reverse biased and EB
junction is forward biased),
In saturation region the transistor acts as a closed switch and both the junctions CB and EB
are forward biased.
SWITCHING CHARACTERISTICS
An important application of transistor is in switching circuits. When transistor is used as a
switch it is operated either in cut-off state or in saturation state. When the transistor is driven
into the cut-off state it operates in the non-conducting state. When the transistor is operated in
saturation state it is in the conduction state.
Thus the non-conduction state is operation in the cut-off region while the conducting state is
operation in the saturation region.
1
Fig: Switching Transistor in CE Configuration
As the base voltage VB rises from 0 to VB, the base current rises to IB, but the collector
current does not rise immediately. Collector current will begin to increase only when the base
emitter junction is forward biased and VBE > 0.6V. The collector current IC will gradually
increase towards saturation level I C ( sat ) . The time required for the collector current to rise to
10% of its final value is called delay time td . The time taken by the collector current to rise
from 10% to 90% of its final value is called rise time tr . Turn on times is sum of td and tr .
ton = td + tr
The turn-on time depends on
 Transistor junction capacitances which prevent the transistors voltages from changing
instantaneously.
 Time required for emitter current to diffuse across the base region into the collector
region once the base emitter junction is forward biased. The turn on time ton ranges
from 10 to 300 ns. Base current is normally more than the minimum required to
saturate the transistor. As a result excess minority carrier charge is stored in the base
region.
When the input voltage is reversed from VB1 to -VB 2 the base current also abruptly changes
but the collector current remains constant for a short time interval t S called the storage time.
The reverse base current helps to discharge the minority charge carries in the base region and
to remove the excess stored charge form the base region. Once the excess stored charge is
removed the baser region the base current begins to fall towards zero. The fall-time t f is the
time taken for the collector current to fall from 90% to 10% of I C ( sat ) . The turn off time toff
is the sum of storage time and the fall time. toff = t s + t f
2
V B 1
-V B 2
td = T u rn o n d e la y tim e .
tr = R is e tim e .
ts = S to r a g e tim e .
IB
tf = F a ll T im e .
t o n = ( t d + t r)
IB1
t o f f = ( t s + t f)
-IB 2
IC
I C (sat)
0 .9 I C
tr
0 .1 I C
t
ts tf
td
Fig: Switching Times of Bipolar Junction Transistor
CONSTRUCTION, OPERATION & STATIC CHARACTERISTICS OF TRIAC
A triac is a three terminal bi-directional switching thyristor device. It can conduct in both
directions when it is triggered into the conduction state. The triac is equivalent to two SCRs
connected in anti-parallel with a common gate. Figure below shows the triac structure. It
consists of three terminals viz., MT2 , MT1 and gate G.
M T 1
G N 2
M T 2
P 2
N 3
P 2
N 1
N 1
P 1 G M T 1
P 1
N 4
M T 2
Fig. : Triac Structure Fig. : Triac Symbol
3
The gate terminal G is near the MT1 terminal. Figure above shows the triac symbol. MT1 is
the reference terminal to obtain the characteristics of the triac. A triac can be operated in four
different modes depending upon the polarity of the voltage on the terminal MT2 with respect
to MT1 and based on the gate current polarity.
The characteristics of a triac is similar to that of an SCR, both in blocking and conducting
states. A SCR can conduct in only one direction whereas triac can conduct in both directions.
TRIGGERING MODES OF TRIAC

MODE 1 : MT2 positive, Positive gate current ( I + mode of operation)
When MT2 and gate current are positive with respect to MT1, the gate current flows through
P2-N2 junction as shown in figure below. The junction P 1-N1 and P2-N2 are forward biased
but junction N1-P2 is reverse biased. When sufficient number of charge carriers are injected
in P2 layer by the gate current the junction N1-P2 breakdown and triac starts conducting
through P1N1P2N2 layers. Once triac starts conducting the current increases and its V-I
characteristics is similar to that of thyristor. Triac in this mode operates in the first-quadrant.
M T 2 (+ )
P 1
N 1
P
Ig 2
N 2
M T 1 (-)
G
V
(+ )
Ig
MODE 2 : MT2 positive, Negative gate current ( I - mode of operation)
M T 2 (+ )
P 1
In itia l F in a l
N
c o n d u c tio n 1 c o n d u c tio n
P 2
N 3 N 2
M T 1 (-)
G
V
Ig
When MT2 is positive and gate G is negative with respect to MT 1 the gate current flows
through P2-N3 junction as shown in figure above. The junction P1-N1 and P2-N3 are
4
forward biased but junction N1-P2 is reverse biased. Hence, the triac initially starts
conducting through P1N1P2N3 layers. As a result the potential of layer between P2-N3 rises
towards the potential of MT2. Thus, a potential gradient exists across the layer P2 with left
hand region at a higher potential than the right hand region. This results in a current flow in
P2 layer from left to right, forward biasing the P2N2 junction. Now the right hand portion P1-
N1 - P2-N2 starts conducting. The device operates in first quadrant. When compared to Mode
1, triac with MT2 positive and negative gate current is less sensitive and therefore requires
higher gate current for triggering.
MODE 3 : MT2 negative, Positive gate current ( III + mode of operation)
When MT2 is negative and gate is positive with respect to MT 1 junction P2N2 is forward
biased and junction P1-N1 is reverse biased. N2 layer injects electrons into P2 layer as shown
by arrows in figure below. This causes an increase in current flow through junction P 2-N1.
Resulting in breakdown of reverse biased junction N1-P1. Now the device conducts through
layers P2N1P1N4 and the current starts increasing, which is limited by an external load.
M T 2 (- )
N 4
P 1
N 1
P 2
N 2
G M T 1 (+ )
(+ )
Ig
The device operates in third quadrant in this mode. Triac in this mode is less sensitive and
requires higher gate current for triggering.
MODE 4 : MT2 negative, Negative gate current ( III - mode of operation)
M T 2 (-)
N 4
P 1
N 1
P 2
N 3
G M T 1 (+ )
(+ )
Ig
In this mode both MT2 and gate G are negative with respect to MT 1, the gate current flows
through P2N3 junction as shown in figure above. Layer N3 injects electrons as shown by
arrows into P2 layer. This results in increase in current flow across P1N1 and the device will
5
turn ON due to increased current in layer N1. The current flows through layers P2N1P1N4.
Triac is more sensitive in this mode compared to turn ON with positive gate current. (Mode
3).
Triac sensitivity is greatest in the first quadrant when turned ON with positive gate current
and also in third quadrant when turned ON with negative gate current. when MT2 is positive
with respect to MT1 it is recommended to turn on the triac by a positive gate current. When
MT2 is negative with respect to MT1 it is recommended to turn on the triac by negative gate
current. Therefore Mode 1 and Mode 4 are the preferred modes of operation of a triac ( I +
mode and III - mode of operation are normally used).
TRIAC CHARACTERISTICS
Figure below shows the circuit to obtain the characteristics of a triac. To obtain the
characteristics in the third quadrant the supply to gate and between MT2 and MT1 are
reversed.
R L I
- +
A
M T 2
R g
+ +
+ - G
A M T V V
1 s
-
+ -
V gg
-
Figure below shows the V-I Characteristics of a triac. Triac is a bidirectional switching
device. Hence its characteristics are identical in the first and third quadrant. When gate
current is increased the break over voltage decreases.
V B 01, V B 01
M T 2(+ ) - B re a k o v e r v o lta g e s
G (+ ) Ig2 > Ig21
 Ig2
I Ig1
V B 02
V
 V V B 01
M T 2(- )
G (-)
Fig.: Triac Characteristic

Triac is widely used to control the speed of single phase induction motors. It is also used in
domestic lamp dimmers and heat control circuits, and full wave AC voltage controllers.
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CONSTRUCTION & OPERATION OF POWER MOSFET
Power MOSFET is a metal oxide semiconductor field effect transistor. It is a voltage
controlled device requiring a small input gate voltage. It has high input impedance. MOSFET
is operated in two states viz., ON STATE and OFF STATE. Switching speed of MOSFET is
very high. Switching time is of the order of nanoseconds.
MOSFETs are of two types
 Depletion MOSFETs
 Enhancement MOSFETs.
MOSFET is a three terminal device. The three terminals are gate (G), drain (D) and source
(S).
DEPLETION MOSFET
Depletion type MOSFET can be either a n-channel or p-channel depletion type MOSFET.
A depletion type n-channel MOSFET consists of a p-type silicon substrate with two highly
doped n+ silicon for low resistance connections. A n-channel is diffused between drain and
source. Figure below shows a n-channel depletion type MOSFET. Gate is isolated from the
channel by a thin silicon dioxide layer.
M e ta l
+
D n D
p -ty p e
G n
s u b s tr a te G
S n
+ S
C hannel
O x id e
Structure Symbol
Fig. : n-channel depletion type MOSFET
Gate to source voltage (VGS) can be either positive or negative. If V GS is negative, electrons
present in the n-channel are repelled leaving positive ions. This creates a depletion.
+
M e ta l
D p
D
n -ty p e
G p
s u b s tr a te G
S p
+ S
C hannel
O x id e
Structure Symbol
Fig. : P-channel depletion type MOSFET
7
Figure above shows a p-channel depletion type MOSFET. A P-channel depletion type
MOSFET consists of a n-type substrate into which highly doped p-regions and a P-channel
are diffused. The two P+ regions act as drain and source P-channel operation is same except
that the polarities of voltages are opposite to that of n-channel.
ENHANCEMENT MOSFET
Enhancement type MOSFET has no physical channel. Enhancement type MOSFET can be
either a n-channel or p-channel enhancement type MOSFET.
M e ta l
+
D n D
p -ty p e
G
s u b s tr a te G
S n
+ S
O x id e
Structure Symbol
Fig. : n-channel enhancement type MOSFET
Figure above shows a n-channel enhancement type MOSFET. The P-substrate extends upto
the silicon dioxide layer. The two highly doped n regions act as drain and source.
When gate is positive (VGS) free electrons are attracted from P-substrate and they collect
near the oxide layer. When gate to source voltage, V GS becomes greater than or equal to a
value called threshold voltage (VT). Sufficient numbers of electrons are accumulated to form
a virtual n-channel and current flows from drain to source.
Figure below shows a p-channel enhancement type of MOSFET. The n-substrate extends
upto the silicon dioxide layer. The two highly doped P regions act as drain and source. For p-
channel the polarities of voltages are opposite to that of n-channel.
+
M e ta l
D p
D
n -ty p e
G
s u b s tr a te G
S p
+ S
O x id e
Structure Symbol
Fig. : P-channel enhancement type MOSFET.
8
VI CHARACTERISTICS OF MOSFET
Depletion MOSFET
Figure below shows n-channel depletion type MOSFET with gate positive with respect to
source. I D , VDS and VGS are drain current, drain source voltage and gate-source voltage. A
plot of variation of I D with VDS for a given value of VGS gives the Drain characteristics or
Output characteristics.
D ID
G
V D S
+ +
V G S S
- -
Fig: n-channel Depletion MOSFET

n-channel Depletion type MOSFET
VGS & VDS are positive. I D is positive for n channel MOSFET . VGS is negative for depletion
mode. VGS is positive for enhancement mode.
Figure below shows the drain characteristic. MOSFET can be operated in three regions
 Cut-off region,
 Saturation region (pinch-off region) and
 Linear region.
In the linear region I D varies linearly with VDS . i.e., increases with increase in VDS . Power
MOSFETs are operated in the linear region for switching actions. In saturation region I D
almost remains constant for any increase in VDS .
L in e a r S a tu ra tio n
re g io n re g io n
V G S3
ID V G S2
V G S1
V D S
Fig.: Drain Characteristic
9
Figure below shows the transfer characteristic. Transfer characteristic gives the variation of
I D with VGS for a given value of VDS . I DSS is the drain current with shorted gate. As curve
extends on both sides VGS can be negative as well as positive.
ID SS
ID
V G S(O F F )
V G S
Fig.: Transfer characteristic

Enhancement MOSFET
D ID
G
V D S
+ +
V G S S
- -
Fig: n-channel Enhancement MOSFET

Enhancement type MOSFET
VGS is positive for a n-channel enhancement MOSFET. VDS & I D are also positive for n
channel enhancement MOSFET
Figure above shows circuit to obtain characteristic of n channel enhancement type MOSFET.
Figure below shows the drain characteristic. Drain characteristic gives the variation of I D
with VDS for a given value of VGS .
ID
V T
V G S
VT = VGS ( TH ) = Gate Source Threshold Voltage
Fig.: Transfer Characteristic
10
Figure below shows the transfer characteristic which gives the variation of I D with VGS for a
given value of VDS .
L in e a r S a tu ra tio n
re g io n re g io n
V G S3
ID V G S2
V G S1
V D S
VGS 3 > VGS 2 > VGS1

Fig. : Drain Characteristic
MOSFET PARAMETERS
The parameters of MOSFET can be obtained from the graph as follows.
DI D
Mutual Transconductance g m = .
DVGS VDS = Constant
DVDS
Output or Drain Resistance Rds = .
DI D VGS = Constant
Amplification factor m = Rds x g m
Power MOSFETs are generally of enhancement type. Power MOSFETs are used in
switched mode power supplies.
Power MOSFET’s are used in high speed power converters and are available at a
relatively low power rating in the range of 1000V, 50A at a frequency range of several tens of
KHz ( f max = 100 KHz ) .
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SWITCHING CHARACTERISTICS OF MOSFET

Power MOSFETs are often used as switching devices. The switching characteristic of a
power MOSFET depends on the capacitances between gate to source CGS , gate to drain CGD
and drain to source CGS . It also depends on the impedance of the gate drive circuit. During
turn-on there is a turn-on delay td ( on ) , which is the time required for the input capacitance CGS
to charge to threshold voltage level VT . During the rise time tr , CGS charges to full gate
voltage VGSP and the device operate in the linear region (ON state). During rise time tr drain
current I D rises from zero to full on state current I D .
 Total turn-on time, ton = td ( on ) + tr
MOSFET can be turned off by discharging capacitance CGS . td ( off ) is the turn-off delay time
required for input capacitance CGS to discharge from V1 to VGSP . Fall time t f is the time
required for input capacitance to discharge from VGSP to threshold voltage VT . During fall
time t f drain current falls from I D to zero. Figure below shows the switching waveforms of
power MOSFET.
V G
V 1
V 1
V G SP
V T
tr
td (o n ) t d (o ff) t f
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CONSTRUCTION, OPERATION & STATIC CHARACTERISTICS OF INSULATED

GATE BIPOLAR TRANSISTOR (IGBT)
IGBT is a voltage controlled device. It has high input impedance like a MOSFET and
low on-state conduction losses like a BJT.
Figure below shows the basic silicon cross-section of an IGBT. Its construction is
same as power MOSFET except that n+ layer at the drain in a power MOSFET is replaced by
P+ substrate called collector.
C o lle c to r
+ C
p
+
n B u ffe rla y e r
-
n epi G
p
+ +
n n E
G a te G a te
E m itte r
Structure Symbol
Fig.: Insulated Gate Bipolar Transistor
IGBT has three terminals gate (G), collector (C) and emitter (E). With collector and gate
voltage positive with respect to emitter the device is in forward blocking mode. When gate to
emitter voltage becomes greater than the threshold voltage of IGBT, a n-channel is formed in
the P-region. Now device is in forward conducting state. In this state p + substrate injects
holes into the epitaxial n - layer. Increase in collector to emitter voltage will result in increase
of injected hole concentration and finally a forward current is established.
CHARACTERISTIC OF IGBT
Figure below shows circuit diagram to obtain the characteristic of an IGBT. An output
characteristic is a plot of collector current I C versus collector to emitter voltage VCE for
given values of gate to emitter voltage VGE .
IC
R C
R S G V C C
V C E
V G R G E V G E
E
Fig.: Circuit Diagram to Obtain Characteristics
13
IC
V G E4
V G E3
V G E4 >V G E3 >V G E2 >V G E 1
V G E2
V G E1
V CE
Fig. : Output Characteristics

A plot of collector current I C versus gate-emitter voltage VGE for a given value of VCE gives
the transfer characteristic. Figure below shows the transfer characteristic.
Note
Controlling parameter is the gate-emitter voltage VGE in IGBT. If VGE is less than the
threshold voltage VT then IGBT is in OFF state. If VGE is greater than the threshold voltage
VT then the IGBT is in ON state.
IGBTs are used in medium power applications such as ac and dc motor drives, power
supplies and solid state relays.
IC
V G E
V T
Fig. : Transfer Characteristic
SWITCHING CHARACTERISTIC OF IGBT

Figure below shows the switching characteristic of an IGBT. Turn-on time consists of
delay time td ( on ) and rise time tr .
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V G E
V G ET
t
tr tf
t d (o n ) t d (o ff)
V CE
t (o n ) = t d (o n )+ t r
0 .9 V CE t (o ff) = t d (o ff)+ t f
0 .1 V CE
t
IC
0 .9 I C E
0 .1 I C E
t
t d (o ff) t f
Fig. : Switching Characteristics

The turn on delay time is the time required by the leakage current I CE to rise to 0.1 I C , where
I C is the final value of collector current. Rise time is the time required for collector current to
rise from 0.1 I C to its final value I C . After turn-on collector-emitter voltage VCE will be very
small during the steady state conduction of the device.
The turn-off time consists of delay off time td ( off ) and fall time t f . Off time delay is the time
during which collector current falls from I C to 0.9 I C and VGE falls to threshold voltage VGET .
During the fall time t f the collector current falls from 0.90 I C to 0.1 I C . During the turn-off
time interval collector-emitter voltage rises to its final value VCE .
IGBT’s are voltage controlled power transistor. They are faster than BJT’s, but still not quite
as fast as MOSFET’s. the IGBT’s offer for superior drive and output characteristics when
compared to BJT’s. IGBT’s are suitable for high voltage, high current and frequencies upto
20KHz. IGBT’s are available upto 1400V, 600A and 1200V, 1000A.
IGBT APPLICATIONS
Medium power applications like DC and AC motor drives, medium power supplies, solid
state relays and contractors, general purpose inverters, UPS, welder equipments, servo
controls, robotics, cutting tools, induction heating
TYPICAL RATINGS OF IGBT
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Voltage rating = 1400V. Current rating = 600A. Maximum operating frequency = 20KHz.
Switching time �2.3m s ( tON �tOFF ) . ON state resistance = 600m = 60 x10-3  .
POWER MOSFET RATINGS
Voltage rating = 500V. Current rating = 50A. Maximum operating frequency = 100KHz.
Switching time �0.6 m s to 1m s ( tON �tOFF ) . ON state resistance RD( ON ) = 0.4m to 0.6m .
tf Turn off fall time = 350nsec.
tOFF = td ( OFF ) + t f = 700n sec (maximum)
trr Reverse recovery time 250nsec.

Qrr Reverse recovery charge = 2.97mc (typical).
CONSTRUCTION & OPERATION OF THYRISTORS

A thyristor is the most important type of power semiconductor devices. They are extensively
used in power electronic circuits. They are operated as bi-stable switches from non-
conducting to conducting state.
A thyristor is a four layer, semiconductor of p-n-p-n structure with three p-n junctions. It has
three terminals, the anode, cathode and the gate.
The word thyristor is coined from thyratron and transistor. It was invented in the year 1957 at
Bell Labs. The Different types of Thyristors are
 Silicon Controlled Rectifier (SCR).
 TRIAC
 DIAC
 Gate Turn Off Thyristor (GTO)
SILICON CONTROLLED RECTIFIER (SCR)
The SCR is a four layer three terminal device with junctions

J1 , J 2 , J 3 as shown. The construction of SCR shows that the gate
terminal is kept nearer the cathode. The approximate thickness of
each layer and doping densities are as indicated in the figure. In
terms of their lateral dimensions Thyristors are the largest
semiconductor devices made. A complete silicon wafer as large as
ten centimeter in diameter may be used to make a single high
Fig.: Symbol power thyristor.
16
G a te C a th o d e
n
+
10
19
cm
-3
n
+
10
19
cm
-3
 1 0 mm

J3 - 17 -3
p 10 cm 3 0 -1 00 mm

J2
–
n 10
13
-5 x 1 0
14
cm
-3 5 0 -1 0 0 0 mm
J1
p
+
10
17
cm
-3
 3 0 -5 0 mm
19 -3
p 10 cm
Anode
Fig.: Structure of a generic thyristor
QUALITATIVE ANALYSIS
When the anode is made positive with respect the cathode junctions J1 & J 3 are forward
biased and junction J 2 is reverse biased. With anode to cathode voltage VAK being small,
only leakage current flows through the device. The SCR is then said to be in the forward
blocking state. If VAK is further increased to a large value, the reverse biased junction J 2 will
breakdown due to avalanche effect resulting in a large current through the device. The
voltage at which this phenomenon occurs is called the forward breakdown voltage VBO . Since
the other junctions J1 & J 3 are already forward biased, there will be free movement of
carriers across all three junctions resulting in a large forward anode current. Once the SCR is
switched on, the voltage drop across it is very small, typically 1 to 1.5V. The anode current is
limited only by the external impedance present in the circuit.
Fig.: Simplified model of a thyristor
Although an SCR can be turned on by increasing the forward voltage beyond VBO , in
practice, the forward voltage is maintained well below VBO and the SCR is turned on by
17
applying a positive voltage between gate and cathode. With the application of positive gate
voltage, the leakage current through the junction J 2 is increased. This is because the resulting
gate current consists mainly of electron flow from cathode to gate. Since the bottom end layer
is heavily doped as compared to the p-layer, due to the applied voltage, some of these
electrons reach junction J 2 and add to the minority carrier concentration in the p-layer. This
raises the reverse leakage current and results in breakdown of junction J 2 even though the
applied forward voltage is less than the breakdown voltage VBO . With increase in gate current
breakdown occurs earlier.
V-I CHARACTERISTICS OF THYRISTOR
RL
VAA K
Fig. Circuit
VGG
Fig: V-I Characteristics

A typical V-I characteristics of a thyristor is shown above. In the reverse direction the
thyristor appears similar to a reverse biased diode which conducts very little current until
avalanche breakdown occurs. In the forward direction the thyristor has two stable states or
modes of operation that are connected together by an unstable mode that appears as a
negative resistance on the V-I characteristics. The low current high voltage region is the
forward blocking state or the off state and the low voltage high current mode is the on state.
For the forward blocking state the quantity of interest is the forward blocking voltage VBO
which is defined for zero gate current. If a positive gate current is applied to a thyristor then
the transition or break over to the on state will occur at smaller values of anode to cathode
voltage as shown. Although not indicated the gate current does not have to be a dc current but
instead can be a pulse of current having some minimum time duration. This ability to switch
the thyristor by means of a current pulse is the reason for wide spread applications of the
device.
18
However once the thyristor is in the on state the gate cannot be used to turn the device off.
The only way to turn off the thyristor is for the external circuit to force the current through
the device to be less than the holding current for a minimum specified time period.
Fig.: Effects on gate current on forward blocking voltage
HOLDING CURRENT I H
After an SCR has been switched to the on state a certain minimum value of anode current is
required to maintain the thyristor in this low impedance state. If the anode current is reduced
below the critical holding current value, the thyristor cannot maintain the current through it
and reverts to its off state usually I m is associated with turn off the device.
LATCHING CURRENT I L
After the SCR has switched on, there is a minimum current required to sustain conduction.
This current is called the latching current. I L associated with turn on and is usually greater
than holding current.
TWO TRANSISTOR MODEL OF TRANSISTOR
The general transistor equations are,
19
I C = b I B + ( 1 + b ) ICBO
I C = a I E + I CBO
I E = IC + I B
I B = I E ( 1 - a ) - ICBO
The SCR can be considered to be made up of two transistors as shown in above figure.
Considering PNP transistor of the equivalent circuit,
I E 1 = I A , I C = I C1 , a = a1 , I CBO = I CBO1 , I B = I B1
\ I B1 = I A ( 1 - a1 ) - I CBO1 - - - ( 1)
Considering NPN transistor of the equivalent circuit,

I C = I C2 , I B = I B2 , I E2 = I K = I A + I G
I C2 = a 2 I k + I CBO2
I C2 = a 2 ( I A + I G ) + I CBO2 - - - ( 2)
From the equivalent circuit, we see that

\ I C2 = I B1
a 2 I g + I CBO1 + I CBO 2
� IA =
1 - ( a1 + a 2 )
Two transistors analog is valid only till SCR reaches ON state
Case 1: When I g = 0 ,
I CBO1 + I CBO2
IA =
1 - ( a1 + a 2 )
The gain a1 of transistor T1 varies with its emitter current I E = I A . Similarly varies with
I E = I A + I g = I K . In this case, with I g = 0 , a 2 varies only with I A . Initially when the applied
forward voltage is small, ( a1 + a 2 ) < 1 .
If however the reverse leakage current is increased by increasing the applied forward voltage,
the gains of the transistor increase, resulting in ( a1 + a 2 ) � 1 .
From the equation, it is seen that when ( a1 + a 2 ) = 1 , the anode current I A tends towards �.
This explains the increase in anode current for the break over voltage VB 0 .
Case 2: With gate current I g applied.
When sufficient gate drive is applied, we see that I B2 = I g is established. This in turn results in
a current through transistor T2 , this increases a 2 of T2 . But with the existence of
I C2 = b 2 I b 2 = b 2 I g , a current through T, is established. Therefore,
20
I C1 = b1 I B1 = b1 b 2 I B2 = b1 b 2 I g . This current in turn is connected to the base of T2 . Thus the
base drive of T2 is increased which in turn increases the base drive of T1 , therefore
regenerative feedback or positive feedback is established between the two transistors. This
causes ( a1 + a 2 ) to tend to unity therefore the anode current begins to grow towards a large
value. This regeneration continues even if I g is removed this characteristic of SCR makes it
suitable for pulse triggering; SCR is also called a Lathing Device.
SWITCHING CHARACTERISTICS (DYNAMIC CHARACTERISTICS) OF SCR

THYRISTOR TURN-ON CHARACTERISTICS
When the SCR is turned on with the application of the gate signal, the SCR does not conduct
fully at the instant of application of the gate trigger pulse. In the beginning, there is no
appreciable increase in the SCR anode current, which is because, only a small portion of the
silicon pellet in the immediate vicinity of the gate electrode starts conducting. The duration
between 90% of the peak gate trigger pulse and the instant the forward voltage has fallen to
90% of its initial value is called the gate controlled / trigger delay time t gd . It is also defined
as the duration between 90% of the gate trigger pulse and the instant at which the anode
current rises to 10% of its peak value. t gd is usually in the range of 1msec.
Fig.: Turn-on characteristics
Once t gd has lapsed, the current starts rising towards the peak value. The period during which
the anode current rises from 10% to 90% of its peak value is called the rise time. It is also
defined as the time for which the anode voltage falls from 90% to 10% of its peak value. The
summation of t gd and tr gives the turn on time ton of the thyristor.
THYRISTOR TURN OFF CHARACTERISTICS
21
V AK
tC
tq
IA
d i
C o m m u t a t io n
A n o d e c u rre n t d t
b e g in s t o
d e cre a se R ecovery R e c o m b in a tio n
t1 t2 t3 t4 t5
tq= d e v ic e o f f t im e
trr tgr
tc= c ir c u it o f f t im e
tq
tc
When an SCR is turned on by the gate signal, the gate loses control over the device and the
device can be brought back to the blocking state only by reducing the forward current to a
level below that of the holding current. In AC circuits, however, the current goes through a
natural zero value and the device will automatically switch off. But in DC circuits, where no
neutral zero value of current exists, the forward current is reduced by applying a reverse
voltage across anode and cathode and thus forcing the current through the SCR to zero.
As in the case of diodes, the SCR has a reverse recovery time trr which is due to charge
storage in the junctions of the SCR. These excess carriers take some time for recombination
resulting in the gate recovery time or reverse recombination time t gr . Thus, the turn-off time
tq is the sum of the durations for which reverse recovery current flows after the application of
reverse voltage and the time required for the recombination of all excess carriers present. At
the end of the turn off time, a depletion layer develops across J 2 and the junction can now
withstand the forward voltage. The turn off time is dependent on the anode current, the
magnitude of reverse Vg applied ad the magnitude and rate of application of the forward
voltage. The turn off time for converte grade SCR’s is 50 to 100msec and that for inverter
grade SCR’s is 10 to 20msec.
To ensure that SCR has successfully turned off , it is required that the circuit off time tc be
greater than SCR turn off time tq .
THYRISTOR TURN ON
 Thermal Turn on: If the temperature of the thyristor is high, there will be an increase
in charge carriers which would increase the leakage current. This would cause an
increase in a1 & a 2 and the thyristor may turn on. This type of turn on many cause
thermal run away and is usually avoided.
 Light: If light be allowed to fall on the junctions of a thyristor, charge carrier
concentration would increase which may turn on the SCR.
 LASCR: Light activated SCRs are turned on by allowing light to strike the silicon
wafer.
22
 High Voltage Triggering: This is triggering without application of gate voltage with
only application of a large voltage across the anode-cathode such that it is greater than
the forward breakdown voltage VBO . This type of turn on is destructive and should be
avoided.
 Gate Triggering: Gate triggering is the method practically employed to turn-on the
thyristor. Gate triggering will be discussed in detail later.
dv
 Triggering: Under transient conditions, the capacitances of the p-n junction will
dt
influence the characteristics of a thyristor. If the thyristor is in the blocking state, a
rapidly rising voltage applied across the device would cause a high current to flow
through the device resulting in turn-on. If i j2 is the current throught the junction j2 and
C j2 is the junction capacitance and V j2 is the voltage across j2 , then
( )
dq2 d C j dVJ 2 dC j2
ij 2 = = C j Vj = 2 + V j2
dt dt 2 2
dt dt
dv
From the above equation, we see that if is large, 1 j2 will be large. A high value of charging
dt
dv
current may damage the thyristor and the device must be protected against high . The
dt
dv
manufacturers specify the allowable .
dt
THYRISTOR RATINGS
First Subscript Second Subscript Third Subscript

D  off state W  working M  Peak Value
T  ON state R  Repetitive
23
F  Forward S Surge or non-repetitive

R  Reverse
VOLTAGE RATINGS
VDWM : This specifies the peak off state working forward voltage of the device. This specifies
the maximum forward off state voltage which the thyristor can withstand during its working.
VDRM : This is the peak repetitive off state forward voltage that the thyristor can block
repeatedly in the forward direction (transient).
VDSM : This is the peak off state surge / non-repetitive forward voltage that will occur across
the thyristor.
VRWM : This the peak reverse working voltage that the thyristor can withstand in the reverse
direction.
VRRM : It is the peak repetitive reverse voltage. It is defined as the maximum permissible
instantaneous value of repetitive applied reverse voltage that the thyristor can block in
reverse direction.
VRSM : Peak surge reverse voltage. This rating occurs for transient conditions for a specified
time duration.
VT : On state voltage drop and is dependent on junction temperature.
VTM : Peak on state voltage. This is specified for a particular anode current and junction
temperature.
dv
rating: This is the maximum rate of rise of anode voltage that the SCR has to withstand
dt
dv
and which will not trigger the device without gate signal (refer triggering).
dt
CURRENT RATING
ITaverage : This is the on state average current which is specified at a particular temperature.
24
ITRMS : This is the on-state RMS current.
Latching current, I L : After the SCR has switched on, there is a minimum current required to
sustain conduction. This current is called the latching current. I L associated with turn on and
is usually greater than holding current
Holding current, I H : After an SCR has been switched to the on state a certain minimum value
of anode current is required to maintain the thyristor in this low impedance state. If the anode
current is reduced below the critical holding current value, the thyristor cannot maintain the
current through it and reverts to its off state usually I m is associated with turn off the device.
di
rating: This is a non repetitive rate of rise of on-state current. This maximum value of rate
dt
of rise of current is which the thyristor can withstand without destruction. When thyristor is
switched on, conduction starts at a place near the gate. This small area of conduction spreads
di
rapidly and if rate of rise of anode current is large compared to the spreading velocity of
dt
carriers, local hotspots will be formed near the gate due to high current density. This causes
the junction temperature to rise above the safe limit and the SCR may be damaged
di
permanently. The rating is specified in A m sec .
dt
GATE SPECIFICATIONS
I GT : This is the required gate current to trigger the SCR. This is usually specified as a DC
value.
VGT : This is the specified value of gate voltage to turn on the SCR (dc value).
VGD : This is the value of gate voltage, to switch from off state to on state. A value below this
will keep the SCR in off state.
QRR : Amount of charge carriers which have to be recovered during the turn off process.
Rthjc : Thermal resistance between junction and outer case of the device.
VARIOUS GATE TRIGGERING METHODS OF SCR.

Types
The different methods of gate triggering are the following
25
 R-triggering.
 RC triggering.
 UJT triggering.
RESISTANCE TRIGGERING
A simple resistance triggering circuit is as shown. The resistor R1 limits the current through
the gate of the SCR. R2 is the variable resistance added to the circuit to achieve control over
the triggering angle of SCR. Resistor ‘R’ is a stabilizing resistor. The diode D is required to
ensure that no negative voltage reaches the gate of the SCR.
vO
a b
LO AD
i R 1
R 2
v S = V m s in  t
D V T
R V g
Fig.: Resistance firing circuit
V S V S V S
V m s in  t
3 4 3 4 3 4
 2 t  2 t  2 t
Vg Vgt Vg Vg Vgp> Vgt

Vgp= Vgt
Vgp Vgp Vgt t t t

Vo Vo Vo
a
t t t
io io io
t 0 t t
270
VT VT VT
3 4
t  2 t t
a 0 0
0 a= 90 a< 90
90
(a ) (b ) (c )
Fig.: Resistance firing of an SCR in half wave circuit with dc load
(a) No triggering of SCR (b) a = 900 (c) a < 900

Design
26
Vm
With R2 = 0 , we need to ensure that < I gm , where I gm is the maximum or peak gate
R1
Vm
current of the SCR. Therefore R1 � .
I gm
Also with R2 = 0 , we need to ensure that the voltage drop across resistor ‘R’ does not exceed
Vgm , the maximum gate voltage
V R
Vgm � m
R1 + R
\ Vgm R1 + Vgm R �Vm R
\ Vgm R1 �R ( Vm - Vgm )
V R
R � gm 1
Vm - Vgm
OPERATION
Case 1: Vgp < Vgt
Vgp , the peak gate voltage is less then Vgt since R2 is very large. Therefore, current ‘I’ flowing
through the gate is very small. SCR will not turn on and therefore the load voltage is zero and
vscr is equal to Vs . This is because we are using only a resistive network. Therefore, output
will be in phase with input.
Case 2: Vgp = Vgt , R2 � optimum value.
When R2 is set to an optimum value such that Vgp = Vgt , we see that the SCR is triggered at
900 (since Vgp reaches its peak at 900 only). The waveforms shows that the load voltage is
zero till 900 and the voltage across the SCR is the same as input voltage till it is triggered at
900 .
Case 3: Vgp > Vgt , R2 � small value.
The triggering value Vgt is reached much earlier than 900 . Hence the SCR turns on earlier
than VS reaches its peak value. The waveforms as shown with respect to Vs = Vm sin  t .
At  t = a , VS = Vgt ,Vm = Vgp ( Q Vgt = Vgp sin a )
�V �
Therefore a = sin -1 � gt �
�Vgp �
� �
Vm R
But Vgp =
R1 + R2 + R
V ( R + R2 + R ) �
�
Therefore a = sin -1 �gt 1 �
� Vm R �
Since Vgt , R1 , R are constants aa R2
27
RESISTANCE CAPACITANCE TRIGGERING
RC HALF WAVE
Capacitor ‘C’ in the circuit is connected to shift the phase of the gate voltage. D1 is used to
prevent negative voltage from reaching the gate cathode of SCR.
In the negative half cycle, the capacitor charges to the peak negative voltage of the supply
( -Vm ) through the diode D2 . The capacitor maintains this voltage across it, till the supply
voltage crosses zero. As the supply becomes positive, the capacitor charges through resistor
‘R’ from initial voltage of -Vm , to a positive value.
When the capacitor voltage is equal to the gate trigger voltage of the SCR, the SCR is fired
and the capacitor voltage is clamped to a small positive value.
vO
LO AD
+
R
D 2 V T
-
v S = V m s in  t
D 1
V C C
Fig.: RC half-wave trigger circuit

V m s in  t V m s in  t
vs vs
V gt V gt
-/2 0 -/2 0
0 t 0 t
vc vc
vc vc
a a a a
vo a a vo
Vm Vm
0
    t a t
vT vT
Vm
a a 0   t
-V m t  
a -V m
(2 + a )
(a ) (b )
Fig.: Waveforms for RC half-wave trigger circuit

(a) High value of R (b) Low value of R
Case 1: R  Large.
When the resistor ‘R’ is large, the time taken for the capacitance to charge from -Vm to Vgt is
large, resulting in larger firing angle and lower load voltage.
Case 2: R  Small
28
When ‘R’ is set to a smaller value, the capacitor charges at a faster rate towards Vgt resulting
in early triggering of SCR and hence VL is more. When the SCR triggers, the voltage drop
across it falls to 1 – 1.5V. This in turn lowers, the voltage across R & C. Low voltage across
the SCR during conduction period keeps the capacitor discharge during the positive half
cycle.
DESIGN EQUATION
From the circuit VC = Vgt + Vd 1 . Considering the source voltage and the gate circuit, we can
write vs = I gt R + VC . SCR fires when vs �I gt R + VC that is vS �I g R + Vgt + Vd 1 . Therefore
v - Vgt - Vd 1
R�s . The RC time constant for zero output voltage that is maximum firing angle
I gt
�T �
for power frequencies is empirically gives as RC �1.3 � �.
�2 �
RC FULL WAVE
A simple circuit giving full wave output is shown in figure below. In this circuit the initial
voltage from which the capacitor ‘C’ charges is essentially zero. The capacitor ‘C’ is reset to
this voltage by the clamping action of the thyristor gate. For this reason the charging time
constant RC must be chosen longer than for half wave RC circuit in order to delay the
50T vs - Vgt
triggering. The RC value is empirically chosen as RC � . Also R � .
2 I gt
v O
LOAD
+
+
D1 D3 R
V T
v d -
C
vS= V m s in  t
D4 D2
-
Fig: RC full-wave trigger circuit
29
vs V m s in  t vs V m s in  t
t t
vd
vd vd
vc vc vgt vc t vgt t
vo vo
a a a
a
t t
vT vT
t
(a ) (b )
Fig: Wave-forms for RC full-wave trigger circuit
(a) High value of R (b) Low value of R
PROBLEM
1. Design a suitable RC triggering circuit for a thyristorised network operation on a
220V, 50Hz supply. The specifications of SCR are Vgt min = 5V , I gt max = 30mA .
vs - Vgt - VD
R= = 7143.3
Ig
Therefore RC �0.013
R �7.143k
C �1.8199 m F
UNI-JUNCTION TRANSISTOR (UJT)
B 2 B 2
E t a - p o in t +
B 2
R B2 E t a - p o in t
R B2
p -ty p e
E
E A A V BB
E +
R B1
n -ty p e R
V e Ie B1
V BB
- -
B 1 B 1 B 1
(a ) (b ) (c)
Fig.: (a) Basic structure of UJT (b) Symbolic representation (c) Equivalent circuit
UJT is an n-type silicon bar in which p-type emitter is embedded. It has three terminals
base1, base2 and emitter ‘E’. Between B1 and B2 UJT behaves like ordinary resistor and the
30
internal resistances are given as RB1 and RB 2 with emitter open RB B = RB1 + RB 2 . Usually the
p-region is heavily doped and n-region is lightly doped. The equivalent circuit of UJT is as
shown. When VBB is applied across B1 and B2 , we find that potential at A is
VBB RB1 � RB1 �

VAB1 = = VBB �
= �
RB1 + RB 2 � RB1 + RB 2 �
 is intrinsic stand off ratio of UJT and ranges between 0.51 and 0.82. Resistor RB 2 is
between 5 to 10K.
OPERATION
When voltage VBB is applied between emitter ‘E’ with base 1 B1 as reference and the emitter
voltage VE is less than ( VD + VBE ) the UJT does not conduct. ( VD + VBB ) is designated as VP
which is the value of voltage required to turn on the UJT. Once VE is equal to VP �VBE + VD ,
then UJT is forward biased and it conducts.
The peak point is the point at which peak current I P flows and the peak voltage VP is across
the UJT. After peak point the current increases but voltage across device drops, this is due to
the fact that emitter starts to inject holes into the lower doped n-region. Since p-region is
heavily doped compared to n-region. Also holes have a longer life time, therefore number of
carriers in the base region increases rapidly. Thus potential at ‘A’ falls but current I E
increases rapidly. RB1 acts as a decreasing resistance.
The negative resistance region of UJT is between peak point and valley point. After valley
point, the device acts as a normal diode since the base region is saturated and RB1 does not
decrease again.
N e g a t iv e R e s i s t a n c e
R e g io n
Ve
C u to ff S a tu r a tio n
r e g io n r e g io n
VBB
R lo a d l in e
Vp
P e a k P o in t
V a ll e y P o i n t
Vv
0 Ip Iv Ie
Fig.: V-I Characteristics of UJT
UJT RELAXATION OSCILLATOR
31
UJT is highly efficient switch. The switching times is in the range of nanoseconds. Since UJT
exhibits negative resistance characteristics it can be used as relaxation oscillator. The circuit
diagram is as shown with R1 and R2 being small compared to RB1 and RB 2 of UJT.
Ve C a p a c it o r C a p a c it o r
V BB+ V d i s c h a r g in g
c h a r g in g
VBB T2= R 1C
Vp
R R2
B VP
E 2 T 1= R C Vv
VV
T t
C B1
Ve R1 v
o Vo
a1

t
(a ) (b )
Fig.: UJT oscillator (a) Connection diagram and (b) Voltage waveforms
OPERATION
When VBB is applied, capacitor ‘C’ begins to charge through resistor ‘R’ exponentially
towards VBB . During this charging emitter circuit of UJT is an open circuit. The rate of
charging is t 1 = RC . When this capacitor voltage which is nothing but emitter voltage VE
reaches the peak point VP = VBB + VD , the emitter base junction is forward biased and UJT
turns on. Capacitor ‘C’ rapidly discharges through load resistance R1 with time constant
t 2 = R1C ( t 2 = t 1 ) . When emitter voltage decreases to valley point Vv , UJT turns off. Once
again the capacitor will charge towards VBB and the cycle continues. The rate of charging of
the capacitor will be determined by the resistor R in the circuit. If R is small the capacitor
charges faster towards VBB and thus reaches VP faster and the SCR is triggered at a smaller
firing angle. If R is large the capacitor takes a longer time to charge towards VP the firing
angle is delayed. The waveform for both cases is as shown below.
EXPRESSION FOR PERIOD OF OSCILLATION ‘T’

The period of oscillation of the UJT can be derived based on the voltage across the capacitor.
Here we assume that the period of charging of the capacitor is lot larger than than the
discharging time.
Using initial and final value theorem for voltage across a capacitor, we get
VC = V final + ( Vinitial - V final ) e

-t
RC
t = T ,VC = VP ,Vinitial = VV , V final = VBB
32
Therefore VP = VBB + ( VV - VBB ) e-T / RC
V -V �
�
� T = RC log e � BB V �
VBB - VP �
�
If
VV < VBB ,
� V �
T = RC ln � BB �
VBB - VP �
�
� �
� 1 �
= RC ln � �
� VP �
1-
�
� VBB ��
But VP = VBB + VD
If VD = VBB VP = VBB
�1 �
Therefore T = RC ln � �
1 - �
�
DESIGN OF UJT OSCILLATOR
Resistor ‘R’ is limited to a value between 3 kilo ohms and 3 mega ohms. The upper limit on
‘R’ is set by the requirement that the load line formed by ‘R’ and VBB intersects the device
characteristics to the right of the peak point but to the left of valley point. If the load line fails
to pass to the right of the peak point the UJT will not turn on, this condition will be satisfied
VBB - VP
if VBB - I P R > VP , therefore R < .
IP
At the valley point I E = IV and VE = VV , so the condition for the lower limit on ‘R’ to ensure
VBB - VV
turn-off is VBB - IV R < VV , therefore R > .
IV
The recommended range of supply voltage is from 10 to 35V. the width of the triggering
pulse t g = RB1C .
In general RB1 is limited to a value of 100 ohm and RB 2 has a value of 100 ohm or greater and
104
can be approximately determined as RB 2 = .
VBB
33
dv
OPERATION OF PROTECTION
dt
dv
The across the thyristor is limited by using snubber circuit as shown in figure (a) below.
dt
If switch S1 is closed at t = 0 , the rate of rise of voltage across the thyristor is limited by the
capacitor CS . When thyristor T1 is turned on, the discharge current of the capacitor is limited
by the resistor RS as shown in figure (b) below.
Fig. (a)
Fig. (b)
Fig. (c)
34
The voltage across the thyristor will rise exponentially as shown by fig (c) above.
From fig. (b) above, circuit we have (for SCR off)
1
VS = i ( t ) RS + i ( t ) dt + Vc ( 0 ) [ for t = 0] .
C�
VS - t t s
Therefore i( t) = e , where t s = RS CS
RS
Also VT ( t ) = VS - i ( t ) RS
VS - t t s
VT ( t ) = VS - e RS
RS
-t
� -tt s �
Therefore VT ( t ) = VS - VS e ts
= VS �
1- e �
� �
At t = 0, VT ( 0 ) = 0
At t = t s , VT ( t s ) = 0.632VS
dv VT ( t s ) - VT ( 0 ) 0.632VS
Therefore = =
dt ts RS CS
VS
And RS = .
ITD
ITD is the discharge current of the capacitor.
dv
It is possible to use more than one resistor for and discharging as shown in the
dt
dv
figure (d) below. The is limited by R1 and CS . R1 + R2 limits the discharging current such
dt
VS
that ITD =
R1 + R2
Fig. (d)
The load can form a series circuit with the snubber network as shown in figure (e) below.
The damping ratio of this second order system consisting RLC network is given as,
35
a RS + R CS
d= = , where LS is stray inductance and L, R is load inductance
0 2 LS + L
and resistance respectively.
To limit the peak overshoot applied across the thyristor, the damping ratio should be in the
range of 0.5 to 1. If the load inductance is high, RS can be high and CS can be small to retain
the desired value of damping ratio. A high value of RS will reduce discharge current and a
low value of CS reduces snubber loss. The damping ratio is calculated for a particular circuit
RS and CS can be found.
Fig. (e)
di
OPERATION OF PROTECTION
dt
36
di
Practical devices must be protected against high . As an example let us consider the
dt
circuit shown above, under steady state operation Dm conducts when thyristor T1 is off.
di
If T1 is fired when Dm is still conducting can be very high and limited only by the stray
dt
di
inductance of the circuit. In practice the is limited by adding a series inductor LS as
dt
di VS
shown in the circuit above. Then the forward = .
dt LS
GATE TURN-OFF THYRISTORS
A gate-turn-off thyristor (GTO) like an SCR can be turned on by applying a positive gate
signal. However, it can be turned off by a negative gate signal. A GTO is a latching device
and can be built with current and voltage ratings similar to those of an SCR. A GTO is turned
on by applying a short positive pulse and turned off by a short negative pulse to its gate. The
GTOs have advantages over SCRs.
Elimination of commutating components in forced commutation, resulting in reduction in
cost, weight, and volume.
37
Reduction in acoustic and electro-magnetic noise due to the elimination of commutation
chokes.
Faster turn-off permitting high switching frequencies and
Improved efficiency of converters.
In low power applications GTOs have the following advantages over bipolar transistors.
A higher blocking voltage capability.
A high ratio of peak controllable current to average current.
A high ratio of surge peak current to average current, typically 10:1.
A high on-state gain (anode current/gate current), typically 600; and
A pulsed gate signal of short duration.
Under surge conditions, a GTO goes into deeper saturation due to regenerative action. On the
other hand, a bipolar transistor tends to come out of saturation.
A GTO has low gain during turn-off, typically 6, and requires a relatively high negative
current pulse to turn off. It has higher on-state voltage than that of SCRs. The on-state voltage
of typical 550A, 1200V GTO is typically 3.4V.
Controllable peak on-state current ITGQ is the peak value of on-state current which can be
turned off by gate control. The off state voltage is reapplied immediately after turn-off and
the reapplied dv dt is only limited by the snubber capacitance. Once a GTO is turned off, the
load current I L , which is diverted through and charges the snubber capacitor, determines the
reapplied dv dt .
dv I L
=
dt Cs
Where Cs is the snubber capacitance

SWITCHING CHARACTERISTICS OF GTO:
38
Where,tq=Turn off time
ts=storage time
tf=fall time
tt=tail time
During storage time ts, the negative gate current rises to a particular value and prepares the
GTO for turning off by flushing out the stored carriers. After ts, anode current begins to fall
rapidly and anode voltage starts rising.
As shown in the fig (b) the anode current falls to a certain value and then abruptly changes its
rate of fall. This interval during which anode current falls rapidly is the fall time tf and is of
order 1μsec
At the time t= ts+tf, there is a spike in voltage due to abrupt change in anode current. After tf ,
anode current ia and anode voltage va keep moving towards their turn off values for a time tt
called tail time.
NOTE:
 For V-I Characteristics and Turn ON Switching Characteristics of GTO refer

SCR Characteristics
 Turn ON Switching Characteristics of GTO is same as SCR Turn ON
Characteristics, But TURN OFF Characteristics will be differ
THYRISTOR COMMUTATION TECHNIQUES

In practice it becomes necessary to turn off a conducting thyristor. (Often thyristors
are used as switches to turn on and off power to the load). The process of turning off a
conducting thyristor is called commutation. The principle involved is that either the anode
should be made negative with respect to cathode (voltage commutation) or the anode current
should be reduced below the holding current value (current commutation).
The reverse voltage must be maintained for a time at least equal to the turn-off time of
SCR otherwise a reapplication of a positive voltage will cause the thyristor to conduct even
without a gate signal. On similar lines the anode current should be held at a value less than
the holding current at least for a time equal to turn-off time otherwise the SCR will start
conducting if the current in the circuit increases beyond the holding current level even
without a gate signal. Commutation circuits have been developed to hasten the turn-off
process of Thyristors. The study of commutation techniques helps in understanding the
transient phenomena under switching conditions.
The reverse voltage or the small anode current condition must be maintained for a
time at least equal to the TURN OFF time of SCR; Otherwise the SCR may again start
conducting. The techniques to turn off a SCR can be broadly classified as
 Natural Commutation
 Forced Commutation.
NATURAL COMMUTATION (CLASS F)

This type of commutation takes place when supply voltage is AC, because a negative
voltage will appear across the SCR in the negative half cycle of the supply voltage and the
SCR turns off by itself. Hence no special circuits are required to turn off the SCR. That is the
39
reason that this type of commutation is called Natural or Line Commutation. Figure 1.1
shows the circuit where natural commutation takes place and figure 1.2 shows the related
waveforms. tc is the time offered by the circuit within which the SCR should turn off
completely. Thus tc should be greater than tq , the turn off time of the SCR. Otherwise, the
SCR will become forward biased before it has turned off completely and will start conducting
even without a gate signal.
T
+
v s ~  R  v o
Fig. 1.1: Circuit for Natural Commutation
Fig. 1.2: Natural Commutation – Waveforms of Supply and Load Voltages (Resistive
Load)
This type of commutation is applied in ac voltage controllers, phase controlled
rectifiers and cyclo converters.
FORCED COMMUTATION
When supply is DC, natural commutation is not possible because the polarity of the
supply remains unchanged. Hence special methods must be used to reduce the SCR current
below the holding value or to apply a negative voltage across the SCR for a time interval
greater than the turn off time of the SCR. This technique is called FORCED
COMMUTATION and is applied in all circuits where the supply voltage is DC - namely,
Choppers (fixed DC to variable DC), inverters (DC to AC). Forced commutation techniques
are as follows:
 Self Commutation
 Resonant Pulse Commutation
 Complementary Commutation
40
 Impulse Commutation
 External Pulse Commutation.
 Load Side Commutation.
 Line Side Commutation.
SELF COMMUTATION OR LOAD COMMUTATION OR CLASS A

COMMUTATION: (COMMUTATION BY RESONATING THE LOAD)
In this type of commutation the current through the SCR is reduced below the holding
current value by resonating the load. i.e., the load circuit is so designed that even though the
supply voltage is positive, an oscillating current tends to flow and when the current through
the SCR reaches zero, the device turns off. This is done by including an inductance and a
capacitor in series with the load and keeping the circuit under-damped. Figure 1.3 shows the
circuit.
This type of commutation is used in Series Inverter Circuit.
T L V c(0 )
i R + -
L o ad C
Fig. 1.3: Circuit for Self Commutation

C
V
L C u rre n t i
t
0 /2 
2 V
C a p a c ito r v o lta g e
V
t
G a te p u ls e
t
t
-V
V o lta g e a c ro s s S C R
Fig. 1.5: Self Commutation – Wave forms of Current and Capacitors Voltage
RESONANT PULSE COMMUTATION (CLASS B COMMUTATION)
The circuit for resonant pulse commutation is shown in figure 1.12.
41
L
T
i
a
b C
IL
V
L oad
F W D
Fig. 1.12: Circuit for Resonant Pulse Commutation

This is a type of commutation in which a LC series circuit is connected across the
SCR. Since the commutation circuit has negligible resistance it is always under-damped i.e.,
the current in LC circuit tends to oscillate whenever the SCR is on.
Initially the SCR is off and the capacitor is charged to V volts with plate ‘a’ being
positive. Referring to figure 1.13 at t = t1 the SCR is turned ON by giving a gate pulse. A
current I L flows through the load and this is assumed to be constant. At the same time SCR
short circuits the LC combination which starts oscillating. A current ‘i’ starts flowing in the
direction shown in figure. As ‘i’ reaches its maximum value, the capacitor voltage reduces to
zero and then the polarity of the capacitor voltage reverses ‘b’ becomes positive). When ‘i’
falls to zero this reverse voltage becomes maximum, and then direction of ‘i’ reverses i.e.,
through SCR the load current I L and ‘i’ flow in opposite direction. When the instantaneous
value of ‘i’ becomes equal to I L , the SCR current becomes zero and the SCR turns off. Now
the capacitor starts charging and its voltage reaches the supply voltage with plate a being
positive.
G a te p u ls e
o f S C R
t
t 1 
V
C a p a c ito r v o lta g e
v ab
t
t C
I p i
t

I L

D t
I S C R
V o lta g e a c r o s s
S C R
t
Fig. 1.13: Resonant Pulse Commutation – Various Waveforms

ALTERNATE CIRCUIT FOR RESONANT PULSE COMMUTATION
The working of the circuit can be explained as follows. The capacitor C is assumed to
be charged to VC ( 0 ) with polarity as shown, T1 is conducting and the load current I L is a
constant. To turn off T1 , T2 is triggered. L, C, T1 and T2 forms a resonant circuit. A resonant
42
current ic ( t ) flows in the direction shown, i.e., in a direction opposite to that of load current
IL .
ic ( t ) = I p sin  t (refer to the previous circuit description). Where I p = VC ( 0 ) C &

L
and the capacitor voltage is given by
1
vc ( t ) = � iC ( t ) .dt
C
1 C .
vc ( t ) = VC ( 0 )
� sin  t.dt
C L
vc ( t ) = -VC ( 0 ) cos  t
T 1 iC ( t) IL
C L T
a b iC ( t) 2
- +
V C(0 ) L
V T 3
O
A
FW D D
Fig. 1.16: Resonant Pulse Commutation – An Alternate Circuit

When ic ( t ) becomes equal to I L (the load current), the current through T1 becomes
zero and T1 turns off. This happens at time t1 such that
t
I L = I p sin 1
LC
C
I p = VC ( 0 )
L
� IL L�
t1 = LC sin -1 � �
VC ( 0 ) C �
�
� �
and the corresponding capacitor voltage is
vc ( t1 ) = -V1 = -VC ( 0 ) cos  t1
Once the thyristor T1 turns off, the capacitor starts charging towards the supply
voltage through T2 and load. As the capacitor charges through the load capacitor current is
same as load current I L , which is constant. When the capacitor voltage reaches V, the supply
voltage, the FWD starts conducting and the energy stored in L charges C to a still higher
voltage. The triggering of T3 reverses the polarity of the capacitor voltage and the circuit is
ready for another triggering of T1 . The waveforms are shown in figure 1.17.
43
EXPRESSION FOR tc
Assuming a constant load current I L which charges the capacitor
CV
tc = 1 seconds
IL
Normally V1 �VC ( 0 )
For reliable commutation tc should be greater than tq , the turn off time of SCR T1 . It is
to be noted that tc depends upon I L and becomes smaller for higher values of load current.
C u rre n t iC (t)
V
C a p a c ito r
v o lta g e v ab
t
t1
V 1
tC
V C ( 0 )
Fig. 1.17: Resonant Pulse Commutation – Alternate Circuit – Various Waveforms

RESONANT PULSE COMMUTATION WITH ACCELERATING DIODE
D 2
iC ( t)
T 1
IL
C L iC ( t) T 2
- +
V C(0 )
L
T O
V 3
A
FW D D
Fig. 1.17(a)
44
iC
IL
0 t
V C
0 t
t1 t2
V 1
V C (O ) tC
Fig. 1.17(b)
A diode D2 is connected as shown in the figure 1.17(a) to accelerate the discharging
of the capacitor ‘C’. When thyristor T2 is fired a resonant current iC ( t ) flows through the
capacitor and thyristor T1 . At time t = t1 , the capacitor current iC ( t ) equals the load current I L
and hence current through T1 is reduced to zero resulting in turning off of T1 . Now the
capacitor current iC ( t ) continues to flow through the diode D2 until it reduces to load current
level I L at time t2 . Thus the presence of D2 has accelerated the discharge of capacitor ‘C’.
Now the capacitor gets charged through the load and the charging current is constant. Once
capacitor is fully charged T2 turns off by itself. But once current of thyristor T1 reduces to
zero the reverse voltage appearing across T1 is the forward voltage drop of D2 which is very
small. This makes the thyristor recovery process very slow and it becomes necessary to
provide longer reverse bias time.
From figure 1.17(b)
t2 =  LC - t1
VC ( t2 ) = -VC ( O ) cos  t2
Circuit turn-off time tC = t2 - t1
COMPLEMENTARY COMMUTATION (CLASS C COMMUTATION, PARALLEL
CAPACITOR COMMUTATION)
In complementary commutation the current can be transferred between two loads.
Two SCRs are used and firing of one SCR turns off the other. The circuit is shown in figure
1.21.
45
IL
R 1 R 2
a b iC
V
C
T 1 T 2
Fig. 1.21: Complementary Commutation

The working of the circuit can be explained as follows.
Initially both T1 and T2 are off; Now, T1 is fired. Load current I L flows through R1 . At
the same time, the capacitor C gets charged to V volts through R2 and T1 (‘b’ becomes
positive with respect to ‘a’). When the capacitor gets fully charged, the capacitor current ic
becomes zero.
To turn off T1 , T2 is fired; the voltage across C comes across T1 and reverse biases it,
hence T1 turns off. At the same time, the load current flows through R2 and T2 . The capacitor
‘C’ charges towards V through R1 and T2 and is finally charged to V volts with ‘a’ plate
positive. When the capacitor is fully charged, the capacitor current becomes zero. To turn off
T2 , T1 is triggered, the capacitor voltage (with ‘a’ positive) comes across T2 and T2 turns off.
The related waveforms are shown in figure
G a te p u ls e G a te p u ls e
o f T 1 o f T 2
t
p
V
I L 2V
V
C u r re n t th ro u g h R 1 R 1
R 1
t
C u r re n t th ro u g h T 2V
1
R 2
V
R 1
t
2 V C u r re n t th ro u g h T 2
R 1
V
R 2
t
V
V o lta g e a c ro s s
c a p a c ito r v ab
t
- V
tC tC
V o lta g e a c ro s s T 1 t
tC
46
IMPULSE COMMUTATION (CLASS D COMMUTATION)
The circuit for impulse commutation is as shown in figure 1.25.
T 1
IL
-
T 3 V C (O ) C
+
L
L T O
V 2
A
F W D D
Fig. 1.25: Circuit for Impulse Commutation

The working of the circuit can be explained as follows. It is assumed that initially the
capacitor C is charged to a voltage VC ( O ) with polarity as shown. Let the thyristor T1 be
conducting and carry a load current I L . If the thyristor T1 is to be turned off, T2 is fired. The
capacitor voltage comes across T1 , T1 is reverse biased and it turns off. Now the capacitor
starts charging through T2 and the load. The capacitor voltage reaches V with top plate being
positive. By this time the capacitor charging current (current through T2 ) would have reduced
to zero and T2 automatically turns off. Now T1 and T2 are both off. Before firing T1 again, the
capacitor voltage should be reversed. This is done by turning on T3 , C discharges through T3
and L and the capacitor voltage reverses. The waveforms are shown in figure
G a te p u ls e G a te p u ls e G a te p u ls e
of T 2 of T 3 of T 1
t
V S
C a p a c ito r
v o lta g e
V C
tC
V o lta g e a c r o s s T 1
t
V C
Fig. 1.26: Impulse Commutation – Waveforms of Capacitor Voltage, Voltage across T1 .

An alternative circuit for impulse commutation is shown in figure 1.27.
47
i
T 1 +
IT1 V C (O ) C
_
T 2
D
V
L
IL
R L
Fig. 1.27: Impulse Commutation – An Alternate Circuit

The working of the circuit can be explained as follows:
Initially let the voltage across the capacitor be VC ( O ) with the top plate positive.
Now T1 is triggered. Load current flows through T1 and load. At the same time, C discharges
through T1 , L and D (the current is ‘i’) and the voltage across C reverses i.e., the bottom plate
becomes positive. The diode D ensures that the bottom plate of the capacitor remains
positive.
To turn off T1 , T2 is triggered; the voltage across the capacitor comes across T1 . T1 is
reverse biased and it turns off (voltage commutation). The capacitor now starts charging
through T2 and load. When it charges to V volts (with the top plate positive), the current
through T2 becomes zero and T2 automatically turns off.
The related waveforms are shown in figure 1.28.
G a te p u ls e G a te p u ls e
of T 1 of T 2
t
V C
C a p a c ito r
v o lta g e
t
-V
tC
T h is is d u e to i
IT 1 IL
C u r re n t th r o u g h S C R V
R L
t
2V
R L
IL
L o a d c urre n t
V V o lta g e a c ro s s T 1
tC
Fig. 1.28: Impulse Commutation – (Alternate Circuit) – Various Waveforms
48
EXTERNAL PULSE COMMUTATION (CLASS E COMMUTATION)
T 1 T 2 L T 3
+
V S R 2V A U X C V A U X
L
-
Fig. 1.34: External Pulse Commutation

In this type of commutation an additional source is required to turn-off the conducting
thyristor. Figure 1.34 shows a circuit for external pulse commutation. VS is the main voltage
source and VAUX is the auxiliary supply. Assume thyristor T1 is conducting and load RL is
connected across supply VS . When thyristor T3 is turned ON at t = 0 , VAUX , T3 , L and C from
an oscillatory circuit. Assuming capacitor is initially uncharged, capacitor C is now charged
to a voltage 2VAUX with upper plate positive at t =  LC . When current through T3 falls to
zero, T3 gets commutated. To turn-off the main thyristor T1 , thyristor T2 is turned ON. Then
T1 is subjected to a reverse voltage equal to VS - 2VAUX . This results in thyristor T1 being
turned-off. Once T1 is off capacitor ‘C’ discharges through the load RL
LOAD SIDE COMMUTATION
In load side commutation the discharging and recharging of capacitor takes place
through the load. Hence to test the commutation circuit the load has to be connected.
Examples of load side commutation are Resonant Pulse Commutation and Impulse
Commutation.
LINE SIDE COMMUTATION
In this type of commutation the discharging and recharging of capacitor takes place
through the supply.
L T 1
+ IL
T +
3
_ C L
F W D O
V S A
L r D
T 2
Fig.: 1.35 Line Side Commutation Circuit

Figure 1.35 shows line side commutation circuit. Thyristor T2 is fired to
charge the capacitor ‘C’. When ‘C’ charges to a voltage of 2V, T2 is self commutated. To
reverse the voltage of capacitor to -2V, thyristor T3 is fired and T3 commutates by itself.
Assuming that T1 is conducting and carries a load current I L thyristor T2 is fired to turn off T1
. The turning ON of T2 will result in forward biasing the diode (FWD) and applying a reverse
49
voltage of 2V across T1 . This turns off T1 , thus the discharging and recharging of capacitor is
done through the supply and the commutation circuit can be tested without load.
PROBLEM
1. A UJT is used to trigger the thyristor whose minimum gate triggering voltage is 6.2V,
The UJT ratings are:  = 0.66 , I p = 0.5mA , I v = 3mA , RB1 + RB 2 = 5k  , leakage
current = 3.2mA, V p = 14v and Vv = 1V . Oscillator frequency is 2kHz and capacitor C
= 0.04mF. Design the complete circuit.
Solution
�1 �
T = RC C ln � �
1 - �
�
Here,
1 1
T= = , since f = 2kHz and putting other values,
f 2 �103
1 � 1 �
= RC �0.04 �10-6 ln � �= 11.6k 
2 �10 3
1 - 0.66 �
�
The peak voltage is given as, V p = VBB + VD
Let VD = 0.8 , then putting other values,

14 = 0.66VBB + 0.8
VBB = 20V
The value of R2 is given by

0.7 ( RB 2 + RB1 )
R2 =
VBB
0.7 ( 5 �103 )
R2 =
0.66 �20
\ R2 = 265
Value of R1 can be calculated by the equation

VBB = I leakage ( R1 + R2 + RB1 + RB 2 )
20 = 3.2 �10 -3 ( R1 + 265 + 5000 )
R1 = 985
The value of Rc( max ) is given by equation
50
VBB - V p
Rc( max ) =
Ip
20 - 14
Rc( max ) =
0.5 �10 -3
Rc( max ) = 12k 
Similarly the value of Rc( min ) is given by equation

VBB - Vv
Rc( min ) =
Iv
20 - 1
Rc( min ) =
3 �10-3
Rc( min ) = 6.33k 
2. Design the UJT triggering circuit for SCR. Given -VBB = 20V ,  = 0.6 , I p = 10 m A ,
Vv = 2V , I v = 10mA . The frequency of oscillation is 100Hz. The triggering pulse
width should be 50 m s .
Solution
1 1
The frequency f = 100Hz, Therefore T = =
f 100
�1 �
From equation T = RcC ln � �
1- �
�
Putting values in above equation,
1 � 1 �
= RcC ln � �
100 1 - 0.6 �
�
\ Rc C = 0.0109135
Let us select C = 1m F . Then Rc will be,

0.0109135
Rc( min ) =
1�10-6
Rc( min ) = 10.91k  .
The peak voltage is given as,

V p = VBB + VD
Let VD = 0.8 and putting other values,
V p = 0.6 �20 + 0.8 = 12.8V
The minimum value of Rc can be calculated from
51
V -V
Rc( min ) = BB v
Iv
20 - 2
Rc( min ) = = 1.8k 
10 �10-3
Value of R2 can be calculated from
104
R2 =
VBB
104
R2 = = 833.33
0.6 �20
Here the pulse width is give, that is 50ms.
Hence, value of R1 will be,
t 2 = R1C
The width t 2 = 50 m sec and C = 1m F , hence above equation becomes,

50 �10-6 = R1 ��
1 10 -6
\ R1 = 50
Thus we obtained the values of components in UJT triggering circuit as,
R1 = 50 , R2 = 833.33 , Rc = 10.91k  , C = 1m F .
52

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EE8552-Power Electronics Department of EEE 2019-2020

Fig: NPN Transistor Fig: Input Characteristic

Fig: Output / Collector V CE

Fig: Switching Transistor in CE Configuration

Fig. : Triac Structure Fig. : Triac Symbol

TRIGGERING MODES OF TRIAC

MODE 2 : MT2 positive, Negative gate current ( I - mode of operation)

Fig.: Triac Characteristic

Fig. : n-channel depletion type MOSFET

Fig. : P-channel depletion type MOSFET

Fig: n-channel Depletion MOSFET

Fig.: Drain Characteristic

Fig.: Transfer characteristic

Fig: n-channel Enhancement MOSFET

VT = VGS ( TH ) = Gate Source Threshold Voltage

Fig.: Transfer Characteristic

VGS 3 > VGS 2 > VGS1

Amplification factor m = Rds x g m

SWITCHING CHARACTERISTICS OF MOSFET

 Total turn-on time, ton = td ( on ) + tr

CONSTRUCTION, OPERATION & STATIC CHARACTERISTICS OF INSULATED

Fig.: Circuit Diagram to Obtain Characteristics

Fig. : Output Characteristics

Fig. : Transfer Characteristic

SWITCHING CHARACTERISTIC OF IGBT

Fig. : Switching Characteristics

TYPICAL RATINGS OF IGBT

trr Reverse recovery time 250nsec.

CONSTRUCTION & OPERATION OF THYRISTORS

SILICON CONTROLLED RECTIFIER (SCR)

The SCR is a four layer three terminal device with junctions

Fig.: Simplified model of a thyristor

Fig: V-I Characteristics

Fig.: Effects on gate current on forward blocking voltage

TWO TRANSISTOR MODEL OF TRANSISTOR

The general transistor equations are,

Considering NPN transistor of the equivalent circuit,

From the equivalent circuit, we see that

Case 2: With gate current I g applied.

SWITCHING CHARACTERISTICS (DYNAMIC CHARACTERISTICS) OF SCR

Fig.: Turn-on characteristics

THYRISTOR TURN OFF CHARACTERISTICS

First Subscript Second Subscript Third Subscript

F  Forward S Surge or non-repetitive

VT : On state voltage drop and is dependent on junction temperature.

VARIOUS GATE TRIGGERING METHODS OF SCR.

Fig.: Resistance firing circuit

Vg Vgt Vg Vg Vgp> Vgt

Vgp Vgp Vgt t t t

(a) No triggering of SCR (b) a = 900 (c) a < 900

At  t = a , VS = Vgt ,Vm = Vgp ( Q Vgt = Vgp sin a )

Fig.: RC half-wave trigger circuit

Fig.: Waveforms for RC half-wave trigger circuit

Fig: RC full-wave trigger circuit

VBB RB1 � RB1 �

Fig.: V-I Characteristics of UJT

UJT RELAXATION OSCILLATOR

EXPRESSION FOR PERIOD OF OSCILLATION ‘T’

VC = V final + ( Vinitial - V final ) e

t = T ,VC = VP ,Vinitial = VV , V final = VBB

DESIGN OF UJT OSCILLATOR

GATE TURN-OFF THYRISTORS

Where Cs is the snubber capacitance