1.
In parts of the processor, adders are used to calculate c) Accept a carry bit from a previous stage
____________
a) Addresses
b) Table indices
c) Increment and decrement operators
d) All of the Mentioned
Explanation: Adders are used to perform the operation of
addition. Thus, in parts of the processor, adders are used
to calculate addresses, table indices, increment and
decrement operators, and similar operations.
2. Total number of inputs in a half adder is __________
a) 2
b) 3
c) 4
d) 1
Explanation: Total number of inputs in a half adder is two.
Since, an EXOR gates has 2 inputs and carry is connected
with the input of EXOR gates. The output of half-adder is
also 2, them being, SUM and CARRY. The output of EXOR
gives SUM and that of AND gives carry.
3. In which operation carry is obtained?
a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction
Explanation: In addition, carry is obtained. For example: 1 0
1 + 1 1 1 = 1 0 0; in this example carry is obtained after 1st
addition (i.e. 1 + 1 = 1 0). In subtraction, borrow is
obtained. Like, 0 – 1 = 1 (borrow 1).
4. If A and B are the inputs of a half adder, the sum is given
by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Explanation: If A and B are the inputs of a half adder, the
sum is given by A XOR B, while the carry is given by A AND
B.
5. If A and B are the inputs of a half adder, the carry is
given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Explanation: If A and B are the inputs of a half adder, the
carry is given by: A(AND)B, while the sum is given by A XOR
B.
6. Half-adders have a major limitation in that they cannot
__________
a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
d) Accept a carry bit from the following stages
Explanation: Half-adders have a major limitation in that
they cannot accept a carry bit from a previous stage,
meaning that they cannot be chained together to add
multi-bit numbers. However, the two output bits of a half-
adder can also represent the result A+B=3 as sum and carry
both being high.
7. The difference between half adder and full adder is
__________
a) Half adder has two inputs while full adder has four
inputs
b) Half adder has one output while full adder has two
outputs
c) Half adder has two inputs while full adder has three
inputs
d) All of the Mentioned
Explanation: Half adder has two inputs while full adder has
three outputs; this is the difference between them, while
both have two outputs SUM and CARRY.
8. If A, B and C are the inputs of a full adder then the sum
is given by __________
a) A AND B AND C
b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C
Explanation: If A, B and C are the inputs of a full adder then
the sum is given by A XOR B XOR C.
9. If A, B and C are the inputs of a full adder then the carry
is given by __________
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
Explanation: If A, B and C are the inputs of a full adder
then the carry is given by A AND B OR (A OR B) AND C,
which is equivalent to (A AND B) OR (B AND C) OR (C AND
A).
10. How many AND, OR and EXOR gates are required for
the configuration of full adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
Explanation: There are 2 AND, 1 OR and 2 EXOR gates
required for the configuration of full adder, provided using
half adder. Otherwise, configuration of full adder would
require 3 AND, 2 OR and 2 EXOR.
11 Which of the circuits in figure (a to d) is the sum-of-
products implementation of figure (e)?
 13. The device shown here is most likely a ________

a) Comparator
b) Multiplexer
c) Inverter
d) Demultiplexer
Explanation: The given diagram is demultiplexer, because it
takes single input & gives many outputs. A demultiplexer is
a combinational circuit that takes a single output and
latches it to multiple outputs depending on the select lines.
14. What type of logic circuit is represented by the figure
shown below?

a) a
b) b
c) c a) XOR
d) d b) XNOR
Answer: d c) AND
Explanation: SOP means Sum Of Products form which d) XAND
represents the sum of product terms having variables in Explanation: After solving the circuit we get (A’B’)+AB as
complemented as well as in uncomplemented form. Here, output, which is XNOR operation. Thus, it will produce 1
the diagram of d contains the OR gate followed by the AND when inputs are even number of 1s or all 0s, and produce 0
gates, so it is in SOP form. when input is odd number of 1s.
12. Which of the following logic expressions represents the 15. For a two-input XNOR gate, with the input waveforms
logic diagram shown? as shown below, which output waveform is correct?

a) X=AB’+A’B
b) X=(AB)’+AB
c) X=(AB)’+A’B’
d) X=A’B’+AB a) d
Explanation: 1st output of AND gate is = A’B’ b) a
2nd AND gate’s output is = AB and, c) c
OR gate’s output is = (A’B’)+(AB) = AB + A’B’. d) b
 Explanation: When both inputs are same then the o/p is Hence, inputs are S0 and S1 are Low means 0, so output is
high for a XNOR gate. Y0 and rest all are HIGH.
i.e., A B O/P 19. The carry propagation can be expressed as ________
001 a) Cp = AB
010 b) Cp = A + B
100 c) All but Y0 are LOW
1 1 1. d) All but Y0 are HIGH
Thus, it will produce 1 when inputs are even number of 1s Explanation: This happens in parallel adders (where we try
or all 0s, and produce 0 when input is odd number of 1s. to add numbers in parallel via more than one adders). A
16. Which of the following combinations of logic gates can carry propagation occurs when carry from one adder needs
decode binary 1101? to be forwarded to other adder and that second adder is
a) One 4-input AND gate holding the computation (addition) because carry from
b) One 4-input AND gate, one inverter first adder has not come yet. So, there is a slight delay for
c) One 4-input AND gate, one OR gate second adder and this is known as carry propagation.
d) One 4-input NAND gate, one inverter 20. 3 bits full adder contains ________
Explanation: For decoding any number output must be a) 3 combinational inputs
high for that code and this is possible in One 4-input NAND b) 4 combinational inputs
gate, one inverter option only. A decoder is a c) 6 combinational inputs
combinational circuit that converts binary data to n-coded d) 8 combinational inputs
data upto 2n outputs. Explanation: Full Adder is a combinational circuit with 3
17. What is the indication of a short to ground in the input bits and 2 output bits CARRY and SUM. Three bits full
output of a driving gate? adder requires 23 = 8 combinational circuits.
a) Only the output of the defective gate is affected 21. A latch is an example of a ___________
b) There is a signal loss to all load gates a) Monostable multivibrator
c) The node may be stuck in either the HIGH or the LOW b) Astable multivibrator
state c) Bistable multivibrator
d) The affected node will be stuck in the HIGH state d) 555 timer
Explanation: Short to ground in the output of a driving Explanation: A latch is an example of a bistable
gate indicates of a signal loss to all load gates. This results multivibrator. A Bistable multivibrator is one in which the
in information being disrupted and loss of data. circuit is stable in either of two states. It can be flipped
18. For the device shown here, assume the D input is LOW, from one state to the other state and vice-versa.
both S inputs are LOW and the input is LOW. What is the 22. Latch is a device with ___________
status of the Y’ outputs? a) One stable state
b) Two stable state
c) Three stable state
d) Infinite stable states
Explanation: Since, a latch works on the principal of
bistable multivibrator. A Bistable multivibrator is one in
which the circuit is stable in either of two states. It can be
flipped from one state to the other state and vice-versa. So
a) All are HIGH a latch has two stable states.
b) All are LOW 23. Why latches are called a memory devices?
c) All but Y0 are LOW a) It has capability to stare 8 bits of data
d) All but Y0 are HIGH b) It has internal memory of 4 bit
Explanation: In the given diagram, S0 and S1 are selection c) It can store one bit of data
bits. So, d) It can store infinite amount of data
I/P S0 S1 O/P Explanation: Latches can be memory devices, and can store
D = 0 0 0 Y0 one bit of data for as long as the device is powered. Once
D = 0 0 1 Y1 device is turned off, the memory gets refreshed.
D = 0 1 0 Y2 24. Two stable states of latches are ___________
D = 0 1 1 Y3 a) Astable & Monostable
b) Low input & high output 30. The first step of analysis procedure of SR latch is to
c) High output & low output ___________
d) Low output & high input a) label inputs
Explanation: A latch has two stable states, following the b) label outputs
principle of Bistable Multivibrator. There are two stable c) label states
states of latches and these states are high-output and low- d) label tables
output. Explanation: All flip flops have at least one output labeled
25. How many types of latches are ___________ Q (i.e. inverted). This is so because the flip flops have
a) 4 inverting gates inside them, hence in order to have both Q
b) 3 and Q complement available, we have atleast one output
c) 2 labelled.
d) 5 31. The inputs of SR latch are ___________
Explanation: There are four types of latches: SR latch, D a) x and y
latch, JK latch and T latch. D latch is a modified form of SR b) a and b
latch whereas, T latch is an advanced form of JK latch. c) s and r
26. The full form of SR is ___________ d) j and k
a) System rated Explanation: SR or Set-Reset latch is the simplest type of
b) Set reset bistable multivibrator having two stable states. The inputs
c) Set ready of SR latch are s and r while outputs are q and q’. It is clear
d) Set Rated from the diagram:
Explanation: The full form of SR is set/reset. It is a type of digital-circuits-questions-answers-latches-q7
latch having two stable states. 32. When a high is applied to the Set line of an SR latch,
27. The SR latch consists of ___________ then ___________
a) 1 input a) Q output goes high
b) 2 inputs b) Q’ output goes high
c) 3 inputs c) Q output goes low
d) 4 inputs d) Both Q and Q’ go high
Explanation: SR or Set-Reset latch is the simplest type of Explanation: S input of a SR latch is directly connected to
bistable multivibrator having two stable states. the output Q. So, when a high is applied Q output goes
The diagram of SR latch is shown below: high and Q’ low.
digital-circuits-questions-answers-latches-q7 advertisement
28. The outputs of SR latch are ___________ 33. When both inputs of SR latches are low, the latch
a) x and y ___________
b) a and b a) Q output goes high
c) s and r b) Q’ output goes high
d) q and q’ c) It remains in its previously set or reset state
Explanation: SR or Set-Reset latch is the simplest type of d) it goes to its next set or reset state
bistable multivibrator having two stable states. The inputs Explanation: When both inputs of SR latches are low, the
of SR latch are s and r while outputs are q and q’. It is clear latch remains in it’s present state. There is no change in
from the diagram: the output.
digital-circuits-questions-answers-latches-q7. 34. When both inputs of SR latches are high, the latch goes
29. The NAND latch works when both inputs are ___________
___________ a) Unstable
a) 1 b) Stable
b) 0 c) Metastable
c) Inverted d) Bistable
d) Don’t cares Explanation: When both gates are identical and this is
Explanation: The NAND latch works when both inputs are “metastable”, and the device will be in an undefined state
1. Since, both of the inputs are inverted in a NAND latch. for an indefinite period.