Unit-1

• difference between multiprocessors and multicomputers.

• Parity bit, even and odd parity bit generation and design 3-bit odd
parity generator and checker. Distinguish error detection and
correction codes.

• Draw diagram & explain functional units of computer. Bus

structures, arbitration methods.

• Performance measure. Basic operational concepts of computer with

neat diagram.

• Various representations of signed number. Conversions from hex to

octal, decimal to octal, hex.

• Discuss Flynn’s classification of computers. Communication

topologies used in multiprocessors.

• Explain about sign magnitude and 2’s complement approaches for

representing fixed point numbers. Why 2’s compl. is preferable?

• Addition overflow.

Unit 2

• design circuit transferring data from 4-bit register(uses d-flipflops)

to a register uses RS flip flop.

• RTL languages, branching functions statements. Memory reference

instructions. Interrupt cycle.

• Design register selection circuit to transfer content from 4-bit

register to Bus.explain.

• Design circuit to increment, decrement, complement and clear 4-bit

registers using RS.

• Design circuit of parallel load into 4-bit registers from a bus. Assume
d-flipflops,show selection bits logic.

• How many interrupts are available? What is PSW? Explain superior

mode and supervisory mode.

• Write RTL statements for BUN,BSA,ISZ. Explain X=(A+B*C)/(A-B-C)

in stack
 • Explain various addressing modes. List and explain arithmetic micro
operations.

Unit 3

• microprogram sequencer with diagram. Write micro-routines to

fetch an instruction.

• Compare hardwired control and micro programmed control unit.

• Explain control word, control memory, control address register and

micro instruction.

• Explain design of micro programmed control unit. Write add and sub
subroutines. explain horizontal and vertical instructions.

• Subroutine register in control unit. Mapping technique to generate

next address.

• Pipeline register-explain? Microinstruction sequencing techniques,

specifically variable format address microinstruction.

Unit 4

• fast multiplication circuits. About array multipliers.

• Booths algorithm. Problem .

• Draw circuit for 9’s compl. Arithmetic overflow, divide overflow

with examples.

• Restoring method of division with two 4-bit numbers. Divide

problem.

• How many bits needed for storing the result of add, sub, mul, div of
two n-bit unsigned numbers?

• With Flow chart explain mul of two signed magnitude fixed

numbers.

• With flow chart explain add&sub of signed fixed numbers. Draw

circuit for BCD add&sub explain the method.

Unit 5

discuss

Write through cache

 Write back cache

 Memory management unit

 Flash memory

 Page table, TLB, locality of reference

• Compare paging and segmentation, cache mapping techniques.

• RAID, replacement algorithms for cache.

• Virtual memory techniques. Paging technique.

• DRAM- synchronous and asynchronous.

• Explain with applications.

 ROM

 PROM

 EPROM, EEPROM.

Unit 6

DMA, DMA transfers, explain Daisy chaining with neat sketch.

Parallel priority interrupt, interrupt cycle.

Modes of transfer. What is polling? I/o communication techniques with

advantages& disadvantages?

Asynchronous serial transfer, communication interface.

Differentiate cycle stealing and burst transfers of DMA.

Explain

• Isolated vs memory mapped I/o, interrupt initiated i/o

• I/O bus vs memory bus, programmed i/o.

• I/O Interface, IOP, IBM 370 I/O channel

• Peripheral devices, DMA controller.

Unit 7

 vector processing, array processors.

  Pipelining? Explain 4-segment instruction pipeling.
Flynn’s classification of computers.

 RISC pipelining, arithmetic pipeline.

 Explain 3-segment instruction pipeline with timing

diagram.

 SIMD array processor. Pipeline for floating point

add&sub.

 Explain

• Data dependency, operand forwarding

• Delayed branch, load

• Branch target buffer, pre-fetch target buffer

• Hardware interlocks

• Pipeline conflicts

Explain related to vector processing

 Super computers

 Vector operations

 Matrix multiplication

 Memory interleaving

Unit 8

o differentiate tightly coupled and loosely coupled multiprocessors.

o Hypercube n/w operation , cross bar switch with neat sketch. List
all parts available fro node 7 to node 9 that use minimum number
of intermediate nodes for 4-dimensional hypercube n/w.

o Explain multipoint memory organization with diagram.

o 8x8 omega n/w, solution to cache coherence.

o Different kinds of Multi stage switching n/ws. Compare their

functioning.
o Binary tree 2x2 switches. How many switch points are there in a
cross bar switch n/w that connect ‘p’ processors to ‘m’ memory
modules.

o Write short notes on

• Cache coherence Shared memory multiprocessors

• Critical section

• Inter process communication.