Beruflich Dokumente
Kultur Dokumente
EX.No:1
DATE : ADDER
AIM:
To Simulate VHDL Program for Adder Using ModelSim SE 6.0a tool and verify the
output.
APPARATUS REQUIRED:
1. EDA Tool: ModelSim SE 6.0a
2. PC : WINDOWS OS
PROCEDURE:
PROGRAM:
Half Adder(VHDL) using dataflow:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity halfadder is
port ( a,b : in std_logic;
sum, carry : out std_logic);
end halfadder;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fulladder is
port ( a,b,c : in std_logic;
sum, carry : out std_logic);
end fulladder;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity and1 is
port ( a : in std_logic;
b : in std_logic;
y : out std_logic);
end and1;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity xor1 is
port ( a : in std_logic;
b : in std_logic;
y : out std_logic);
end xor1;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity halfadder is
port ( a,b : in std_logic;
sum, carry : out std_logic);
end halfadder;
component xor1
port(a,b: in std_logic; y: out std_logic);
end component;
component and1
port(a,b: in std_logic; y: out std_logic);
end component;
begin
x1: xor1 port map(a,b,sum);
a1: and1 port map(a,b,carry);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity and1 is
port ( a : in std_logic;
b : in std_logic;
y : out std_logic);
end and1;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity or1 is
port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or1;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity xor1 is
port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xor1;
architecture behavioral of xor1 is
begin
y<= a xor b xor c;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fulladder is
port ( a, b, c : in std_logic;
sum, carry : out std_logic);
end fulladder;
ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50
RESULT:
Thus the half adder and full adder program using ModelSim SE 6.0a was stimulated and
output was verified.
EX.No:2
DATE : Multiplexer and Demultiplexer
AIM:
To Simulate VHDL Program for Multiplexer and Demultiplexer Using ModelSim SE
6.0a tool and verify the output.
APPARATUS REQUIRED:
1. EDA Tool: ModelSim SE 6.0a tool
2. PC:WINDOWS OS
PROCEDURE:
PROGRAM:
2 to 1 MUX (VHDL) using dataflow:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux 2 to 1 is
port ( i1,i2,s : in std_logic;
y : out std_logic);
end mux 2 to 1;
architecture behavioral of mux 2 to 1 is
begin
end behavioral;
entity mux 4 to 1 is
port ( i1,i2,i3,i4,s1,s2 : in std_logic;
y : out std_logic);
end mux 4 to 1;
begin
y<=(not(s1) and not(s2) and i1) or (not(s1) and (s2) and i2) or (s1 and not(s2) and i3) or
(s1 and s2 and i4);
end behavioral;
entity mux 8 to 1 is
port(a : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(2 downto 0);
y : out std_logic);
end mux 8 to 1;
architecture behavioral of mux 8 to 1 is
begin
process(sel,a)
begin
case sel is
when"000"=>
y<=a(0);
when"001"=>
y<=a(1);
when"010"=>
y<=a(2);
when"011"=>
y<=a(3);
when"100"=>
y<=a(4);
when"101"=>
y<=a(5);
when"110"=>
y<=a(6);
when"111"=>
y<=a(7);
when others=>
end case;
end process;
end behavioral;
entity demux 1 to 2 is
port ( i, s : in std_logic;
y1,y2 : out std_logic);
end demux 1 to 2;
begin
y1<= i and (not(s));
y2<= i and s;
end behavioral;
1 to 4 DEMUX (VHDL) using dataflow:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity demux 1 to 4 is
port ( i,s1,s0 : in std_logic;
y1,y2,y3,y4 : out std_logic);
end demux 1 to 4;
begin
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity demux 1 to 8 is
port ( i,s0,s1,s3 : in std_logic;
y1,y2,y3,y4,y5,y6,y7,y8 : out std_logic);
end demux 1 to 8;
begin
y1<= i and (not(s2)) and (not(s1)) and (not(s0));
y2<= i and (not(s2)) and (not(s1)) and (s0);
y3<= i and (not(s2)) and (s1) and (not(s0));
y4<= i and (not(s2)) and (s1) and (s0);
y5<= i and (s2) and (not(s1)) and (not(s0));
y6<= i and (s2) and (not(s1)) and (s0);
y7<= i and (s2) and (s1) and (not(s0));
y8<= i and (s2) and (s1) and (s0);
end behavioral;
ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50
RESULT:
Thus the Multiplexer and Demultiplexer program using ModelSim SE 6.0a was
stimulated and output was verified.
EX.No:3
DATE : Encoder and Decoder
AIM:
To Simulate VHDL Program for Encoder and Decoder Using ModelSim SE 6.0a tool and
verify the output.
APPARATUS REQUIRED:
3. EDA Tool: ModelSim SE 6.0a tool
4. PC:WINDOWS OS
PROCEDURE:
PROGRAM:
2 to 4 Decoder:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder 2 to 4 is
port ( e,i1,i2 : in std_logic;
o1,o2,o3,o4 : out std_logic);
end decoder 2 to 4;
architecture behavioral of decoder 2 to 4 is
begin
o1<= e and (not i1) and (not i2);
o2<= e and (not i1) and i2;
o3<= e and i1 and (not i2);
o4<= e and i1 and i2;
end behavioral;
3 to 8 Decoder:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder 3 to 8 is
port ( e,i1,i2,i3 : in std_logic;
o1,o2,o3,o4,o5,o6,o7,o8 : out std_logic);
end decoder 3 to 8;
2 to 4 Encoder:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity encoder 2 to 4 is
port ( i1,i2,i3,i4 : in std_logic;
o1,02 : out std_logic);
end encoder 2 to 4;
architecture behavioral of encoder 2 to 4 is
begin
o1<=(not (i1) and (i3) and not (i2) and not(i1)) or (i4 and not(i3) and not (i2) and not (i1));
o2<=(not (i4) and not(i3) and (i2) and not(i1)) or (i4 and not(i3) and not (i2) and not (i1));
end behavioral;
ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50
RESULT:
Thus the Encoder and Decoder program using ModelSim SE 6.0a was stimulated and
output was verified.
EX.No:4
DATE : Multiplier
AIM:
To Simulate VHDL Program for Multiplier Using ModelSim SE 6.0a tool and verify the
output.
APPARATUS REQUIRED:
5. EDA Tool: ModelSim SE 6.0a tool
6. PC:WINDOWS OS
PROCEDURE:
PROGRAM:
Unsigned 8 x 4 bit Multiplier:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mult is
port(A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(3 downto 0);
RES : out std_logic_vector(11 downto 0));
end mult;
architecture archi of mult is
begin
RES <= A * B;
end archi;
ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50
RESULT:
Thus the Multiplier program using ModelSim SE 6.0a was stimulated and output was
verified.
EX.No:5
DATE : Flip Flops
AIM:
To Simulate VHDL Program for Flip Flops Using ModelSim SE 6.0a tool and verify the
output.
APPARATUS REQUIRED:
1. ModelSim SE 6.0a tool
2. PC:XP/WINDOWS
PROCEDURE:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dff is
port ( d,res,clk : in std_logic;
q : out std_logic);
end dff;
entity jkff is
port(j,k,clk,reset : in std_logic;
q,qn : out std_logic);
end jkff;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity srff is
port (s,r,clk : in std_logic;
q,qb : buffer std_logic);
end srff;
begin
q<= not((r and clk) or qb);
qb<= not((s and clk) or q);
end behavioral;
entity tff is
port ( t,clk : in std_logic;
q : out std_logic);
end tff;
ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50
RESULT:
Thus the Flip Flops using ModelSim SE 6.0a was stimulated and output was verified.
EX.No:6
DATE : COUNTER
AIM:
To Simulate VHDL Program for Counter Using ModelSim SE 6.0a tool and verify the
output.
APPARATUS REQUIRED:
1. ModelSim SE 6.0a tool
2. PC:XP/WINDOWS
PROCEDURE:
PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity upcounter is
port ( clk,clr : in std_logic;
q : inout std_logic_vector (2 downto 0));
end upcounter;
architecture behavioral of upcounter is
begin
process(clk)
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity downcounter is
port ( clk,clr : in std_logic;
q : inout std_logic_vector (2 downto 0));
end downcounter;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bcd is
port ( clk,clr : in std_logic;
q : inout std_logic_vector (3 downto 0));
end bcd;
begin
process(clk)
variable temp: std_logic_vector (3 downto 0):="0000";
begin
if (rising_edge (clk)) then
if clr='0' then
case temp is
when "0000"=>temp:="0001";
when "0001"=>temp:="0010";
when "0010"=>temp:="0011";
when "0011"=>temp:="0100";
when "0100"=>temp:="0101";
when "0101"=>temp:="0110";
when "0110"=>temp:="0111";
when "0111"=>temp:="1000";
when "1000"=>temp:="1001";
when others=>temp:="0000";
end case;
else
temp:="0000";
end if;
end if;
q<=temp;
end process;
end behavioral;
entity syn4 is
port ( clk,rst : in std_logic;
q : inout std_logic_vector (2 downto 0));
end syn4;
begin
process(clk)
end behavioral;
Sequence: 01357
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity seq is
port ( clk,clr : in std_logic;
q : inout std_logic_vector (2 downto 0));
end seq;
begin
process(clk)
end behavioral;
ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50
RESULT:
Thus the Counter program using ModelSim SE 6.0a was stimulated and output was
verified.
EX.No:7
DATE : SHIFT REGISTERS
AIM:
To Simulate VHDL Program for Shift Registers Using ModelSim SE 6.0a tool and verify
the output.
APPARATUS REQUIRED:
PROCEDURE:
PROGRAM:
REGISTER:
library ieee;
use ieee.std_logic_1164.all;
entity reg is
port(clk : in std_logic;
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0);
ld : in std_logic) ;
end reg;
architecture behavioral of reg is
begin
generic_register: process(clk, input, ld)
begin
if (rising_edge(clk)) then
if (ld = '1') then
output <= input ;
end if ;
end if ;
end process ;
end behavioral ;
library ieee;
use ieee.std_logic_1164.all;
entity siso is
port(C, SI : in std_logic;
SO : out std_logic);
end siso;
begin
process (C)
begin
if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end process;
SO <= tmp(7);
end archi;
8-bit Shift Register with Positive-Edge Clock, Serial In,
and Parallel Out:
library ieee;
use ieee.std_logic_1164.all;
entity sipo is
port(C, SI : in std_logic;
PO : out std_logic_vector(7 downto 0));
end sipo;
begin
process (C)
begin
if (C'event and C='1') then
tmp <= tmp(6 downto 0) & SI;
end if;
end process;
PO <= tmp;
end archi;
ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50
RESULT:
Thus the Shift Registers program using ModelSim SE 6.0a was stimulated and output
was verified.
EX.No:8
DATE : CMOS INVERTER
AIM:
To Design CMOS Inverter Using Multisim Software and verify the output.
APPARATUS REQUIRED:
1. Multisim Software
2. PC:XP/WINDOWS
Inverter Circuit:
DC Operating Point:
ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50
RESULT:
Thus the CMOS Inverter is Designed using Multisim and output was verified.
EX.No:9
DATE : CMOS NAND and NOR Gates
AIM:
To Design CMOS NAND and NOR Gates Using Multisim Software and verify the
output.
APPARATUS REQUIRED:
3. Multisim Software
4. PC:XP/WINDOWS
RESULT:
Thus the CMOS NAND and NOR Gates is Designed using Multisim and output was
verified.
EX.No:10
DATE : CMOS D Latch
AIM:
To Design CMOS D Latch using Multisim Software and verify the output.
APPARATUS REQUIRED:
5. Multisim Software
6. PC:XP/WINDOWS
RESULT:
Thus the CMOS D Latch is Designed using Multisim and output was verified.
EX.No:11
DATE : 4 BIT ADDER
AIM:
To Study the synthesis of a VHDL Program Using tools in XILINX ISE 8.2i Software.
APPARATUS REQUIRED:
1. XILINX ISE 8.2i tool
2. PC:XP/WINDOWS
PROCEDURE:
PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity fadd4 is
port(a,b : in std_logic_vector(3 downto 0);
cin : in std_logic;
s : out std_logic_vector(3 downto 0);
cout : out std_logic);
end fadd4;
architecture structural of fadd4 is
component fulladd
port(a,b,cin : in std_logic;
sum,cout : out std_logic);
end component;
signal c1,c2,c3: std_logic;
begin
end structural;
ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50
RESULT:
Thus the 4 Bit Adder program using XILINX ISE 8.2i Software was stimulated and
output was verified.
EX.No:12
DATE : Real Time Clock
AIM:
To Study the synthesis of a VHDL Program Using tools in XILINX ISE 8.2i Software.
APPARATUS REQUIRED:
3. XILINX ISE 8.2i tool
4. PC:XP/WINDOWS
PROCEDURE:
PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rtc_im is
port(reset,clk_4m,load,control:in std_logic;
rtc_seg:out std_logic_vector(7 downto 0);
rtc_dis:out std_logic_vector(5 downto 0));
end rtc_im;
enable <= '1' when pulsegen = "1111010000100100000000" else --enable signal for sec1
counter
'0';
--************************ second_cntr1 *************************
p1:process (reset,clk_4m,sec1_rg,enable,load) --decade counter
begin
if (reset = '1') then
sec1_rg <= "0000";
elsif load = '1' then
sec1_rg <= "0100";
ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50
RESULT:
Thus the Real time clock program using XILINX ISE 8.2i Software was stimulated and
output was verified.