NEW 4-TRANSISTOR XOR AND XNOR DESIGNS
Hung Tien Bui, Abdul Karim Al-Sheraidah, and Yuke Wang
Dept. of Computer Science & Engineering, Florida Atlantic University
777 Glades Rd., Boca Raton, Florida, 3343 1 USA
E-mail: yuke@cse..fau.edu
Abstract
Exclusive-OR and exclusive-NOR gates are important
in digital circuits. This paper proposes a new set of
low power 4-transistor XOWXNOR gates. Simulations
have been performed on the circuits along with 10
other XOR gates. The results show that the new
XOR/XNOR gates consistently consume less power
than any other XOR/XNOR gate known at the time of
publication. In fact, it consumes up to more than 3
times less power than the complementary CMOS
implementation and can have 34% better propagation
delay. The static energy-recovery XOR gate, which is
the second least power-consuming, dissipates 10%
more power than the new gater.
I INTRODUCTION
The exclusive-OR (XOR) and exclusive-NOR
(XNOR) gates are well known for their roles in larger
circuits such as full adders and parity checkers [l]. The
performance of these larger circuits is affected by the
individual performance of the XOWXNOR gates that
are included in them. The XOWXNOR gates can be
implemented using AND, OR and NOT gates, only the
redundancy is large [I]. Therefore, an optimized
design of the XOWXNOR gates can certainly benefit
the performance of the larger circuits that they are part
of.
The implementation of these XOWXNOR gates
can be done in different ways. Complementary CMOS
uses dual networks to implement a given function. A
first part consists solely of PMOS transistors while a
second part consists of NMOS transistors. This
technique is popular and produces results that are
widely accepted. Another logic style, known as pass-
transistor logic, is also commonly used. It differs from
complementary CMOS in that the source side of the
MOS transistor is connected to an input line instead of
being connected to power lines. Another important
difference is that only one pass-transistor network
(either NMOS or PMOS) is required [3]. With time,
several other designs have appeared and each has
claimed to be more performant than the last.
In this paper, we propose a new set of
XOWXNOR gates that uses only 4 transistors, the
smallest size known to date for an XOR/XNOR gate
that uses single-rail inputs. Its performance is
evaluated through simulation and the results are
0-7803-6470-8/00/ $10.00 0 2000 IEEE
compared with the simulation results of IO other
designs.
The paper is divided as follows: Section 2
describes the work that has previously been done on
XOR/XNOR gates. In section 3, we propose a new set
of XOR/XNOR gates and we evaluate its performance
with respect to other XORIXNOR gates. The
experiments are described and the simulation results
are analyzed in Section 4. In Section 5, we draw the
conclusions.
n PREVIOUS WORK
The XOR and XNOR gates implement hnctions
that are complementary. The XNOR gate yields a logic
1 only when both signals are equal whereas the XOR
gate yields a logic 0 for the same inputs. Using A and B
as inputs, XOR and XNOR outputs can be generated
using this equation:
A e B = (2 A B ) V ( A A 1) (1)
A@B = (AhB)v ( A A E ) (2)
Numerous XOWXNOR gates have been proposed
throughout the years [I], [2], [3], [4], [5]. They vary in
design approaches and transistor counts. Among these,
4 are created using complementary CMOS design
techniques and they are shown in Figures 3 (a) [3] and
(b) [4], (c) [4] and (d) [2]. Complementary pass-
transistor logic (CPL) is used to build (e), [3], (r) [3]
and (g). A variation of CPL, called double pass-
transistor logic (DPL), is used to make (h) [3]. Designs
(i) [ 11 and (i) [ 11 are designs that use only 4 transistors,
which is the lowest transistor count for XOWXNOR
gates when using single rail inputs.
I XORGnte I TrarrsIstorCom I CrltlcdPnthSlze I CrltlcalPnthOccllrm I
(s) I 12 3 4 (Inputs All I@$
I (C) I 8 I 3 I IOnputa.04 I
I (a) I 0 I 3 I 4flnputa:Alllnmns) I
Figure 1. Information on XOR Gates
To perform a transistor count, it is essential to modify
the circuits and make them follow the same
conventions. The circuits using double rail inputs are
changed into single rail inputs with added inverters.
The inverters consist of 2 transistors and the
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 T h e Second IEEE Asia Pacific Conference on ASICs / Aug 28-30, 2000
transmission gates consist of 2 transistors. The
transistor count for these XOR gates is provided in
Figure 1. The last element of that table, (k), is the new
XOR gate that is presented in the next section.
111 DESIGN AND ANALYSIS OF NEW
XORKNOR GATES
A new XOR is presented in Figure 2. It is related
to design (i) in Figure 3 and the only difference is that
the VDD connection in design (i) is connected to the
input A . Because it has no power supply, it is referred
to as the Powerless XOR, or P-. Similarly, we propose
a new XNOR gate that is named Groundless XNOR,
or G-, because there is no ground.
I
YOD
m
rrI
Figure 2. New XOR/XNOR Gates
In the following, we analyze the performance of
the different XOR gates shown in Figure 3 in terms of
power consumption and propagation delay. The
evaluation is done in both in theory and experimentally
through simulations.
Equation (3) [7] is used to estimate the power
consumption of a circuit.
* O*h' +,' * hm+Z%d * YDD (3)
PI,,,,,, = (IC,* F.txm"r
In this equation, C, is the load capacitance, V, is the
.-
m (D
Figure 3. Previous XORKNOR Gates
26
voltage swing, P, is the probability of a switch, FClk is
the clock frequency, I,, is the short-circuit current, I,eak
is the leakage current and VDD is the supply voltage.
The main components of the power dissipation are the
is, and v , - ~ components.
~,~~ The ileakcomponent of the
equation is very low and is sometimes omitted in
literature.
The voltage swing of a circuit is the change in
voltage that occurs during a transition. It is equal to the
voltage difference between a IogiQnd a logie
When the signal transmission is perfect, the logils
equal to VDD and the log& equal to VSS. The
voltage swing is therefore equal to the supply voltage
and so, a reduction in supply voltage results in lower
power dissipation.
The voltage swing is also reduced when the
signals are not fully transmitted. This occurs when an
NMOS transmits a logic '1' or a PMOS transmits a
logic '0'. A circuit that has a lesser driving capability
often dissipates less power. CMOS designs usually
have several series connected transistors at the output.
This results in weaker driving capability than if it is
driven by an inverter or a buffer, but yet not as weak as
the previous case.
The short-circuit current is established by a direct
path between VDD and VSS. The repeated presence of
such connection causes higher power consumption. A
large part of the power consumption is caused by the
frequent switching of inverters, in particular, ones that
are connected to the input ports. This part of the power
,A
P-
"
is less when direct paths from VDD to VSS are limited
or become non-existent when either VDD or VSS is
not present, as in the case of the static energy-recovery
XOR (Figure 2) and P- XOR (Figure 3).
Figure 4 summarizes the key elements that
dissipate power. The Incomplete Voltage Swings
column only takes into consideration cases where a
logic '1' is transmitted through an NMOS and where a
'0' is transmitted through a PMOS.The Source of is,
column identifies the main transitions that cause short-
circuit current. These are the signals that momentarily
connect VDD and VSS every time the states change.
Only short-circuit currents generated by
comDlementary CMOS inverters are considered in
order

INPUTS XOR XNOR

Figure 4. Key Power Dissipation Elements

The speed is evaluated using the critical path. A

list of critical paths is given in Figure 1. The transistors
in the path are counted as being part of the critical path
when they transmit a signal that contributes to
generating the output.
According to the table, the fastest gate is (j)
because of the presence of only 1 critical path
encounter that consists of 2 transistors. The (i) design
and the new P-IG- design are also expected to be fast.
Figure (f) contains a feedback loop to correct the
voltage swing and this will cause the circuit to be slow.
According to Figure 1, (b) is also expected to be slow.

IV EXPERIMENT DESCRIPTION
The simulation environment is setup to measure
performance in terms of propagation delay and power
dissipation. Simulations are performed at varying
frequencies to take into account the fact that different
applications work at different frequencies. The same
applies to capacitive loading conditions. Simulation
conditions are shown in Figure 5 .
Lopd I OOlPP I oar@I omr@ I OlP I OJPp I OS@ I
-F 1% 5m 10- zm SO- I W m la*

For a measurement in propagation delay, we must

take into consideration the change of inputs that results
in a change of output. The delay is measured between

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 T h e Second IEEE Asia Pacific Conference o n ASICs / Aug 28-30, 2000

ranked in terms of power, delay and power-delay POWER DELAY POWER-DELAY

product in Figure 12.
L m-
"r-

:i
02
Figure 12. Ranking for XOR/XNOR Gates at O.OlpF

V CONCLUSIONS
In this paper, we proposed new 4-transistor XOR
and XNOR gates. The XOR gate was simulated and
the results, in terms of power consumption and
propagation delay, were compared with the
performance of 11 other XOR gates. The results show
that the new P-/G- XOR always consumes less power
than any other XOR gates. In terms of propagation
I L
'I delay, design (i) is the XOR gate that is the fastest. The
proposed P-/G- XOR is slower than the other 2 4-
transistor XOR gates.

REFERENCES
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[ 5 ] H. T. Bui, A. K. AI-Sheraidah and Y. Wang.
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-F Mr) .
.r _
k Wesley, 1993
[7] A.P. Chandrakasan, S. Sheng and R. W.
Figure 11. Power-Delay Product at 0.OlpF
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