Midsemester Examination - Solutions

Question 1 (10 marks):

(a) Using two’s complement representation of signed 4-bit numbers including 1 sign bit, perform
the following arithmetic operation using two’s complement arithmetic step by step and find the
value of x, explaining how you interpret the final carry generated by the addition process:
x = 110 – 210 + 410 – 610 + 710 [4]
0001 1111 0011 1101
1110 0100 1010 0111
1111 1 0011 1101 1 0100
Discard Discard
Discarding the Carry bit beyond the Sign bit after every addition, we get x = 0100 (410).
(b) A computer, using r’s complement representation of numbers consisting of the Sign bit and two
digits, gives the following results expressed in r’s complement form:
m + n = 064r, m – n = 022r, n – m = 145r.
Express n – m as a negative decimal number in terms of the unknown r. [1]
Hence find the values of
(i) the radix r, [1]
(ii) the two numbers m and n, expressed in terms of the radix r, and [2]
(iii) – m – n in r’s complement form by performing r’s complement arithmetic. [2]

Using decimal representation, m + n = 6r + 4, m – n = 2r + 2, n – m = – r2 + 4r + 5. [1]

(i) (m – n) + (n – m) = 2r + 2 + (– r2 + 4r + 5) = 0  r2 – 6r – 7 = (r – 7)(r + 1) = 0
 r = 7 or r = – 1. Taking the positive answer, r = 7. [1]
(ii) Using this value of r, m + n = 4610 and m – n = 1610  m = 3110 = 437 & n = 1510 = 217. [2]
(iii) Radix complement arithmetic:
– m = 1247 and – n = 1467  – m – n = 3037.
Discarding the overflow, – m – n = 1037 (= – 4610). [2]
Question 2 (10 marks):
A student staying in a hostel has to make up his mind about his dinner. If he has enough money (M)
and at least three of his friends (F) also agree to go out for dinner, he will have dinner with his friends
in a restaurant outside the campus. However, he will not go out if it is raining (R). If he is not able to
go out, but at least three of his friends agree to join him (J), he will order home delivery of food from
outside. But if the kind of food he wanted is not available on home delivery (K), or if the general
feeling is that the food in the hostel mess is good on that day (G), he will have his dinner in the hostel
mess. Let his decision be denoted by a 2-bit output D1D0:
D1D0 = 00  He eats in the hostel mess,
D1D0 = 01  He goes out to have dinner in a restaurant, and
D1D0 = 10  He orders food through home delivery.
(a) Assign binary variables to represent the various conditions using the letters indicated in
parentheses above, and obtain both POS and SOP expressions for D1 and D0 in terms of these
variables by logical reasoning, without using any map representation. (It is anyway difficult
to construct a map for 6 variables). [3 + 3]
Let the binary variables representing the various conditions be defined as follows.
M = 1  he has enough money,
F = 1  at least three of his friends agree to go out,
R = 1  it is raining,
J = 1  at least three of his friends agree to join him,
K = 1  the kind of food he wanted is available on home delivery and
G = 1  the food in the hostel mess is good.
As the combination D1D0 = 11 is immaterial, one can draw the following conclusions.
1. He goes out to have dinner in a restaurant if D0 = 1, irrespective of the value of D1.
2. He orders food through home delivery if D1 = 1, irrespective of the value of D0.
3. He eats in the hostel mess if D1 = 0 and D0 = 0.
 D0 = M F R’ (has money, friends agree and it is not raining).
Clearly this expression qualifies both as SoP and as PoS. [2]
D1 = D0’ J K G’ (cannot go out, friends join, kind of food available, mess food not good).
Substituting for D0, we can get the PoS expression for D1:
D1 = (M’ + F’ + R) J K G’. The SoP expression is obtained by expanding the expression. [2]
D1 = M’ J K G’ + F’ J K G’ + R J K G’. [2]
(b) Given Quad 2-input and Dual 4-input gate chips, find out the required numbers of different types
of gates and hence the chip count for a two-level realisation:
(i) using NAND gates only and (ii) using NOR gates only. [2 + 2]

(i) NAND Realisation (ii) NOR Realisation

Output 2-input Gates 4-input Gates 2-input Gates 4-input Gates
D1 3 (NOT) 4 4 (NOT) 2
D0 2 (NOT) 1 2 (NOT) 1
Total Gates 5 5 6 3
Total Chips 4 (= 1 + 3) 4 (= 2 + 2)
Question 3 (10 marks):
Decimal numbers can be coded in various binary codes. The excess-3 BCD and the 5-4-2-1 codes
assign codes for the decimal digits 0-1-2-3-4-5-6-7-8-9 as follows.
Excess-3 (E3 E2 E1 E0) : 0011-0100-0101-0110-0111-1000-1001-1010-1011-1100,
5-4-2-1: (C3 C2 C1C0) : 0000-0001-0010-0011-0100-1000-1001-1010-1011-1100.
You are required to design a circuit for generating 5-4-2-1 code from excess-3 code.
(a) Construct Karnaugh maps for the four output variables C3 C2 C1C0 in terms of the four input
variables E3 E2 E1 E0, marking as “don’t care” the combinations that do not correspond to any
decimal digit. [4]

E1 E0 0 0 01 11 10 E1 E0 0 0 01 11 10
E3 E2 E3 E2
00 ϕ ϕ 0 ϕ 00 ϕ ϕ 0 ϕ

01 0 0 0 0 01 0 0 1 0
C3 C2
11 1 ϕ ϕ ϕ 11 1 ϕ ϕ ϕ

10 1 1 1 1 10 0 0 0 0

E1 E0 0 0 01 11 10 E1 E0 0 0 01 11 10
E3 E2 E3 E2
00 ϕ ϕ 0 ϕ 00 ϕ ϕ 0 ϕ

01 0 1 0 1 01 1 0 0 1
C1 C0
11 0 ϕ ϕ ϕ 11 0 ϕ ϕ ϕ

10 0 0 1 1 10 0 1 1 0

(b) Read the K-maps to obtain minimal SoP expressions for the two output variables C3 C2 and
minimal PoS expressions for the two output variables C1 C0. [4]
C3 = E3, C2 = E3 E2 + E2 E1 E0,
C1 = (E3 + E1’ + E0’)(E1 + E0)(E3’ + E1) and C0 = (E3 + E0’)(E3’ + E0).
(c) Find the minimum number of chips required for generating the four output bits, realising the SoP
expressions with 2-level NAND-NAND circuits, and the PoS expressions with 2-level NOR-NOR
circuits, given that both NAND and NOR gate chips are available in quad 2-input, triple 3-input and
dual 4-input configurations. [2]
Gate requirements:
Output 2-input 3-input 4-input NOT Chips
C3 - - - - 1 Triple 3-input NAND chip
C2 2 1 -
C1 2 2 - 3 1 triple 3-input and 2 quad 2-input NOR chips
C0 3 - -
Question 4 (10 marks):
The Karnaugh maps for two functions Q1 and Q2 of four variables A, B, C, D are given below. These
functions have to be realised using two 4-input multiplexers and NAND/NOR/XOR gates.

Q1 Q2
CD 0 0 0 1 1 1 1 0 CD 0 0 0 1 1 1 1 0
AB AB
00 1 0   00   0 1

01  1 0 1 01 1 0  0

11 0 0 1  11  0 1 

10   1 0 10 0 1  1

(a) Tabulate the Data Inputs required for the two multiplexers for three different choices of the
Select inputs of the multiplexers in the format given below. [3x2]

Select AB CD AC
Output Q1 Q2 Q1 Q2 Q1 Q2
Input

X0 D’ D’ A’ / B’ A’ / B B + D’ D’

- X1 C’ + D’ C’ D’ A’ B B’ D’ B’ D’

X2 D C+D A’ / B B’ 0 B’ D

X3 C C A A/B D 1

(b) Hence find the minimum number of gates required for a realisation using only one kind (NAND
or NOR) of gate for each of the above choices of the Select inputs. [3]

Select AB CD AC
NAND D’, (CD)’, ((C’D’)’)’, (C’D’)’  6 B’, ((A’B)’)’  4 D’, (B’D)’, ((B’D’)’)’, ((B’D)’)’  6
NOR D’, ((C’+D’)’)’, (C+D)’, ((C+D)’)’  6 B’, (A+B’)’  2 D’, ((B+D’)’)’, (B+D)’, (B+D’)’  4
Minimum 6 gates 2 gates 4 gates
So the choice Select = C D gives the minimum number of gates: only 2 NOR gates.
Question 5 (8 marks):
(a) Write the Verilog code for a full adder. It has 3 inputs, a, b, cin (carry in) and 2 outputs (sout
and cout). You may use any kind of coding style. [3]

module full_adder(a,b,cin,sout,cout);
input a,b,cin;
output reg sout,cout;
always@(*) begin
{cout,sout}=a+b+cin;
end
endmodule

(b) Write a Verilog code for a D latch. It has 2 inputs, “din” and “en” and one output “q”. When the
en input is high the value of din should pass on q and when en is zero, the old “latched” value of
din should remain at q. [3]
module dlatch (
din ,
en ,
q );
input din, en ;
output q;
reg q;

always @ ( en or din)
if (en) begin
q <= din;
end
endmodule

(c) In the below code snippet, “a” carries a value of 4(0100) and “b” carries a value of 7 (0111) in
beginning. Write a code in the space provided so that you can swap the values of a and b without
using a 3rd variable or register. So, the displayed values should be “7” for a and “4” for b. [2]
`timescale 1ns / 1ps
module test();
reg [3:0] a;
reg [3:0] b ;
initial
begin
a = 4'b0100;
b = 4'b0111;
//Write your code here

a<=b;
b<=a;
#5;

$display ("Value of a is %d",a);

$display ("Value of b is %d",b);
end
endmodule
Question 6 (6 marks):
(a) Draw a timing waveform for a, b, c from the below code snippet. [3]
module test;
reg a,b,c;
initial
begin
a = 0;
# 5;
a =1;
# 10
a =0;
end
always @(a)
begin
b <= #6a;
end
always @(a)
begin
#6 c <= a;
end
endmodule

(b) Draw a timing waveform for the reg ”a” from the below Verilog code. [1]
module test;
reg a;
initial
begin
a = 0;
end
always
#5 a =! a;
Endmodule

(c) What are the displayed values of a, b,c,d if you compile and run the below Verilog code? [2]
module test ();
reg a, b, c, d;
initial
begin
#5;
a = 1;
$display("Value of a is ",a);
b <= #5 a;
$display("Value of b is ",b);
c <= b;
#10;
$display("Value of c is ",c);
d =b;
 $display("Value of d is ",d);
end
endmodule
a =1
b = x (undefined)
c = x (undefined)
d=1

Question 7 (6 marks):
(a) What is the difference between structural and behavioral coding style in Verilog? Give a small
example. [2]
In structural data flow modelling, digital design functions are defined using components
such as an inverter, a MUX, an adder, a decoder, basic digital logic gates etc.
input A, B;
output sum, carry;
xor (.in1(A), .in2(B), .out(sum));
and (.in1(A), .in2(B), .out(carry));
Behavioral code uses direct assigns, procedural blocks like always etc
input A, B;
output sum, carry;
wire sum, carry;
assign sum = A ^ B;
assign carry = A & B;
(b) Is it compulsory for an always block to have a sensitivity list? Explain its significance. What can
happen if some of the signals being read inside the always block are omitted from the sensitivity
list? [2]
No, it is not compulsory for an always block to have a sensitivity list. If there are n signals
in the sensitivity list of always block, any change on any of the n signals causes the
statements inside the always block to execute. If some signals are omitted which are being
read, it might lead to synthesis – simulation mismatch
(c) State one advantage of Verilog over C which makes it popular as a hardware description
language. [1]
C language does not support concurrent execution of statements which is an important
aspect of modelling any Hardware system
(d) Consider the following Verilog code
module test();
wire temp;
always
begin
#5;
temp = 1 ;
$display ("Value of temp is", temp);
end
endmodule

What is the value printed for temp? [1]

a) 1
b) 0
c) May depend on the simulator chosen
d) Code will not compile and would result in a syntax error