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EED206 QUIZ 3A Solution

Given 4 D flip-flops with positive-logic Clock and positive-logic asynchronous Set (SD) and Clear
(RD) inputs, design an UP/DOWN Ripple Counter to generate the state sequence given below
(Hint: Use the fourth flip-flop to control the UP/DOWN mode):
Q2Q1Q0: 010011100101100011010011……

As the flip-flops have Positive-logic Clock, the Clock connections for UP and DOWN counting
would be as follows.
UP: CK1 = Q0’ and CK2 = Q1’ and DOWN: CK1 = Q0 and CK2 = Q1.
Hence we can make CK1 = Q0  Q3 and CK2 = Q1  Q3 where Q3 = 1 for UP and 0 for DOWN.
The UP sequence ends with 101, and we have to make Q3  0 to change to DOWN sequence.
The DOWN sequence ends with 010 and we have to make Q3  1 to change to UP sequence.
We can use the SD and RD inputs of the fourth flip-flop to implement this logic:
RD3 = Q2 Q1’ Q0 and SD3 = Q2’ Q1 Q0’.