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ISSN(Online): 2320-9801

ISSN (Print) : 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering


An ISO 3297: 2007 Certified Organization Vol.3, Special Issue 1, February 2015

National Conference on Computing and Communication (NC3 2K15)


Organized by
Dept. of CSE, CARE Group of Institutions, Tiruchirapalli-620009, India on 27th February 2015

High Speed RNS-To-Binary Converter Design


Using Parallel Prefix Adders
Augusta Angel. M1, Vijay M.M2
Second Year M.E (Applied Electronics) Dept. of ECE, VV College of Engineering, Tisayanvillai, TN, India1.
Assistant Professor, Dept. of ECE, VV College of Engineering, Tisayanvillai, TN, India2.

ABSTRACT: In this paper, the implementation of residue number system reverse converters based on hybrid parallel-
prefix adders is analyzed. The parallel prefix adder provides high speed and reduced delay arithmetic operations but it
is not widely used since it suffers from high power consumption. Hence, a hybrid parallel prefix adder component is
presented to perform fast modulo addition in Residue Number System reverse conversion. The proposed components
are not only results in fast arithmetic operation and it also highly reduced the hardware complexity since it requires
fewer amount of logic elements. In this work, the proposed components are implemented in different moduli sets
reverse converter designs and the performances are compared for different values of n.

KEYWORDS: Digital arithmetic, parallel-prefix adder, residue number system (RNS), reverse converter.

I. INTRODUCTION

In the last decades the rapid growth of personal wireless communication and handheld portable multimedia and
communication devices leads to rigorous demand on performance, power, cost and time-to-market. The battery-
powered devices require cheap, high performance and power efficient embedded processors. Hence we are in need of
system that performs computations fast and make use of the power and energy efficiently. The Residue Number System
(RNS) plays a very important role in the world of portable and battery based devices, because of its low power features
and delay. It has been an important research field in computer arithmetic for many decades because of its attractive
features such as parallelism, fault tolerance, modularity and carry free operations. Recently the researches are focussed
in the introduction of new efficient algorithms and simple hardware implementations. The major issues in designing a
efficient RNS are
1) Moduli set selection
2) Forward conversion
3) Residue arithmetic unit
4) Reverse conversion
The crucial step for any successful RNS application is the residue to binary conversion (R/B). In recent years, the
conversion process has been studied extensively to improve the performance of the converters. New algorithms and
novel arithmetic formulations has been investigated to achieve simple conversion formulas and new moduli sets, which
provide more simple formulations are introduced. Then, the obtained final simplified conversion equations are
computed using adder architectures such as carry save adders (CSAs), ripple-carry architectures, instead of carry-
propagate adders (CPAs), fast and expensive adders namely carry-look ahead or parallel prefix adders architectures
(Zarandi et al 2014). The residue to binary conversion is a tedious process; the conversion algorithms are based on the
Chinese remainder theorem (CRT) or mixed radix conversion. The use of CRT requires large modulo adders and the
MRC usage requires a number of look up tables. The advantage of both classical CRT and MRC are inherited in the
new CRT theorems proposed by Wang.

Distributed arithmetic principles are used to perform the inner product computation in [5].The input data
which are in the residue domain which are encoded using the Thermometer code format and the outputs are encoded
using the One hot code format. Compared to the conventional method which use Binary code format, the proposed

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ISSN(Online): 2320-9801
ISSN (Print) : 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering


An ISO 3297: 2007 Certified Organization Vol.3, Special Issue 1, February 2015

National Conference on Computing and Communication (NC3 2K15)


Organized by
Dept. of CSE, CARE Group of Institutions, Tiruchirapalli-620009, India on 27th February 2015
system which achieves higher operating speed.The RNS are widely used in computer arithmetic, cryptography, signal
processing applications such as fast Fourier transforms, digital filtering and image processing (Wang et al 2002). In this
brief, two power-efficient and low-area hybrid parallel-prefix adders are presented to tackle the limitations in
performance which leads to significant reduction of the delay and considerable improvements in hardware requirements
in comparison with the original converters without using parallel-prefix adders.

II. BACKGROUND

The reverse converter is the main part of the RNS. In contrast to other parts, reverse converter consists of a complex
structure. While designing reverse converter more attention should be taken because the convention delay should not
prevent the speed gain of the RNS arithmetic unit. The moduli set selection and conversion algorithm plays significant
effects on the overall reverse converter performance. Hence, moduli sets with distinct dynamic ranges have been
introduced [8]–[14]. The hardware components selection also a key to the RNS performance in addition to the distinct
moduli set selection. In addition to the moduli set, hardware components selection is key to the RNS performance. The
simplified conversion equations are computed using basic adder architectures such as Carry Propagate Adder (CPA),
Carry Select Adder (CSA). In order to increase the speed of operations instead of carry propagate adders, parallel prefix
adders are employed. Since it consumes more power than other adders they are not used in complex reverse converters
structure. However, parallel-prefix adders with its high-speed feature have been used in the RNS modular arithmetic
channels. The high speed is achieved due to parallel carry computation structures, which is based on different
algorithms. Each of these structures has distinct characteristics. Therefore, hardware components selection should be
undertaken carefully.

III. PARALLEL PREFIX ADDER COMPONENTS

The algorithms of reverse conversion are principally based on the Chinese remainder theorem (CRT), mixed-radix
conversion (MRC), and new Chinese remainder theorems (New CRTs). In addition to these, novel conversion
algorithms have been proposed, which are not as general as CRT, MRC, or New CRTs. To design a reverse converter,
the values of moduli of the moduli set must first be substituted in conversion algorithm formulas. Then, the resulting
equations should be simplified by using arithmetic properties. Finally, simplified equations would be realized using
hardware components such as full adders, half adders, logic gates, or LUT. The simplified equations are computed
using Ripple Carry Adders (RCA) but this leads increase in delay with the number of bits.

On the other hand, parallel prefix adders are high speed adders which bind the delay. However, in reverse converters
several parallel-prefix adders are required. This leads to high power consumption which degrades its speed gain. In this
section, two adder components are introduced to make use of parallel prefix adders high speed gain in RNS reverse
converter. To achieve final binary representation in reverse converter structures one regular binary addition is required.
The bit length of the operands is large which has significant effects in the total delay of the RNS reverse converter. A
thorough assessment of this final regular addition in recent converter designs shows that one of the operands has some
constant bits with value 1 as highlighted by the lemma, described in [1].

Based on the Lemma, to perform the first part of the addition a regular binary adder with the Brent-kung parallel prefix
adder as prefix structure can be used, for which the corresponding bits of the input operands are fully variable, and to
do the second part of addition since the operands are constant the RCA with simplified logic is used in which full adder
becomes XNOR/OR gates. The hybrid regular parallel-prefix XNOR/OR (HRPX) adder component is used to perform
the (4n + 1)-bit addition instead of subtraction. The HRPX is shown in Fig. 3. The carry output of the XNOR/OR chain
is not needed and it can be ignored.

In all reverse converter design, the modulo 2 n − 1 addition is a necessary operation for most moduli sets [8]–[12]. The
Carry Propagate Adder (CPAs) with end around carry (EAC) [19] is by default a moduli 2 n − 1 adder. But it suffers
from double representation of zero whereas; in reverse converters a single representation of zero is needed. A detector
circuit is needed to correct this error which introduces additional delay. Binary to Excess-1 Converter (BEC) are

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ISSN(Online): 2320-9801
ISSN (Print) : 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering


An ISO 3297: 2007 Certified Organization Vol.3, Special Issue 1, February 2015

National Conference on Computing and Communication (NC3 2K15)


Organized by
Dept. of CSE, CARE Group of Institutions, Tiruchirapalli-620009, India on 27th February 2015
employed to overcome this double zero representation problem. The main advantage of this BEC logic comes from the
lesser number of logic gates than the n-bit Full Adder (FA) structure. The binary-to-excess-one converter (BEC) [20]
can be modified to fix the double-representation of zero issue.

The main reason for the high power consumption of these parallel prefix adders is the recursive effect of generating and
propagating signals at each prefix level. An approach is proposed in [21], which uses an additional prefix level to add
the output carry. However, this method suffers from high fan-out, delay and it is applicable for small width operands.
However, we can overcome this problem by eliminating the additional prefix level by using a modified excess-one unit.

Fig. 1. Modified Excess-1 Unit. Fig. 2. Hybrid Modular Parallel Prefix Excess-1 Unit.

Fig. 3. HRPX structure.

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ISSN(Online): 2320-9801
ISSN (Print) : 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering


An ISO 3297: 2007 Certified Organization Vol.3, Special Issue 1, February 2015

National Conference on Computing and Communication (NC3 2K15)


Organized by
Dept. of CSE, CARE Group of Institutions, Tiruchirapalli-620009, India on 27th February 2015
In contrast to the BEC, based on control signals from the prefix structure the modified unit is conditionally
incremented. The modified excess one unit is shown in Fig. 1, and the hybrid modular parallel prefix excess-one
(HMPE) adder is shown in Fig. 2. The HMPE consists of a regular prefix adder (Brent Kung Prefix Network) and the
modified excess-one unit. First, two operands are added using the prefix adder structure, the square block represents
pre-processing stage which generates the propagate and generate signals. These signals are given to the prefix network
to compute carry. The diagonal block represents post processing stage which produces sum output and afterwards the
result is conditionally incremented based on control signals generated by the prefix structure to assure the single zero
representation.
Summarizing, the HMPE is highly flexible, it can be used with other parallel prefix networks.. The HRPX
avoids the usage of a large size parallel-prefix adder structure which results in high power-consumption, and the long
carry-propagation chain of a RCA is avoided

IV. REVERSE CONVERTER DESIGN METHODOLOGY

In this section, the methodology of reverse converter design is described. Several reverse converters for different
moduli sets have been introduced, it includes more complex reverse converter design, which has several Carry Select
Adders (CSAs) and Carry Propagate Adders with End Around Carry (EACs) followed by a final subtractor with two
operands of different size [10]–[12]. The implementation of this subtractor using regular binary-adder results in one
operand with some constant bits and the other operand with fully variable bits. the reverse converters that have been
designed for moduli sets with the popular moduli other than 2 n and 2n ± 1 are described [14]. First of all, based on the
specified applications the required performance metrics has to be determined. To achieve the least power consumption
and hardware cost without considering speed, no prefix adder is needed. On the other hand, if high speed is the
designer goal, the CPAs with EAC and the regular CPAs should be replaced by traditional parallel prefix modulo 2n − 1
adders and regular parallel-prefix adders, respectively. However, for the VLSI designers, a suitable tradeoff between
speed, power, and area is often more important. In this case, first, CPAs with the EAC can be replaced by the HMPEs.
Then, if the converter contains a regular CPA where one of its operands has a string of constant bits with the value of
one, it can be replaced with the HRPX.
V. IMPLEMENTATIONS

In order to support a thorough assessment, especially for power-consumption, the proposed method was applied to two
different reverse converters. The architectures of these converters are proposed in [10]. The implemented converters
can be classified as follows: 1) cost effective designs using only the RCAs for the CPAs with the EAC and regular
CPAs; 2) speed efficient designs, which substitute all the CPAs with EAC and the regular CPA by the parallel-prefix
modulo 2n − 1 adders and 3) designs that use both HMPE and HRPX, tradeoffs between circuit parameters. Three well-
known approaches for prefix network [18], i.e., Brent–Kung (BK), have been considered for implementing the required
prefix network in the proposed designs.

The circuits for all these configurations were designed and specified in the Verilog HDL. Structural or behavioral
descriptions can be considered. Verilog HDL describes just the circuit operation, and therefore the circuit’s quality
depends on synthesis tool [23]. However, herein our purpose is to compare the proposed architectures on a fair basis,
and independently of the particular abilities of the synthesis tools. In addition, four different values of n (4 and 2) were
considered to obtain experimental results for the different configurations of the implemented converters. The obtained
results are presented in Tables I and II. The results include:, delay (nanosecond), number of LUTs and number of IOs
are used to compare the circuit’s area/latency and power/latency balancing. As it was expected, the RCA-based
converter [10] suggests the most competitive area and the power consumption metrics, but the highest delay. The
suggested designs have considerably improved the delay.

Our main goal is to decrease the cost of achieving high speed converters using parallel-prefix adders and also to
provide applicable competitive tradeoffs between power consumption and delay. In the other hand, the proposed
designs consume more power to achieve higher speed than the RCA-based ones. The comparison result of moduli set

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ISSN(Online): 2320-9801
ISSN (Print) : 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering


An ISO 3297: 2007 Certified Organization Vol.3, Special Issue 1, February 2015

National Conference on Computing and Communication (NC3 2K15)


Organized by
Dept. of CSE, CARE Group of Institutions, Tiruchirapalli-620009, India on 27th February 2015
{2n − 1, 2n, 2n + 1, 22n+1 – 1} for n=2 and moduli set {2n − 1, 22n, 2n + 1, 22n + 1} for n=2 & 4 is shown in following
tables.

TABLE I

moduli set moduli set


moduli set
{2n − 1, 22n, 2n + 1, 22n + {2n − 1, 22n, 2n + 1, 22n + 1}
parameters {2 − 1, 2 , 2n + 1, 22n+1 – 1} for
n n
1} for for
considered n=2
n=2 n=4

Number of Slice
91 41 96
LUTs

Number of IOs 34 23 66

Maximum
combinational 25.635ns 15.581ns 18.112ns
path delay

TABLE II

moduli set {2n − 1, 22n, 2n + 1, 22n


+ 1} for n=2
Hardware moduli set {2n − 1, 2n, 2n + 1, moduli set {2n − 1, 22n, 2n +
requirements 22n+1 – 1} for n=2 1, 22n + 1} for n=4
Proposed RCA

Adders
3 2 4 3
/Subtractors

Multiplexers 3 2 4 3

Xors 72 40 64 113

VI. CONCLUSION AND FUTURE WORK

This brief presents a novel approach to perform addition in reverse converter design for residue number system. The
proposed novel specific hybrid parallel prefix adders components are employed in reverse converter architectures to
enhance the performance. These adder components are designed especially for residue to binary number conversion.

Copyright @ IJIRCCE www.ijircce.com 142


ISSN(Online): 2320-9801
ISSN (Print) : 2320-9798

International Journal of Innovative Research in Computer and Communication Engineering


An ISO 3297: 2007 Certified Organization Vol.3, Special Issue 1, February 2015

National Conference on Computing and Communication (NC3 2K15)


Organized by
Dept. of CSE, CARE Group of Institutions, Tiruchirapalli-620009, India on 27th February 2015
Based on the given methodology the proposed components can be used in any reverse converter design with different
moduli sets. The proposed HMPE structure is highly flexible; it can be replaced with other parallel prefix components
(such as kogge stone and ladner fisher) that enhance the performance and also reduce the power and delay variations. In
this work, the adders are employed in two different moduli sets and the outputs are verified for n=2 & 4.

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BIOGRAPHY

M Augusta Angel is a Second Year Masters of Engineering (Applied Electronics) student, Dept. of ECE,
VV College of Engineering, Tisayanvillai, Tamil Nadu, India. Her research interests are VLSI Physical design, Digital
Image Processing, Computer Networks (wireless Networks), etc.

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