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Definition:
Latch is an electronic logic circuit with two stable states i.e. it is a bi-stable multi vibrator. Latch has a feedback path to retain
the information. Hence a latch can be a memory device. Latch can store one bit of information as long as the device is powered
on. When enable is asserted, latch immediately changes the stored information when the input is changed i.e. they are level
triggered devices. It continuously samples the inputs when the enable signal is on.
a. Latch circuits can work in two states depending on the triggering signal being high or low: Active – High or Active – Low.
b. In case of Active – High latch circuits, normally both the inputs are low. The circuit is triggered by a momentary high on
either of the inputs.
c. In case of Active – Low latch circuits, normally both the inputs are high. The circuit is triggered by a momentary low on
either of the inputs.
SR LATCH
We can use static gates as basic building blocks in order to construct a simple latch and it can be constructed with two NOR
gates by introducing feedback to a NOR gate circuit.
A simple NOR gate logic with feedback is shown below.
Here, both the inputs S and R are 0 (S = R = 0). The output of first NOR gate is P = 1. This is fed to the second NOR gate along
with R = 0. Hence the output of the second gate is Q = 0. The circuit is said to be in stable state with P = 1 and Q = 0. If we make
S = 1, then P = 0. This will make Q =1 as shown below.
This is also a stable state. If S is made 0, there is no change as Q = 1 is fed back to first NOR and P still remains 0. It is shown in
the below figure.
State Diagram
In addition to tables and equations, a state machine (or a system) can be represented by a state diagram. In this state diagram,
a state is represented by a circle, and the transition between states is represented by lines or arcs that connect the circles. State
diagram for a simple SR latch is shown below.
The state diagram provides all the information that a state table can have. This is obtained from the state table directly.
GATED S-R LATCH
Generally, latches are transparent i.e. the output changes immediately when there is a change in the input. But for many
applications, it is desirable to have an isolated period where the output doesn’t change even when there is a change in the
input. During this period, the outputs are said to be truly ‘latched’. This can be achieved with the use of an extra input (enable
or clock or gate). If the enable (or clock or gate) signal is not asserted, the inputs are ignored and the outputs are latched to the
previous values. In order to use this extra signal, additional logic should be added. These circuits are called Gated or Clocked
Latches.
Gated SR latch can be made in two ways: by adding second level of AND gates to SR latch or by adding second level of NAND
gates to ̅S ̅R latch (Inverted SR latch).
The circuit diagram of Gated SR latch constructed from NOR gates is shown below.
The circuit diagram of Gated SR latch constructed from NAND gates is shown below.
As the NAND gate inverts the inputs, ̅S ̅R latch becomes a gated SR latch.
When enable (or clock) is high, the latch is said to be enabled i.e. the output responds to the inputs.
When enable (or clock) is low, the latch is disabled and remains in that state until enable is asserted.
The symbol for gated SR latch is shown below
These simple D latches are not frequently used but Gated D latches are very common. The truth table of a simple D Latch is
shown below.
GATED D LATCH
A gated D latch can be easily constructed by modifying a gated SR latch. The only modification to the gated SR latch is that the R
input has to be changed to inverted S. A gated latch formed from NOR SR latch is shown below.
When the clock or enable is high (logic 1), the output latches whatever is on the D input. When the enable or clock is low
(logic0), the D input for the last enable high will be the output.
This latch circuit will never experience a “Race” condition because the single D input is inverted to provide to both the inputs.
Hence, there is no chance for same input condition. So the D latch circuit can be safely used in any circuit.
The usage of inverter can be avoided as the NAND gate can be used to obtain the inverted value. Some modification is required
in the above circuit and the resultant circuit is shown below.
The truth table (or state table) of a gated D latch is shown below.
Applications
They are basic 1 – bit memory devices.
D latches are typically used as I/O ports in asynchronous systems.
Data latches are sometimes used in synchronous two phase systems to reduce the transistor count.
Advantages of latches
Latch is faster because it has no need to wait for a clock signal so they are most used in high speed designs.
They require less power.
Latch based designs have small die-size.
The major advantage of the latches is “Time-Borrowing”. In which if an operation is not completed within time, the required
time for executing the operation is borrowed from the other operational time.
Disadvantages of latches
Latch less predictable because there is more chance to affect to race conditions.
Level sensitive devices and hence more chance of meta-stability.
Analyzing of Latch circuits is difficult because of its level sensitive property.