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ADC128S052, ADC128S052-Q1
SNAS333E – AUGUST 2005 – REVISED DECEMBER 2015
ADC128S052, ADC128S052-Q1 8-Channel, 200 kSPS to 500 kSPS, 12-Bit A/D Converter
1 Features 3 Description
•
1 Qualified for Automotive Applications The ADC128S052x device is a low-power, eight-
channel CMOS 12-bit analog-to-digital converter
• AEC-Q100 Qualified With the Following Results: specified for conversion throughput rates of
– Device Temperature Grade 1: –40°C to 200 kSPS to 500 kSPS. The converter is based on a
+125°C Ambient Operating Temperature successive-approximation register architecture with
Range an internal track-and-hold circuit. It can be configured
• Eight Input Channels to accept up to eight input signals at inputs IN0
through IN7.
• Variable Power Management
• Independent Analog and Digital Supplies The output serial data is straight binary and is
compatible with several standards, such as SPI,
• Compatible With SPI™, QSPI™, MICROWIRE, QSPI, MICROWIRE, and many common DSP serial
and DSP interfaces.
• Packaged in 16-Pin TSSOP
The ADC128S052x may be operated with
• Conversion Rate 200 kSPS to 500 kSPS independent analog and digital supplies. The analog
• DNL (VA = VD = 5 V) + 1.3 or −0.9 LSB supply (VA) can range from 2.7 V to 5.25 V, and the
(Maximum) digital supply (VD) can range from 2.7 V to VA.
• INL (VA = VD = 5 V) ±1 LSB (Maximum) Normal power consumption using a 3-V or
5-V supply is 1.6 mW and 8.7 mW, respectively. The
• Power Consumption power-down feature reduces the power consumption
– 3-V Supply 1.6 mW (Typical) to 0.06 µW using a 3-V supply and 0.25 µW using a
– 5-V Supply 8.7 mW (Typical) 5-V supply.
The ADC128S052x is packaged in a 16-pin TSSOP
2 Applications package. The ADC128S052 is ensured over the
• Automotive Navigation extended industrial temperature range of −40°C to
+105°C while the ADC128S052-Q1 is ensured to an
• Portable Systems AECQ100 Grade-1 automotive temperature range of
• Medical Instruments −40°C to +125°C.
• Mobile Communications
Device Information(1)
• Instrumentation and Control Systems
PART NUMBER PACKAGE BODY SIZE (NOM)
ADC128S052,
TSSOP (16) 4.40 mm × 5.00 mm
ADC128S052-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VA is used as the Reference VD can be set independently
“Analog” Supply Rail for the ADC of VA “Digital” Supply Rail
VA VD
VIN7 IN7
IN6
IN5
CONTROLLER
IN2
IN1
VIN0 IN0
AGND DGND
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADC128S052, ADC128S052-Q1
SNAS333E – AUGUST 2005 – REVISED DECEMBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.5 Programming........................................................... 17
2 Applications ........................................................... 1 7.6 Register Maps ......................................................... 18
3 Description ............................................................. 1 8 Application and Implementation ........................ 19
4 Revision History..................................................... 2 8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 20
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 22
9.1 Power Supply Sequence......................................... 22
6.1 Absolute Maximum Ratings ..................................... 4
9.2 Power Supply Noise Considerations....................... 22
6.2 ESD Ratings – Commercial ...................................... 4
6.3 ESD Ratings – Automotive ....................................... 4 10 Layout................................................................... 23
6.4 Recommended Operating Conditions ...................... 5 10.1 Layout Guidelines ................................................. 23
6.5 Thermal Information .................................................. 5 10.2 Layout Example .................................................... 23
6.6 Electrical Characteristics .......................................... 5 11 Device and Documentation Support ................. 24
6.7 Timing Specifications ............................................... 8 11.1 Device Support .................................................... 24
6.8 Typical Characteristics .............................................. 9 11.2 Related Links ........................................................ 25
7 Detailed Description ............................................ 15 11.3 Community Resources.......................................... 26
7.1 Overview ................................................................ 15 11.4 Trademarks ........................................................... 26
7.2 Functional Block Diagram ....................................... 15 11.5 Electrostatic Discharge Caution ............................ 26
7.3 Feature Description................................................. 15 11.6 Glossary ................................................................ 26
7.4 Device Functional Modes........................................ 16 12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Device Information table, ESD Ratings table, Thermal Information table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
PW Package
16-Pin TSSOP
Top View
CS 1 16 SCLK
VA 2 15 DOUT
AGND 3 14 DIN
IN0 4 13 VD
ADC128S052
IN1 5 12 DGND
IN2 6 11 IN7
IN3 7 10 IN6
IN4 8 9 IN5
Pin Functions
PIN
TYPE DESCRIPTION
NO. NAME
Chip select. On the falling edge of CS, a conversion process begins. Conversions continue
1 CS Digital I/O
as long as CS is held low.
Positive analog supply pin. This voltage is also used as the reference voltage. This pin must
Power
2 VA be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with 1-µF and 0.1-µF
Supply
monolithic ceramic capacitors located within 1 cm of the power pin.
Power
3 AGND The ground return for the analog supply and signals.
Supply
4
5
6
7
IN0 to IN7 Analog I/O Analog inputs. These signals can range from 0 V to VREF.
8
9
10
11
Power
12 DGND The ground return for the digital supply and signals.
Supply
Power Positive digital supply pin. This pin must be connected to a 2.7-V to VA supply, and bypassed
13 VD
Supply to GND with a 0.1-µF monolithic ceramic capacitor located within 1 cm of the power pin.
Digital data input. The control register of the ADC128S052 is loaded through this pin on
14 DIN Digital I/O
rising edges of the SCLK pin.
Digital data output. The output samples are clocked out of this pin on the falling edges of the
15 DOUT Digital I/O
SCLK pin.
Digital clock input. The ensured performance range of frequencies for this input is
16 SCLK Digital I/O
3.2 MHz to 8 MHz. This clock directly controls the conversion and readout processes.
6 Specifications
6.1 Absolute Maximum Ratings
(1) (2) (3)
See
MIN MAX UNIT
Analog Supply Voltage VA –0.3 6.5 V
Digital Supply Voltage VD –0.3 VA + 0.3, max 6.5 V
Voltage on Any Pin to GND –0.3 VA + 0.3 V
Input Current at Any Pin (4) ±10 mA
Package Input Current (4) ±20 mA
(5)
Power Dissipation at TA = 25°C See
Junction Temperature +150 °C
Storage Temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications.
(3) For soldering specifications: see product folder at www.ti.com and SNOA549.
(4) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin must be
limited to 10 mA. The 20-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 10 mA to two.
(5) The absolute maximum junction temperature (TJMAX) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJMAX, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJMAX − TA)/RθJA. In the 16-pin TSSOP, RθJA is 110°C/W, so PDMAX = 1,200 mW at 25°C and 625 mW at the maximum
operating ambient temperature of 105°C. Note that the power consumption of this device under normal operation is a maximum of
12 mW. The values for maximum power dissipation listed above is reached only when the ADC128S052 is operated in a severe fault
condition (for example, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Such conditions must always be avoided.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor.
(3) Machine model is a 220-pF discharged through ZERO Ω.
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) Data sheet minimum and maximum specification limits are ensured by design, test, or statistical analysis.
(2) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(1) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
Power
Down
Power Up Power Up
Track Hold Track Hold
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8
SCLK
Control register
DOUT FOUR ZEROS DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 FOUR ZEROS DB11 DB10 DB9
CS
tACQ tCONVERT
tCH
SCLK 1 2 3 4 5 6 7 8 16
tDH
tDS
DIN DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC
SCLK
tCSS
CS
tCSH
CS
VA = 5 V
VA = 5 V
Figure 16. INL vs SCLK Duty Cycle Figure 17. SNR vs SCLK Duty Cycle
Figure 18. THD vs SCLK Duty Cycle Figure 19. ENOB vs SCLK Duty Cycle
Figure 30. SNR vs Input Frequency Figure 31. THD vs Input Frequency
Figure 32. ENOB vs Input Frequency Figure 33. Power Consumption vs SCLK
7 Detailed Description
7.1 Overview
The ADC128S052x is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter. For the remainder of this document, ADC128S052x is abbreviated to
ADC128S052.
IN0
. 12-BIT VA
SUCCESSIVE
. MUX T/H
APPROXIMATION
. ADC AGND
IN7 AGND
VD
SCLK
ADC128S052 CS
CONTROL
LOGIC DIN
DOUT
DGND
IN0
CHARGE
REDISTRIBUTION
DAC
MUX
SAMPLING
CAPACITOR
SW1 +
IN7 CONTROL
SW2 - LOGIC
AGND
VA /2
IN0
CHARGE
REDISTRIBUTION
DAC
MUX
SAMPLING
CAPACITOR
IN7
SW1 + CONTROL
LOGIC
SW2
-
AGND
VA /2
111...111
111...110
ADC CODE
111...000
|
|
1LSB = VA/4096
011...111
000...010
000...001
|
000...000
0V 0.5LSB +VA - 1.5LSB
ANALOG INPUT
7.5 Programming
7.5.1 Serial Interface
Figure 1 shows a operational timing diagram, and Figure 2 shows a serial interface timing diagram for the
ADC128S052. CS (chip select) initiates conversions and frames the serial data transfers. SCLK (serial clock)
controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a
conversion result is sent as a serial data stream, MSB first. Data to be written to the control register of the device
is placed on DIN, the serial data input pin. New data is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC's DOUT pin is in a high impedance state when CS is high
and is active when CS is low. Thus, CS acts as an output enable. Similarly, SCLK is internally gated off when CS
is brought high.
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished, and the data is clocked out. SCLK falling edges 1 through 4 clock
out leading zeros while falling edges 5 through 16 clock out the conversion result, MSB first. If there is more than
one conversion in a frame (continuous conversion mode), the ADC re-enters the track mode on the falling edge
of SCLK after the N × 16th rising edge of SCLK and re-enter the hold/convert mode on the N × 16 + 4th falling
edge of SCLK. N is an integer value.
The ADC128S052 enters track mode under three different conditions. In Figure 1, CS goes low with SCLK high,
and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with
SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as
the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously, and the ADC enters
track mode. While there is no timing restriction with respect to the rising edges of CS and SCLK, see Figure 3 for
setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.
While a conversion is in progress, the address of the next input for conversion is clocked into a control register
through the DIN pin on the first 8 rising edges of SCLK after the fall of CS. See Table 1, Table 2, Table 3.
There is no need to incorporate a power-up delay or dummy conversion as the ADC128S052 is able to acquire
the input signal to full resolution in the first conversion immediately following power up. The first conversion result
after power-up is that of IN0.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
D1 C2
R1 30 pF
VIN
C1
3 pF D2
High
Impedance + VA VD VDD
100 100
Source LMV612 IN7 SCLK GPIOa
100
33n CS GPIOb
100 MCU
IN3 ADC128S102 DOUT GPIOc
Schottky
100
Diode
DIN GPIOd
(optional)
Low 100
GND
Impedance IN0
Source
AGND DGND
33n
10 Layout
ANALOG
SUPPLY
RAIL CS SCLK
VA DOUT toMCU
AGND DIN
IN1 DGND
IN2 IN7
IN3 IN6
to analog
IN4 IN5
signal sources
GROUND PLANE
A f22 + + A f10 2
THD = 20 ‡ log 10
A f12
• where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS
power in the first 5 harmonic frequencies. (8)
THROUGHPUT TIME is the minimum time required between the start of two successive conversions. It is the
acquisition time plus the conversion and read out times. In the case of the ADC128S052, this is 16
SCLK periods.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
SPI, QSPI are trademarks of Motorola.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 17-Mar-2017
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 17-Mar-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Catalog: ADC128S052
• Automotive: ADC128S052-Q1
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1 4.55
4.9
NOTE 3
8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 -8
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
14X (0.65)
8 9
(5.8)
4220204/A 02/2017
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
14X (0.65)
8 9
(5.8)
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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