International Journal of Electronic Engineering Research

ISSN 0975 - 6450 Volume 2 Number 1 (2010) pp. 9–14

© Research India Publications
http://www.ripublication.com/ijeer.htm

New Design Technique of 6-Bit Flash A/D Converter

*R.S. Gamad and C.B. Kushwah

Dept. of Electronics and Instrumentation Engineering,

Shri G.S. Institute of Technology & Science, Indore, India
*Corresponding Author E-mail: rsgamad@gmail.com

Abstract

This paper reports the new design of 6-bit flash Analog to Digital Converter
(ADC) using 0.35µm technology. Comparison of design and its simulation
results of this method with existing methods is done and improvement in
results is obtained as compared to existing method considering power, speed
and size. This design approach is based on the concept of systematic transition
of binary codes of number system.

Keywords: Analog to digital converter low, low power, high speed, synopsys,
small size.

Introduction
Analog to Digital Converters (ADCs) are currently adopted in many application fields
to improvement digital systems, which achieve superior performances with respect to
analog solutions. Various examples of ADC applications can be found in data
acquisition systems, measurement systems and digital communication systems. Such
a wide spread usage confers great importance to the design activities, which
nowadays largely contributes to the production cost in integrated circuit devices (ICs).
In this regard, it should be observed that the ADC design have low power
consumption, higher speed, compact in size and low cost. Hence, in present design we
have considered all the parameters and improving the associated performance may
significantly reduce the industrial cost of an ADC manufacturing process and
improved the resolution and design. Flash ADCs are best for applications requiring
very large bandwidth [1-8]. Generally flash ADCs are made by cascading high speed
comparators and each comparator represents 1LSB, and the output code can be
10 R.S. Gamad and C.B. Kushwah

resolute in only one clock cycle [9]. Figure 1 shows a general form of a flash ADC
[10].

Figure 1: Block diagram of a general flash ADC.

Design Implementation and their Simulation Results

A 4-bit, 2.5 V flash ADC design has been reported [1] new flash topology and this
new topology has only 2(N-2) + 2 comparators required. Figure 2 shows the earlier
design.

Figure 2: 4-bit flash ADC.

New Design Technique of 6-Bit Flash A/D Converter 11

Figure 3 presents the important sections of the proposed design of the flash ADC.
These are the basic steps that we have followed to implement present design.

Figure 3: Block diagram of flash ADC for proposed method.

A novel 6-bit, 2.5 V flash ADC has been implemented. In present design we have
used a new flash topology, this topology has required only 2(N-2) + 2 comparators. A
typical schematic view of the proposed flash ADC is presented in Figure 4.

Figure 4: The complex schematic of proposed 6-bit flash ADC.

In present design, analog input voltage has applied to the non-inverting inputs of
all the comparators and inverting inputs of the MSB comparators is set to 32VRef/64,
16 VRef /64 and 48VRef/64. Outputs of these three comparators are used to control the
analog multiplexers, which are connected to the appropriate fractions of the reference
voltage, VRef. The outputs of the comparators (Comp 4 to Comp18) are encoded into
appropriate values. Finally for testing of a design a ramp signal is applied at the input
and the output results of the proposed 6-bit flash ADC are obtained in bit form and
plotted in Figure 5 to view the converted results.
12 R.S. Gamad and C.B. Kushwah

Figure 5: Simulated transient output waveforms of the proposed 6-bit flash ADC on
application of ramp input.

Simulated transient response of proposed ADC is plotted against time. From the
design we have observed the response for different frequencies to check overall
performance of the design. It is observed that the average power consumption of this
design is about 0.5 mW at different frequencies and it is plotted in Figure 6 against
time.

Figure 6: Simulated transient output waveforms of power consumption of the

proposed 6-bit flash ADC on application of ramp input.

In addition to verified the proposed design we have also presented the simulation
results of the design and schematic view of comparator design.

Differential Comparator
Our aim was to design a high speed comparator, which shows improvement in the
power-delay product. After a literature survey, we found that differential comparator
is a better for a design of high speed ADC. A schematic diagram of differential
amplifier with two gain boosters is present in Figure 7. In this design we have used a
current mirror circuit as load in Figure 7. Design has last two inverters are worked as
gain boosters to improve the gain of the design.
New Design Technique of 6-Bit Flash A/D Converter 13

Figure 7: Schematic of modified differential amplifier as a comparator.

After completion of the design we have simulated it and simulated transient

response of the all differential comparators is plotted against time in is presented in
Figure 8.

Figure 8: Simulated transient output waveforms of the all 18 comparators on

application of ramp input.

Conclusion
This paper is presented the improved design of 6-bit flash ADC with less components
as compare to earlier therefore smaller size, and lower power consumption and high
speed. These characteristics make this new design with better performance for many
applications where power and size are major factors. Results indicate that a power and
area saving is obtained when the proposed flash ADC is used instead of full flash
ADC. The proposed 6-bit flash ADC has been designed in TSMC 0.35µ technology.
Whole design of ADC is implemented in Synopsys CosmosSE schematic editor and
results are verified with Synopsys HSPICE. We have also compared our simulated
results with the earlier reported work and we have got better improvement in our
results as reported in table 1.
14 R.S. Gamad and C.B. Kushwah

Table 1: Comparison of results by proposed 6-bit flash ADC design with earlier work.

Parameter Results by earlier work done[3] Results by proposed design

Technology - 0.35 µm
Resolution(bits) 4-bit 6-bit
Speed 400 MHz 1 MHz
Power supply 2.5 V 2.5 V
Power Consumption 1.68 mW 0.5 mW
No. of Comparator 6 18
No. of Devices NMOS - 84 Total MOSFETs - 762
PMOS - 90
Resistors - 16

Acknowledgment
This work has been carried out in SMDP VLSI laboratory of the Electronics and
Instrumentation Engineering department of Shri G. S. Institute of Technology and
Science, Indore, India. This SMDP VLSI project is funded by Ministry of Information
and Communication Technology, Government of India. Authors are thankful to the
Ministry for the facilities provided under this project.

References
[1] Stojcevski, H.P. Le, J. Singh and A. Zayegh, ‘Flash ADC architecture’,
Electronics Letters, Vol. 39 No. 6, March 2003.
[2] Jincheol Yoo, Kyusun Choi, and Jahan Ghaznavi, ‘Quantum Voltage
Comparator for 0.07 µm CMOS Flash A/D Converters’, IEEE, 2003.
[3] Daegyu Lee, Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi, ‘Fat tree encoder
design for ultra-high speed flash A/D converters’, in Proc. of MWSCAS-2002,
Aug. 2002.
[4] Razavi, ‘Principles of Data Conversion System Design’, IEEE Press, 1995.
[5] Nicholas Gray, ‘ABCs of ADCs, Analog-to-Digital Converter
Basics’, National Semiconductor Corporation, 2006.
[6] Jincheol Yoo Kyusun Choi Jahan Ghaznavi, ‘A 0.07µm CMOS Flash Analog
to Digital Converter for High Speed and Low Voltage Applications’,
GLSVLSI’0, Washington, DC, USA., April 2003.
[7] Amir Zjajo, Jose Pineda de Gyvez, ‘DFT for Full Accessibility of Multi-Step
Analog to Digital Converters’, IEEE, 2008.
[8] Anthony Estrada, ‘Improving High Speed Analog to Digital converter
Dynamic Range by Noise Injection’, 2007.
[9] P. E. Allen and D. R. Holberg, ‘CMOS Analog Circuit Design’, 2nd edition,
Oxford University Press, 2002.
[10] R. Jacob Baker,Harry W. Li and David E. Boyce, ‘CMOS Circuit Design,
Layout, and Simulation’, IEEE Press,1998.