SOFT CORE IMPLEMENTATION ON FPGA FOR

ARITHMETIC CALCULATOR

A PROJECT REPORT

Submitted by

ARNAB BHATTACHARJEE (13UEEI0001)

ARUN PRAKASH R (13UEEI0002)

In fulfilment for the award of the degree

Of

BACHELOR OF TECHNOLOGY
in

ELECTRONICS AND INSTRUMENTATION

APRIL 2017
 BONAFIDE CERTIFICATE

Certified that this project report titled “SOFT CORE IMPLEMENTATION ON

FPGA FOR ARITHMETIC CALCULATOR”.

submitted by “ARNAB BHATTACHARJEE (13UEEI0001), ARUNPRAKASH R

(13UEEI0002)”, in fulfillment for the requirements for the award of Bachelor of
Technology in Electronics & Instrumentation Engineering is an authentic work
carried out by them under guidance of my supervision and guidance.

To the best of my knowledge, the matter embodied in the project report has not
been submitted to any other University/Institute for the award of any Degree or
Diploma.

Signature of Supervisor Signature of Head of the Department

Dr. U. SARAVANAKUMAR Dr. G. VAIRAVEL
Associate Professor Professor
Department of ECE, Department of ECE,
Veltech Dr.RR & Dr.SR University, Veltech Dr.RR & Dr.SR University,
Avadi, Chennai-600062 Avadi, Chennai-600062.

Submitted for the fulfillment for the award of degree of Bachelor of

Technology in Electronics & Instrumentation Engineering from VELTECH Dr. RR
& Dr.SR UNIVERSITY, 400 feet Outer Ring Road, Avadi, Chennai-600062
 CERTIFICATE OF EVALUATION

COLLEGE NAME : VELTECH Dr.RR& Dr.SR UNIVERSITY

BRANCH : ELECTRONICS AND INSTRUMENTATION
ENGINEERING
YEAR / SEMESTER : IV / VIII

S. NAME OF THE TITLE OF NAME OF THE

No STUDENT PROJECT GUIDE

1 ARNAB
BHATTACHARJEE SOFT CORE Dr U.
(13UEEI0001) IMPLEMENTATION SARAVANAKUMAR
ARUN PRKASH R ON FPGA FOR
ASSO. PROFESSOR
2 ARITHMETIC
(13UEEI0002) CALCULATOR

The report of the project work submitted by the above students in partial fulfillment
for the award of Bachelor of Technology in ELECTRONICS &
INSTRUMENTATION ENGINEERING of VELTECH Dr.RR & Dr.SR
UNIVERSITY for the viva-voce examination held at VELTECH Dr.RR & Dr.SR
UNIVERSITY on ________________, has been evaluated and confirmed to be
reports of the work done by the above students.

INTERNAL EXAMINER EXTERNAL EXAMINER

 DECLARATION

I hereby declare that the project entitled “SOFT CORE IMPLEMENTATION

ON FPGA FOR ARITHMETIC CALCULATOR “submitted to the VELTECH
Dr.RR & Dr.SR UNIVERSITY, Chennai; is a record of an original work done by
under the guidance of Dr. U. Saravanakumar, associate professor in the same
university and this project work is submitted in the partial fulfilment of the
requirements for the award of Bachelor of Technology Degree in the department of
Electronics and Instrumentation Engineering. The results embodied in this thesis
have not been submitted to any other university or any institution for the award of
degree or diploma.

i
 ACKNOWLEDGEMENT

We express our deepest gratitude to our respected Col. Prof. Vel Dr. R.
Rangarajan B.E. (E.E.E), B.E. (MECH), M.S (AUTO), Founder and
President of VELTECH Dr.RR & Dr.SR UNIVERSITY, D.Sc. and Founder
Chancellor Dr. Sagunthala Rangarajan (M.B.B.S), Chair Person &
Managing Trustee Mrs. Rangarajan Mahalakshmi Kishore and Vice
President Mr. K.V.D. Kishore Kumar for encouraging students and providing
us with an environment to complete our project successfully.
We are very thankful to our beloved Vice Chancellor Prof. Beela
Satyanarayana, B.E. (MECH), M.E. (IE), M.Tech(CSE), Ph.D. (IIT, Delhi)
and Pro-Vice Chancellor Dr. U.Chandrasekhar Ph.D., for providing us an
environment to complete our project successfully.

We are obliged to our beloved Registrar Dr. E. Kannan, M.E., Ph.D., for
giving this valuable guidance to complete our project successfully.
We are thankful to our beloved Director-Academics Prof. Dr. Techn.
Koteswara Rao Anne, Director-Industry Relations Prof. Dr. P. Sarasu and
Director International-Academic Quality Prof. Dr. A. Abudhahir for
providing us wonderful environment to complete our project successfully.

It is a great pleasure for our to acknowledge the assistance and contribution of

our Head of the Department Dr. G.Vairavel, M.E. Ph.D., for their assistance
and useful suggestions, which helped us in completing the project work.
We would also thank our Project Coordinator Dr P. Suresh, M.E. Ph.D., for
his support during the entire course of this project work and also for providing
necessary facilities to carry out the work.

We would also thank our Project Guide Dr. U. Saravanakumar, M.E.

Ph.D., for his support during the entire course of this project work and also for
providing necessary facilities to carry out the work.

We would also thank all the staffs in our department for their guidance to
finish this project successfully. We also like to thank all our friends for their
willing assistance. Words never fill what we owe to our beloved parents for
everything they have done for us.

ii
 ABSTRACT

The idea is to work on advanced logical units with reprogrammable capabilities

depending on user. Implementing IP core (intellectual properties) provides the
advantage of inserting it into any targeting vendor technology or design
methodology. The IP block is a reusable unit of a whole system or part of the
processing system. IP cores may be licensed to another party or can be owned and
used by a single party alone as soft or silicon. IP cores can be used as building
blocks within application-specific integrated circuit (ASIC) designs or field-
programmable gate array (FPGA) logic designs. The Zynq®-7000 All
Programmable family integrates the software programmability of an ARM®-based
processor with the hardware programmability of an FPGA, enabling key analytics
and hardware acceleration while integrating CPU, DSP and mixed signal
functionality on a single device. The project is motivated on the fact of
implementing several peripherals to a FPGA board required by the particular firm
(user) though soft processing and acquiring user based controller, describing
efficiency and comparison of other processor.

iii
 TABLE OF CONTENTS

CHAPTER TITLE PAGE NO

NO
DEDICATION I
ACKNOWLEDGEMENTS ii
ABSTRACT iii
LIST OF FIGURES Vii
LIST OF TABLE Viii
LIST OF ABBREVIATIONS Ix

1 INTRODUCTION 1
1.1 FIELD PROGRAMMABLE GATE ARRAY 1
1.1.1 Partial reconfiguration 2
1.2 ZYNQ FPGA BOARD 2
1.2.1 Zynq zybo 3
1.2.2 Microzed 3
1.2.3 Zedboard 3
1.2.4 ZC702 4
1.3 ZYNQ-7000 ARM FPGA SoC TRAINER 4
BOARD
1.4 KEY FEATURES & BENEFITS 5
1.5 IP CORE (INTELLECTUAL PROPERTY) 6
1.6 SOFT PROCESSORS 6
1.6.1 Why use soft-core processors? 7
1.6.2 Various soft processor offered by vendors 8
1.7 INTEGRATED SOFTWARE DESIGN 8
ENVIRONMENT

iv
 1.7.1Vivado Design Suite - Accelerating High 9
Level Design
1.8 PROPOSED SYSTEM 11

2 LITERATURE SURVEY 12
2.1 INTRODUCTION 12
2.2 RESEARCH PAPER LITERATURE SURVEY 12
2.2.1 Implementing a Run-Time System Manager 12
on Partially Reconfigurable FPGA
2.2.2 The Soft Core Processors: A Review 15
2.2.3Multi-Softcore Architecture on FPGA 17

3 METHODOLOGY 19
3.1 INTRODUCTION 19
3.2 FLOW DESIGN FOR SIMULATION 19
3.3REQUIRED IP BLOCKS AND THEIR 20
INTERFACE
3.3.1 Zynq processing system 20
3.3.2 AXI interconnect 22
3.3.3 General Purpose Input Output (GPIO) 25
3.3.4 Processing system reset 26
3.3.5 AXI quad SPI 26
3.4 SYSTEM REQUIREMENTS 28
3.4.1 VIVADO HLS 2016.4 28
3.4.2 PERIPHERAL MODULES 29
3.4.2.1 Digilent PmodKYPD 29
3.4.2.2 Digilent Pmod OLEDrgb 31
3.5 SYSTEM DESIGN IMPLEMENTATION 32
3.5.1 CHIP TO CHIP 33
3.6 FLOW CHART FOR ARITHMETIC 34
CALCULATOR
3.7 VHDL CODING FOR THE ARITHMETIC 36

v
 CALCULATOR

4 RESULT ANALYSIS
38

4.1 RESULTS 38
4.1.1 Project summary details 39
4.1.1.1 Power analysis 39
4.1.1.2 Utilization 41
4.1.1.3 Elaborate circuit design 42
4.1.1.4 Simulation 43

5 CONCLUSION AND FUTURE SCOPES 45

5.1 CONCLUSION 45
5.2 FUTURE SCOPE 45

REFERENCES 47
APPENDIX 49

vi
 LIST OF FIGURES

FIGURE TITLE PAGE NO.

NO.

Figure 1.1 Basic FPGA evaluation board 1

Figure 1.2 Zynq ZYBO training kit 5
Figure 1.3 Application based usage pyramid 9
Figure 1.4 Internal architecture of Zynq 7000 AP SoC 10
Figure 1.5 Program model of Zynq 7000 11
Figure 2.1 Flow chart for implementing partial reconfiguration 14
Figure 2.2 Multicore architecture 18
Figure 3.1 Typical flow design Xilinx Vivado 19
Figure 3.2 Architecture of Zynq IP block 21
Figure 3.3 Zynq IP block 21
Figure 3.4 AXI interconnect interfaced with Zynq processing 22
system
Figure 3.5 Simulated interface of GPIO 25
Figure 3.6 Simulated interface of processing system reset 26
Figure 3.7 AXI IP block 27
Figure 3.8 16 button Keypad 29
Figure 3.9 LED display 31
Figure 3.10 Final IP block simulation 33
Figure 4.1 Board implementation 38
Figure 4.2 Power analysis from the implemented netlist 40

vii
 Figure 4.3 Design timing summary 41
Figure 4.4 Utilization post implementation 41
Figure 4.5 Utilization post synthesis 42
Figure 4.6 Elaborated circuit design 43
Figure 4.7 Simulation diagram 44
LIST OF TABLES

TABLE NO. TITLE PAGE NO.

Table 2.1 Comparison of soft processor 18

viii
 LIST OF ABBREVIATIONS

AMBA Advanced Microcontroller Bus Architecture

RISC Reduced Instruction Set Computing
AXI AMBA eXtensible Interconnect
LCD Liquid Crystal Display
FPGA Field Programmable Gate Array
DPR Dynamic Partial Reconfiguration
LMB Local Memory Bus
PLB Processor Local Bus
XCL Xilinx Cache Link
EDK Embedded Development Kit
SDK Software Development Kit
IP Intellectual Properties
DDR Double Data Rate
HDL Hardware Descriptive Language
EDA Electronic Design Automation
HLS High Level Synthesis
PMod Peripheral Modules

ix
 CHAPTER 1

INTRODUCTION

1.1 FIELD PROGRAMMABLE GATE ARRAYS

Field Programmable Gate Arrays (FPGAs) have become popular over the
last decade as they allow designers to create complex digital designs at a low
implementation cost (Figure 1.1). Application Specific Circuits (ASICs), in
contrast, introduce a high initial cost and require a large amount of resources to
create complex designs. Modern FPGAs now occupy central positions in
industry because of their capacity for over 1000 multipliers, megabytes of on-
chip memory, hundreds of thousands of logic cells and clock speeds of up to
half a gigahertz. Moreover, the cost per function in FPGAs decreases
significantly over time [9].

Figure 1.1 Basic FPGA evaluation board [9]

1
1.1.1 Partial Reconfiguration

Partial Reconfiguration (PR) is one of the most important features of

modern FPGAs provided by the FPGA vendor Xilinx. It allows modules running
on an FPGA to dynamically reconfigure and swap during execution while the
remaining modules continue operating. PR is an interesting topic for research
among students and researchers in the Reconfigurable Computing and Adaptive
Hardware field. FPGAs are less efficient in area, power and speed than ASICs.
However, it is possible to make them more efficient than a static system when all
or parts of the hardware are reconfigured at run-time through the execution
operation.[10]
The extension of a soft-core instruction set with user-defined instructions used to
speed up the execution of an application in a specific domain can provide huge
PR benefits. Such benefits include integrating different sizes of reconfigurable
modules into the system to be placed on an FPGA at run-time, and being able to
communicate efficiently with the rest of the system and avoiding additional delay.

1.2 ZYNQ FPGA BOARDS

The Zynq-7000 family of SoCs addresses high-end embedded-system

applications, such as video surveillance, automotive-driver assistance, next-
generation wireless, and factory automation. Zynq-7000 integrate a
complete Cortex-A9-processor-based 28 nm system. The Zynq architecture
differs from previous marriages of programmable logic and embedded processors
by moving from an FPGA-centric platform to a processor-centric model. Zynq-
7000 appears the same as a standard, fully featured ARM processor-based system-
on-chip (SOC), booting immediately at power-up and capable of running a variety
of operating systems independently of the programmable logic.[12]

2
1.2.1 Zynq zybo

A good little entry level board with the smallest in the Zynq family, 6
Pmod connectors which is great if you can satisfy your I/O needs with Pmods.
The other options don’t offer so many Pmod connectors on their own. HDMI and
audio is its advantage over the MicroZed. Get the ZYBO if your application is
video/audio and/or you want to take advantage of a few Diligent Pmod
compatible devices.

1.2.2 MicroZed

Best low-cost board purchased with an I/O carrier card to extend the I/O
options. 2 x 50 I/O board-to-board connectors provide opportunity for interfacing
with custom carrier boards. I/O expansion board available if you want to connect
to multiple Pmod devices, add pushbuttons, DIP switches, LEDs, EEPROM,
Xilinx XADC and clock oscillator. The MicroZed, like the ZYBO, has a
minimum of external hardware but the big I/O connectors make it adaptable to a
huge number of applications.

1.2.3 ZedBoard

Best value board in my opinion, with most of the features of the more
expensive boards, the ZedBoard should satisfy a lot of Zynq applications. Pmod
headers for extra I/O. HDMI and audio connections. The ZedBoard sits in the
middle of the range in terms of price but it has great connectivity options.[11]

3
1.2.4 ZC702

Powerful board, comparable to the ZedBoard but it has the advantage of

an extra LPC FMC and the XADC header. 2 LPC FMC connectors provide more
opportunities to get data in and out of the board, for example you could use an
ADC on one, and a DAC on the other. XADC header allows you to take
advantage of the Zynq’s internal low-speed ADC. With respect to the ZedBoard,
the ZC702 allows you to double your I/O options for twice the price, sounds fair
enough.

1.3 ZYBO ZYNQ-7000 ARM/FPGA SoC TRAINER BOARD

The Zybo (Zynq™ Board) is a feature-rich, ready-to-use, entry-level

embedded software and digital circuit development platform built around the
smallest member of the Xilinx Zynq-7000 family, the Z-7010. The Z-7010 is
based on the Xilinx® All Programmable System-on-Chip (AP SoC) architecture,
which tightly integrates a dual-core ARM Cortex-A9 processor with Xilinx 7-
series field programmable gate array (FPGA) logic. When coupled with the rich
set of multimedia and connectivity peripherals available on the Zybo, the Zynq Z-
7010 can host a whole system design. The on-board memories, video and audio
I/O, dual-role USB, Ethernet and SD slot will have your design up-and-ready with
no additional hardware needed. Additionally, six Pmod connectors are available
to put any design on an easy growth path. The Zybo provides an ultra-low cost
alternative to the ZedBoard for designers that don't require the high-density I/O of
the FMC connector, but still wish to leverage the massive processing power and
extensibility of the Zynq AP SoC architecture (figure 1.2).[5]

4
 Figure 1.2 Zynq ZYBO trainer kit[2]

1.4 KEY FEATURES & BENEFITS

 240 KB Block RAM

 28,000 logic cells
 650 MHz dual-core Cortex™-A9 processor
 80 DSP slices
 Audio codec with headphone out, microphone and line in jacks
 DDR3 memory controller with 8 DMA channels
 GPIO: 6 pushbuttons, 4 slide switches, 5 LEDs
 Low-bandwidth peripheral controller: SPI, UART, I2C
 On-chip dual channel, 12-bit, 1 MSPS analog-to-digital converter (XADC)
 Six Pmod ports (1 processor-dedicated, 1 dual analog/digital)
 Xilinx Zynq-7000 (XC7Z010-1CLG400C)
 Micro SD slot (supports Linux file system)

5
1.5 IP core (intellectual property core)

An IP (intellectual property) core is a block of logic or data that is used in

making a field programmable gate array (FPGA) or application-specific
integrated circuit (ASIC) for a product. As essential elements of design reuse, IP
cores are part of the growing electronic design automation (EDA) industry trend
towards repeated use of previously designed components. Ideally, an IP core
should be entirely portable - that is, able to easily be inserted into any vendor
technology or design methodology. Universal Asynchronous
Receiver/Transmitter (UART), central processing units (CPU s), Ethernet
controllers, and PCI interfaces are all examples of IP cores. IP cores fall into one
of three categories: hard cores, firm cores, or soft cores. Hard cores are physical
manifestations of the IP design. These are best for plug-and-play applications, and
are less portable and flexible than the other two types of cores. Like the hard
cores, firm (sometimes called semi-hard) cores also carry placement data but are
configurable to various applications. The most flexible of the three, soft cores
exist either as a net list (a list of the logic gate s and associated interconnections
making up an integrated circuit) or hardware description language (HDL) code. A
number of organizations, such as the Free IP Project and Open Cores, have form
to promote open sharing of IP cores [18].

1.6 SOFT PROCESSOR

A soft processor is an Intellectual Property (IP) core that is implemented

using the logic primitives of the FPGA. Key benefits of using a soft processor
include configurability to trade between price and performance, faster time to
market, easy integration with the FPGA fabric, and avoiding obsolescence. [15]

6
1.6.1 Why use soft-core processors?

When designing an embedded system in a FPGA, we will most likely

need some form of “controller” in our system. This controller can be a simple
microcontroller or a fully-fledged microprocessor running the Linux operating
system. But before we make this decision, let’s first consider the various options
that are available.[4]

Another option is to embed a “hard” processor core on the chip. A hard processor
core has dedicated silicon area on the FPGA. This allows it to operate with a core
frequency similar to that of a discrete microprocessor. Examples of hard processor
cores used in FPGAs are the PowerPC used in Virtex-4/5 and the ARM Cortex-
A9 dual-core MCU used in the new Zynq-7000 All Programmable SoC from
Xilinx.

Hard processor core does not provide the ability to adjust it to better meet the
needs of the application, nor does it allow for the flexibility of adding a processor
to an existing FPGA design or adding an additional processor to provide more
processing capabilities.

A soft-core processor solution is one that is implemented entirely in the logic

primitives of an FPGA. Because of this implementation, the processor will not
operate at the same clock frequencies or have the same performance of a discrete
solution. In many embedded applications, however, the high performance
achieved by the previous two processing options is not required, and performance
can be traded for expanded functionality, reduced cost, and flexibility. All the
major FPGA vendors have soft-core processors in their product offerings and
there are also a number of companies and organizations developing soft-core

7
processors that are platform independent and can be implemented in any FPGA
design.

1.6.2 Various soft processors offered by vendors

 LEON3
 MicroBlaze
 Nios II
 Open RISC

1.7 INTEGRATED SOFTWARE DESIGN ENVIRONMENT

The proven development and verification tools in the Xilinx ISE and
Vivado™ .Design Suites help designers get 7 series FPGA solutions to market
faster and with high quality. The award-winning software includes domain-
specific DSP, embedded-processing and system-level design capabilities. ISE and
Vivado Design Suites include full support for all 7 series devices as well as
advancements that increase team efficiencies for collaborative projects. The
foundation for Next-Generation Targeted Design Platforms Xilinx Targeted
Design Platforms speed time to market and free designers to focus on innovation
and differentiation. The integration of FPGA devices, design tools, and IP into
targeted reference designs that run on development or evaluation boards creates a
robust development and run-time environment. The platforms help designers
more quickly learn about FPGAs and leverage standard or modified tools and IP
to accelerate development. Xilinx teams up with industry leaders to build
customized Base, Domain-Specific, and Market-Specific (Figure 1.3) variations
of the Targeted Design Platform, each introducing common methodologies to
benefit both hardware designers and software application developers. [5]

8
 Figure 1.3 Application based usage pyramid

1.7.1 Vivado Design Suite - Accelerating High Level Design

The Vivado® Design Suite offers a new approach for ultra high
productivity with next generation C/C++ and IP-based design with the new HLx
editions including HL System Edition, HL Design Edition and HL
WebPACK™ Edition. The new HLx editions supply design teams with the tools
and methodology needed to leverage C-based design and optimized reuse, IP
sub-system reuse, integration automation and accelerated design closure. When
coupled with the Ultra Fast High-Level Productivity Design Methodology
Guide, this unique combination is proven to accelerate productivity by enabling
designers to work at a high level of abstraction while facilitating design reuse.

Accelerating High Level Design

 Software-defined IP Generation with Vivado High-Level Synthesis

 Block-based IP Integration with Vivado IP Integrator
9
 Model-based DSP Design Integration with System Generator for DSP

Accelerating Verification

 Vivado Logic Simulation

 Integrated Mixed Language Simulator
 Integrated & Standalone Programming and Debug Environments
 Accelerate Verification by >100X with C, C++ or System C with Vivado
HLS

Accelerating Implementation

 4X Faster Implementation
 20% Better Design Density
 For the low-end & mid-range and 35% Power Advantage in the high-end.

Figure 1.4– Internal architecture of the Zynq 7000 AP SoC

10
 Figure 1.5 – Programming model of ZYNQ 7000

1.8 PROPOSED SYSTEM

The system is based on designing a user defined system using available

intellectual properties for the dedicated to a particular soft processing system, our
purpose is to develop a digital calculator using Pmod peripheral which gives us the
edge to reconfigure the calculation part and customize according to our need. IP blocks
can also be edited for different usage and could be connected with other Pmod when in
need.

11
 CHAPTER 2

LITERATURE SURVEY

2.1 INTRODUCTION

Prior to stating my research, it is important to have a deep understanding

on the existing pages of ZYNQ boards and their user based application
implementation. The main sources of information for the dissertation are books,
journal, theses and dissertations and the internet. There are major areas of reading
in the literature review which are latest. The development on soft processors and
their capabilities and their diverse application.

2.2 RESEARCH PAPER LITERATURE SURVEY

In order to start the project, the first step is to study the research papers
that have been performed previously by other researchers. The paper that is
related to this title are chosen and studied. With the help of this literature survey,
it gives more clear understanding to perform this project.

2.2.1 Implementing a Run-Time System Manager on Partially

Reconfigurable FPGA Systems (Professor Dionisios Pnevmatikatos) Chania,
October 2015.

During recent years several advancements have been made in the FPGA
technology, including but not limited to partial reconfiguration. This new
technology prompted more and more researchers to implement many applications

12
from many different fields on FPGAs taking advantage of PR technology. Also
recently a big part of the research was spent on Operating Systems or Run-Time
System Managers residing on an FPGA system managing the available resources.
In this thesis we present the work done towards the creation and implementation of
an RTSM ported on an actual partially reconfigurable FPGA. In the rest of the
chapter Since the current FPGA technology supports a 2D representation of the
device, the position is described by pairs of x, y coordinates and representing the
bottom-left corner of the rectangle the RR is placed. Regarding the size, for
example, an RR with size 4x5, specifies the number of slices covered by the RR in
x and y dimensions respectively. During the application execution, the RTSM
alters its scheduling decisions in a dynamic fashion. The RTSM reacts according
to dynamic parameters such as the runtime status of each HW/SW task and region,
e.g. executing, idle, scheduled for reconfiguration, scheduled for execution, region
that is free/reconfigured-but-idle/reconfigured-but-active etc. All this information,
about the FPGA condition and the tasks' status, is assessed during run-time and
according to that decisions are made (figure 2.1).

13
 Figure 2.1 Flow chart for implementing partial reconfiguration

In this work we presented the extensions and changes made in order to port and im-
plement an RTSM to an actual partially reconfigurable FPGA system. Several of
theseextensions are towards the creation of a high-level RTSM able to handle HW
and SW tasks comprising one or more applications sharing the same Partially
Reconfigurable device. Also the extensions made have widen the range of
applications the RTSM was able to manage, with the inclusion of loop structures,

14
branches and fork-join operations. Additionally the dynamic changes in execution
times of the tasks offer real dynamically capabilities in our RTSM with which
version, either SW or HW, of a task will be executed. The dynamic changes are
extremely beneficial to the overall execution time of the application.[7]

2.2.2` The Soft Core Processors: A Review

Field Programmable Gate Array (FPGA) devices are used normally for
implementation of parallel algorithms while microprocessors are well known for
sequential algorithms. Application Specific Integrated Circuit (ASIC) design
sometimes need combination of both pertaining to constraints like minimum power
consumption, small area and fewer problems with signal integrity and EMI
(Electromagnetic interference). New industry requirements diminish the life-cycle of
microcontrollers, and several processors became obsolete in shorter periods of time.
The biggest challenge to Hardware architects is fulfillment of new requirements;
which are adaptable characteristics, high performance and power efficiency and
reduction in time to design the product. Flexibility and adaptability are considered
synonyms of reconfigurable technologies. For fast development of System-on-
Programmable-Chip (SoPC), many commercial processors offer memory and logic
elements with a large variety of intellectual Property (IP) peripherals. Also,
reconfigurable systems on a chip became a reality with soft- core processor. The
available Electronic-Design-Automation (EDA) tools help us in constructing
prototypes of Systems-on-a- Chip rapidly and in a very mature way. Hardware
Description Language (HDL) is used for such prototyping. The paper is organized in
four sections as below: Section II summarizes advantages of using soft-core
processors. In section III, a review of several soft-core processors from major

15
 commercial vendors as well as open-source communities is covered. We conclude
with few comments on future work in the area of soft-core processors as well as a
comparison among major soft core processors based on important features such as
clock frequency, word-length, pipeline stages etc.[2]

Table 2.1 Comparison of several soft processors

Soft-core processors are normally used for creating an FPGA based SoC. By virtue of
this technology, we can reduce time periods of processor creation life cycle with the
help of recently available EDA tools. The embedded world is looking forward for more
sophisticated reconfigurable devices with features like least power consumption,

16
highest level of adaptability, small size, capability of run-time reconfiguration and
ability to work with adaptive hardware algorithms (Table 2.1).

2.2.3 Multi-Soft core Architecture on FPGA

The requirements for higher computational capacity and lower cost of future
high-end real-time data-intensive applications like multimedia and image processing
(filtering, edge detection, correlation, etc.) are rapidly growing. As a promising
solution, parallel programming and parallel systems-on-chip (SoC) such as clusters,
multiprocessor systems, and grid systems are proposed. Such sophisticated embedded
systems are required to satisfy high demands regarding energy, power, area, and cost
efficiency. Multicore systems working in SIMD/SPMD (Single Instruction Multiple
Data/Single Program Multiple Data) fashion have been shown to be powerful executers
for data-intensive computations and prove very fruitful in pixel processing domain.
Their parallel architecture strongly reduces the amount of memory access and the clock
speed, thereby enabling higher performance. Such multicore systems are made up of an
array of processing elements (PEs) that synchronously execute the same program on
different local data and can communicate through an interconnection network. These
parallel architectures are characterized by their regular design, which enables design
cost effective scaling of the platform for different performance applications by simply
increasing or reducing the number of processors. Although these architectures have
accomplished a great deal of success in solving data-intensive computations their high
price and the long design cycle have resulted in a very low acceptance rate. Designing
specific solutions is a costly and risky investment due to time-to-market constraints and
high design and fabrication costs. Embedded hardware architectures have to be flexible
to a great extent to satisfy the various parameters of multimedia applications. To
overcome these problems, embedded system designers are increasingly relying on field
programmable gate arrays (FPGAs) as target design platforms. Recent FPGAs provide

17
a high level of logic element density with higher end functioning. The proposed design
aims to imply single architectures combined to a system for better tools design methods
(Figure 2.2) [1].

Figure 2.2 Multicore architecture

18
 CHAPTER 3

METHODOLOGY

3.1 INTRODUCTION

The methodology section deals with design and implementation of

several hardware and software to focus on user defined application. The
procedure thoroughly disserted gives brief knowledge on customizing own
application in FPGA kit with high level synthesis design using Xilinx
VIVADO.[19]

3.2 FLOW DESIGN FOR SIMULATION

The software tool (VIVADO) needs some basic sequence like any other
programming tool/software (figure 3.1).

Figure 3.1 Typical flow design Xilinx VIVADO

19
Design flow using Xilinx Vivado software to create a simple digital circuit using
Verilog HDL. A typical design flow consists of creating models, creating user
constraint files, creating a Vivado project, importing the created models,
assigning created constraint files, optionally running behavioral simulation,
synthesizing the design, implementing the design, generating the bit-stream, and
finally verifying the functionality in the hardware by downloading the generated
bit-stream file.

3.3 REQUIRED IP BLOCKS AND THEIR INTERFACE

The desired IP blocks are arranged in typical fashion for the desired
output, the arithmetic calculator using soft processor. Mentioned Below is the
intellectual properties used as an arranged block.

3.3.1 ZYNQ Processing System

The Processing System IP is the software interface around the Zynq-7000

Processing System. Zynq-7000 family consists of a system-on-chip (SoC) style
integrated processing system (PS) and a Programmable Logic (PL) unit,
providing an extensible and flexible SoC solution on a single die. The Processing
System IP Wrapper acts as a logic connection between the PS and the PL while
assisting you to integrate custom and embedded IPs with the processing system
using the Vivado IP integrator (Figure 3.2). The PL Consist of an Application
Processor unit (APU), Memory interfaces, I/O peripherals (IOP) and
Interconnect. The IP integration with the combination of the PS and the PL
blocks is described (Figure 3.3).[12]

20
Figure 3.2 Architecture of Zynq IP block

Figure 3.3 Zynq IP block

21
3.3.2 AXI INTERCONNECT

The AXI Interconnect IP connects one or more AXI memory-mapped

Master devices to one or more memory-mapped Slave devices. The AXI
interfaces conform to the AMBA AXI version 4 specifications from ARM®,
including the AXI4-Lite control register interface subset (Figure 3.4) . The
Interconnect IP is intended for memory-mapped transfers only; AXI4-Stream
transfers are not applicable. The AXI Interconnect IP can be used from the
Vivado® IP catalog as a IP core from the Embedded Development Toolkit (EDK)
or as a standalone core from the CORE Generator™ IP catalog.[17]

Figure 3.4 AXI interconnect interfaced with ZYNQ processing system

22
3.3.2.1 Introduction of an axi-bus for the xilinx system development

The feature that makes the Zybo Board especially well-fitted for
hardware acceleration applications is the tight coupling between the PS and the
PL. The ARM processors can be connected directly to any component in the PL
area through the set of general purpose AXI ports and an Extended Multiplexed
I/O (EMIO) port. Besides, there are four high performance (HP) AXI4 ports that
PL components can use to access external memory directly. At max capacity, the
HP AXI4 ports have a bandwidth of 1200 MB/s. The second version of the
Advanced eXtensible Interface (AXI4) bus protocol is used to make the PL, which
is part of the ARM Advanced Microcontroller Bus Architecture (AMBA). The
AXI4 is available in the Xilinx ISE Design Suite which can be applied in the
projects. It is suitable for low latency and high bandwidth designs. Differently, the
AMBA provides high-frequency operation without the use of bridges. It fits the
interface requirements of wide range of components and is suitable for memory
controllers.
There are three kinds of AXI4 interfaces:
• AXI4-Full: For high-performance memory-mapped requirements.
• AXI4-Lite: For simple, low-throughput memory mapped communication.
• AXI4-Stream: For high-speed streaming data.
The AXI specification describes an interface between an AXI Master and an AXI
Slave. They are connected and using a structure called Interconnect block, and in
the case of the AXI4-Full and the AXI4-Lite, it is called an AXI Interconnect. It is
used for the memory mapped interfaces only while the AXI4-stream interconnect
can be utilized for the AXI-4 stream bus implementation. Any of those interfaces
are implementable in the PL. Therefore they can be connected directly to the PS
through a set of AXI4 bus ports. In the rest of this section, the AXI specification
and the protocols explained in the details.

23
AXI4-full and AXI4-lite Protocols

The AXI-Full specification proposes a different range of important

features such as variable data and address bus widths with high bandwidth burst
operations. AXI-Bus Interconnect offers advanced caching support and several
transactions assurance access permission. While these features offer the user
flexibility and control, it is often useful to be provided with a much simpler
peripheral which consists of only a subset of these functions. For that reason, a
reduced feature variant of the AXI4-Full specification exists in the form of the
“AXI4-lite”. The AXI4-Lite interconnect provides only necessary interconnect
transactions which are required, and high-level capabilities of interconnect such as
burst support, cache support, and variable bit widths for the address and data buses
has been removed. The AXI4-lite interconnect is suitable for applications where
simple control and status monitoring capabilities are required for a custom built IP
block. Both the AXI-Full and the AXI-Lite have five different channels between
the Master and the Slave. Data between the master and the slave can move in both
directions simultaneously, and data transfer sizes can be different. The AXI4-Full
consists of single address with multiple data with a burst transaction up to 256 data
beats, but AXI4-Lite provides only 1 data transfer per transaction with 32 bits data
width. Due to the advanced semiconductor technology, Field Programmable Gate
Array (FPGA) contains more and more logic gates nowadays. We can even
implement a microprocessor into a single FPGA chip by using hardware
description language, such as VHDL and Verilog. Therefore, FPGA manufacturers
and Open Cores community provide well written soft-core processor for designers
to reduce development time. Xilinx is one of the FPGA manufacturers that support
complete soft processor design flow for academic research and industrial
innovation.

24
 3.3.3 General Puprose input output (GPIO)

General-purpose input/output (GPIO) is a generic pin on an integrated

circuit or computer board whose behavior including whether it is an input or
output pin is controllable by the user at run time (Figure 3.5). GPIO pins have no
predefined purpose, and go unused by default. The idea is that sometimes a system
integrator who is building a full system might need a handful of additional digital
control lines and having these available from a chip avoids having to arrange
additional circuitry to provide them.
.

Figure 3.5 - Simulated interface of GPIO

25
3.3.4 PROCESSING SYSTEM RESET

The Xilinx Processor System Reset Module design allows the customer to
tailor design to suit their application by setting certain parameters to enable/disable
features. The parameterized features of the design are discussed in Processor
System Reset Module Design Parameters (Figure 3.6). [7]

Figure 3.6 Simulated interface of processing system reset

3.3.5 AXI QUAD SPI

The AXI Quad Serial Peripheral Interface connects the AXI4 interface to
those SPI slave devices which are supporting the Dual or Quad SPI protocol along

26
with Standard SPI protocol instruction set. As an example, this core provides a serial
interface to SPI slave devices such as SPI serial flash from Winbond/Numonyx which
support Dual and Quad SPI protocol along with Standard SPI interface. The Dual/Quad
SPI is the enhancement to the Standard SPI protocol that delivers a simple method for a
master and a selected slave to exchange data. Configurable AXI4 interface when
configured with an AXI4-Lite interface the core is backward compatible with version
1.00 of the core (legacy mode).The configurable AXI4 interface for burst mode
operation for the Data Receive Register (DRR) and the Data Transmit Register (DTR)
FIFO. Configurable eXecute In Place (XIP) mode of operation. Connects as a 32-bit
slave on either AXI4-Lite or AXI4 interface

Configurable SPI modes:

o Standard SPI mode

o Dual SPI mode
o Quad SPI mod (Figure 3.7)

Figure 3.7 – Quad AXI IP block interfaced

27
 3.4 SYSTEM REQUIREMENTS

Software:
VIVADO HLS 2016.4
Hardware:
• Zybo Zynq FPGA Board
• Peripherals Modules ( 16 button Keypad & led display)

3.4.1 VIVADO HLS 2016.4

The new Vivado HLx Editions offers a new approach for ultra-high
productivity with next generation platform design automation, C/C++ programming of
the differentiated logic, with graphical system assembly. This approach, described in
the UltraFast High Level Productivity Design Methodology Guide (UG1197), is
proven to accelerate design creation and verification by 15x over RTL-based
methodologies. HLx also complements the Xilinx SDx Development Environments
(SDSoC, SDAccel and SDNet) which are tailored for software and systems engineers.
While the HLx methodology can automate platform design creation, the SDx families
of development environments enable software-defined programming of such platform,
using C, C++, OpenCL, or the emerging P4 language for packet processing. HLx and
SDx represent Xilinx’s new era of software programmability solutions for developing
smarter, connected and differentiated systems leveraging end-product optimized
custom hardware using All Programmable devices including Zynq SoCs, MPSoCs,
ASIC-class FPGAs and 3D ICs.[6]

28
3.4.2 PERIPHERAL MODULES

3.4.2.1 Digilent PmodKYPD

Digilent PmodKYPD is a 16 button keypad, providing users with immense

configurability (Figure 3.8).

 16 momentary push-buttons

 Can detect simultaneous button presses

 Isolated rows and columns

 Small PCB size for flexible designs 3.4“× 2.7” (8.6 cm × 6.9 cm)

 12-pin Pmod port with GPIO interface

Figure 3.8 - 16 button keypad

29
VHDL coding for interfacing keypad

The PmodKYPD communicates with the host board via the GPIO protocol.
Each button is placed within a simple voltage divider circuit. When a button is not
pressed, a large pull-up resistor maintains a logic level high voltage on each of the
row pins. A column pin is driven to a logic level low voltage and a corresponding
The PmodKYPD [3].

entity PmodKYPD is
Port (
clk : in STD_LOGIC;
JA : inout STD_LOGIC_VECTOR (7 downto 0); -- PmodKYPD is
designed to be connected to JA
an : out STD_LOGIC_VECTOR (3 downto 0); -- Controls which
position of the seven segment display to display
seg : out STD_LOGIC_VECTOR (6 downto 0)); -- digit to display on
the seven segment display
end PmodKYPD;
architecture Behavioral of PmodKYPD is
component Decoder is
Port (
clk : in STD_LOGIC;
Row : in STD_LOGIC_VECTOR (3 downto 0);
Col : out STD_LOGIC_VECTOR (3 downto 0);
DecodeOut : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component DisplayController is
Port ( DispVal : in STD_LOGIC_VECTOR (3 downto 0);
anode: out std_logic_vector(3 downto 0);
segOut : out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal Decode: STD_LOGIC_VECTOR (3 downto 0);
30
 begin

C0: Decoder port map (clk=>clk, Row =>JA(7 downto 4), Col=>JA(3 downto
0), DecodeOut=> Decode);
C1: Display Controller port map (DispVal=>Decode, anode=>an, segOut=>seg );
end Behavioral;

3.4.2.2 Digilent Pmod OLEDrgb

The RGB LED module with a 96×64 pixel display capable of 16-bit
color resolution (Figure 3.9).

 96×64 pixel RGB OLED screen

 0.8 x 0.5 graphical display
 16-bit color resolution
 Two low-power display shutdown modes
 12-pin Pmod connector with SPI interface

Figure 3.9 Led display

31
 Interfacing OLED display

The PmodOLEDrgb communicates with the host board via the SPI
protocol. By driving and keeping the Chip Select (CS) line at logic level low, users
may send both commands and data streams to the display controller based on the
state of the Data/Command (D/C) pin. As a graphical display interface, users may
light up any individual pixel on the OLED, display predefined characters, or even
load bitmaps onto the screen. Each pixel can be set to one of the 65,535 colors that
are available. The OLED display has a specific power-up and power-down
sequence to ensure the longevity of the device. There are two field-effect transistors
(FETs) that control the display’s two power supplies. The VCCEN control toggles
the positive voltage supply to the screen itself and the PMODEN control toggles the
power supply ground to the display. Users may turn off either one of these controls
to reduce the power consumption of the PmodOLEDrgb to approximately 200
mA.[16]

3.5 SYSTEM DESIGN IMPLEMENTATION

The intellectual properties discussed are simulated with proper connections

(Figure 3.10). The sources must be added to Zynq IP block for carrying out user
defined application, here arithmetic calculator. [8]

32
 Figure 3.10 - Final IP block simulation

3.5.1 CHIP TO CHIP

The LogiCORE IP AXI Chip2Chip is a soft Xilinx IP core for use with the
Vivado Design Suite. The adaptable block provides bridging between AXI systems for
multi-device System on-chip solutions. The core supports multiple device-to-device
interfacing options and provides a low pin count, high performance AXI chip-to-chip
bridging solution.

The LogiCORE IP AXI Chip2Chip core functions like a bridge to

seamlessly connect two devices over an AXI interface. The core transparently bridges
transactions in compliance with AXI protocol specifications. The bridging function
allows all AXI channels to operate independently by forwarding per-channel data and
control information in compliance with AXI per-channel Valid-Ready handshake. The
optional AXI4-Lite functions in the core are independent of AXI4 Interface functions.
The AXI4-Lite interface can be used for low-bandwidth access such as
configuration/status registers of a peripheral Master/Slave. The AXI Chip2Chip Master

33
instance provides an AXI4 slave interface that can be directly connected to AXI Master
or AXI interconnect devices. The AXI Chip2Chip Slave instance provides an AXI4
Master interface that can be connected to AXI Slave or AXI interconnect devices. The
bridging functions in AXI Chip2Chip cores convert the wide on-chip AXI signaling to
a compact device-to-device interfacing by utilizing a minimum set of device I/Os. The
AXI Chip2Chip bridging also implements functions that provide error-free
communication over the device I/Os. The AXI4-Lite configuration option allows
master or slave mode selection. For example, when the processor is connected to an
AXI Chip2Chip Master instance, then an AXI4-Liteinstance can be set to master mode;
this setup will provide an AXI4-Lite slave interface. When peripheral Masters are
connected to an AXI Chip2Chip Master instance, then an AXI4-Lite instance can be
set to slave mode and it will provide an AXI4-lite master interface.AXI Chip2Chip
operations can be categorized into five modules: AXI4 Interface, AXI4-LiteInterface,
Channel Multiplexer, Link Detect FSM, and PHY interface.

3.6 FLOW CHART FOR ARITHMETIC CALCULATOR

34
35
3.7 VHDL CODING FOR THE ARITHMETIC CALCULATOR

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
my_alu is Port
( clk:in std_logic;
A : in std_logic;
B : in std_logic;
I : in std_logic_vector (2 downto 0);
R : out std_logic_vector (3 downto 0));
end my_alu;
architecture Behavioral of my_alu is
begin
process(A, B, clk)
variable temp : integer ;
begin
if (clk'event and clk='1' )then case I is when "000" => --Add (R=A+B)
temp := conv_integer(A)+ conv_integer(B);
R <= transport conv_std_logic_vector(temp,4) after 10 ns ;
when "001" => --Subtract (R=A-B) temp := conv_integer(A) - conv_integer(B);
R <= conv_std_logic_vector(temp,4);
when "010" => -- (R=not of A0)
if (A='0') then R <=conv_std_logic_vector('1',4);
else R <=conv_std_logic_vector('0',4);

36
 end if;
when "011" => -- (R=A equal to B) if A = B --then temp:= '1';
then R <=conv_std_logic_vector('1' ,4);
else R <=conv_std_logic_vector('0' ,4);
end if;
when "100" => -- (R=A incremented by 1) 65 temp := (conv_integer(A))+ 1;
R <=conv_std_logic_vector(temp,4);
when "101" => -- (R=A modulus to B) temp := conv_integer(A) mod 10;
R<= conv_std_logic_vector(temp,4);
when "110" => -- (R=remainder of A) temp := conv_integer(A)rem 10;
R<= conv_std_logic_vector(temp, 4);
when others=> R<="1111";
end case;
end if;
end process;
end Behavioral;

37
 CHAPTER 4

RESULT ANALYSIS

4.1 RESULTS
After the successful implementation of the IP blocks, the system validation is
checked and designed blocks are shown, the occupied blocks with logics is shown in
sky blue color (Figure 4.1). More the number of components and more is the DSP
blocks, RAMs, LUTs are being used during synthesis.

Figure 4.1 Board implementation

38
4.1.1 Project summary details

The Design Summary allows you to quickly access design overview

information, reports, and messages. By default, the Design Summary appears in the
Workspace when you open a project, and it displays information specific to your
targeted device and software tools

 Project Status - shows high-level design information, including the following:

o Design Strategy - shows the currently enabled design strategy. You can
change the strategy as described in Using Design Goals and Strategies.
o Environment - shows the System Settings for your design, including
Xilinx® environment variable settings, process property settings, and
operating system information.
 Device Utilization Summary - shows information to assist with device
utilization analysis, as described in Analyzing Device Utilization.
 Detailed Reports - provides access to reports that are generated as you process
your design.
 Secondary Reports - provides access to the secondary reports of your choice,
as described in Showing or Hiding Messages and Reports.

4.1.1.1 Power analysis

The power from transistor leakage on all connected voltage rails and the
circuits required for the FPGA to operate normally, post configuration. Device static
power is a function of process, voltage and temperature. This represents the steady
state, intrinsic leakage in the device.

39
 Figure 4.2 - Power analysis from the implemented netlist

The power of user design due to the input data pattern and the designed internal
activity can be described. This power is instantaneous and varies at each clock cycle.
It depends on voltage levels and logic and routing resources used. This also includes
static current from I/O terminations, clock managers, and other circuits which need
power when used. It does not include power supplied to off-chip devices (Figure 4.2).

The Timing Summary section is an overview (Figure 4.3) of the design that includes:

 Timing errors, which is the cumulative number of errors for the entire design.
 Score, which is the sum of all timing errors in pico second.
 Constraints coverage, which shows the number of paths, net and connections
covered by constraints.
 Design statistics, which shows the overall period, input, and output times. It is
for all clocks and is limited by the slowest path.

40
 Figure 4.3 – Design Timing Summary

4.1.1.2 Utilization

The usage estimation of functional blocks for post implementation and

post synthesis is also summarized for a better understanding of basic blocks like
RAM, DSP blocks ,LUT .

Figure 4.4 Utilization post implementation

41
 Figure 4.5 Utilization post synthesis

All these summary description gives the idea to implement more efficient
designing and synthesis of intellectual properties. The summary will react to each
and every change made post implementation thus gives a proper tracing of
utilization (Figure 4.4 & Figure 4.5).

4.1.1.3 Elaborate circuit design

Software is capable of giving elaborated design, i.e. Real time embedded

designing for implementing the IC in a PCB board (Figure 4.6).

42
 Figure 4.6 Elaborated circuit design

4.1.1.4 Simulation

The parameters given in the program can be seen in simulation and can be
verified without any hardware kit. The VHDL code given to the zynq processing
system simulated and the port assingned ar shown (Figure 4.7).

43
Figure 4.7- Simulation diagram

44
 CHAPTER 5

CONCLUSION AND FUTURE SCOPES

5.1 CONCLUSION

The system is designed for a user defined system using available intellectual
properties for the dedicated for a particular soft processing system, our purpose to
develop a digital calculator using Pmod peripheral was developed, which gave us the
edge to reconfigure the calculation part and customize according to our need. IP
blocks was connected and interfaced with Pmod.

Xilinx VIVADO 2016.4 was used a base software for simulating design in ZYBO
board. The user accountability and cost effectiveness of Zybo board was the main
motivation of using this board. Pmod interfacing in Zybo board is comparatively
easier to other boards.

5.2 FUTURE SCOPE

The system can further be developed to make a full arithmetic logical

unit(ALU) .The ALU is a fundamental building block of the central processing unit
(CPU) of a computer, and even the simplest microprocessors contain one for
purposes such as maintaining timers. The ALU can be inside high speed computers
and even supercomputers .It will find its requirement in the field of nano technology.
Commercially it would be very useful in the smart mobile phones and calculating
devices. The processors found inside modern CPUs and graphics processing units

45
(GPUs) accommodate very powerful and very complex ALUs; a single component
may contain a number of ALUs. Hence the ALU interfaced with various devices will
find its application in almost every electronic device. Full ALU can be designed and
simulated with proper IP blocks.

46
REFERENCES

1 .Mouna Baklouti and Mohamed Abid “Multi-Soft core Architecture on FPGA”

Hindawi Publishing Corporation International Journal of Reconfigurable
Computing, 2014
2. J. B. Nade1, Dr. R. V. Sarwadnya ,”The Soft Core Processors: A Review”
international journal of innovative research in electrical, electronics, instrumentation
and control engineering vol. 3, Issue 12, December 2015.

3. Charles H Roth :DIGITAL SYSTEM DESIGN USING VHDL, University of Texas

,PWS Publisher, 2002.

4. Rehab Abdullah Shendi, “ RUN-TIME CUSTOMIZATION OF A SOFT-CORE

CPU ON AN FPGA” UNIVERSITY OF MANCHESTER, 2015.

5. Louise H. Crocket and Ross A. Elliot: The Zynq Book Tutorials. University of
Strathclyde Glasgow, Scotland,UK, 2015.

6. System level synthesis (4/04/2017)” IP cores”[ Xilinx.com ] ,available

https://www.xilinx.com/Vivado_design_suite_user guide.html

7. LogiCORE IP Processing System 7 (5/3/2017) “IP Processing” [Xilinx.com],

https://www.xilinx.com/support/documentation/ip_documentation/processing_system7
/v4_00_a/ds871_processing_system7.pdf

8. Customised IP block(25/03/2017) “creating basic blocks of IP” [FPGA developer],

https://Creating%20a%20custom%20IP%20block%20in%20Vivado%20_%20FPGA%
20Developer.html

9. FPGA (29/02/2017) “what is FPGA “[whatitis.techtarget.com]

http://whatis.techtarget.com/definition/field- programmable-gate-array-FPGA.

47
10. Partial Reconfiguration (02/03/2107) ,” IP vendors and design”
https://pdfs.semanticscholar.org/0863/cb49ed8b54f1e98f9349b68c28e6ebf3dad
11 Virtex-6 FPGA, Xilinx (2013) (1/03/2107), “types of FPGA” [Xilinx]
http://www.xilinx.com/support/documentation/data_sheets/ds150.pdf. Accessed 12
Dec 2013.
12 Zynq-7000 All Programmable SoC Technical Reference Manual(29/02/2017)
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-
TRM.pdf

13 FPGA vendors provide design software that support their device

http://www.fpga4fun.com/FPGAsoftware1.html

14. Bryan H. Fletcher, “FPGA Embedded Processor Revealing True System

Performance”, Embedded Training Program, Embedded Systems Conference and San
Francisco, , 2013

15. Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen D. Brown “Experiences
with Soft-Core Processor Design”,19th IEEE International Parallel and Distributed
Processing Symposium ,2015.

16. C. Oberhauser, Texas Instruments Applications Report LDC Sensor Design ,

Mar.2015.
&id=523&chk=222579d07d3e13fde74ae411749ae30e&Itemid=591.
17. AMBA® AXI4 specification
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022d/index.htmlAM
BA® AXI4-Stream Protocol Specification
18 Vivado® Design Suite User Guide: Designing IP Subsystems using IP Integrator
19. design flow (20/03/2017) “sequence in Vivado”
https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html.

48
APPENDIX : SUCCESSFUL REPORT

Found 1-bit adder carry out for signal <R$addsub0000> created at line 49.
Found 1-bit adder carry out for signal <R$addsub0001> created at line 75.
Found 4-bit 8-to-1 multiplexer for signal <R$mux0001> created at line 47.
Found 1-bit subtractor for signal <R$sub0000> created at line 54.
Found 1-bit xor2 for signal <R$xor0000> created at line 66.
Summary:
inferred 3 Adder/Subtractor(s).
inferred 4 Multiplexer(s).

HDL Synthesis Report

Macro Statistics
# Adders/Subtractors : 3
1-bit adder carry out : 2
1-bit subtractor : 1
# Latches : 1
4-bit latch : 1
# Multiplexers : 1
4-bit 8-to-1 multiplexer : 1
# Xors : 1
1-bit xor2 : 1

Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors : 3
1-bit adder carry out : 2
1-bit subtractor : 1
# Latches : 1

49
4-bit latch : 1 70

NGDBUILD Design Results Summary:

Number of errors: 0
Number of warnings: 10
Writing NGD file "calculator.ngd" ...
Writing NGDBUILD log file "calculatoe.bld"...
NGDBUILD done.
Process "Translate" completed successfully Using target part "4vfx12ff668-10".
Mapping design into LUTs
Running directed packing.
Running delay-based LUT packing... 73

Running related packing...

50
51
52