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Vcc (TTL)
Ø
VDD(MOS)
Ø
Power Dissipation :-
Noise margins – amount of “noise” a signal can tolerate going from an outp
an input.
Currents and voltages in the two
logic states
O – output
I – input
H – high
L - low
Comparison of current-sourcing
and current-sinking actions
Logic Families
• RTL : Resistor transistor logic
In Diode logic, all the logic is implemented with the use of resistors and diodes
•
oThe disadvantage of Diodes is that they tend to degrade the signals quickly.
oDiodes also cannot work for multiple stages, only one stage at a time.
oThe diodes also cannot perform the NOT operation which limits their functionality.
Resistor-Transistor Logic (RTL)
üIn resistor-transistor logic, all the logic is implemented with the use of transistors
and resistors
üResistor-Transistor gates are not very expensive and are very simple to
construct.
ü RTL gates can be used as amplifiers as well to amplify small signals.
ü The drawback in using RTL gates is that they draw a great amount of current
from the power supply.
üThey are used in slower applications, but cannot be used in today's computers as
they cannot switch at high speeds.
1. If any input is high the corresponding transistor is driven into
saturation
2. This causes output as low
3. If all input are low at 0.2v all transistors are cutoff because
Diode Transistor Logic (DTL)
ØIn Diode-transistor logic, all the logic is implemented with the use of diodes
and transistors.
ØDTL has some advantages over DL and RTL. As the diodes can perform AND
and OR operations but along with a transistor the output signal can be amplified
ØThe switching speed of the transistor is limited due to the input resistor to
transistor.
If all the inputs are high the transistor is driven into saturation
region
The voltage at Y equal to VBE plus the two diode drops across D4
& D5.
8-2 The Transistor-Transistor-Logic
(TTL) Logic Family
The NAND gate is a basic TTL circuit.
8-2 The TTL Logic Family
TTL circuits have a similar structure
The input will be the cathode of a PN junction
A HIGH input will turn off the junction and only a leakage
current is generated in Q1 (Q2 and Q4 turn on).
A LOW input turns on the junction and a relatively large current
is generated through Q1 (Q2 and Q4 turn off).
Most TTL circuits have some type of totem-pole output
configuration
TTL
NAND
gate in its
two output
states
TTL NAND gate with output low
TTL NAND gate with output high
Flow of Current in TTL Output State
Figure 8-9 (a) When the TTL output is in the LOW state, Q4 acts as a current sink, deriving its current from the load. (b) In the output
HIGH state, Q3 acts as a current source, providing current to the load gate.
TTL NOR gate circuit
Q2 and Q4
added to
TTL
inverter
ECL is considered to be one of the best because there is a very low propagation
v
delay.
The logic levels for ECL are normally -0.9V for high logic and -1.6 for low logic.
v
The design of ECL consists of termination resistors which allows the signals to
v
Determine the load that gate 1 is driving, the 74LS devices have IIH = 20uA, and IIL
= 0.4mA.
Leakage
• •Gates 2 and 3 have
currents. one input transistor.
Each input •Gate 4 uses a
Calculating fan-out
• Max sink current for LS device in low state, fan-out x IIL = 20 x -0.4mA =
-8mA.
Max supply current for LS device in high state, , fan-out x IOH = 20 x -0.4mA = -8mA.
•
Magnitude of current needed by load should be less than magnitude of max sink or source current.
•
Figure 8-56 Problems 8-11 and 8-13.
N-channel
MOSFET used as a
switch: (a) symbol;
(b) circuit model;
(c) N-MOS inverter
operation.
P-channel MOSFET
P-channel
MOSFET used as
a switch: (a)
symbol; (b)
circuit model for
OFF and ON; (c)
P-MOS inverter
circuit.
8-8 Complementary MOS Logic
The CMOS family uses both P and N channel
MOSFETs
Faster
Consumes less power
More complex fabrication
CMOS Inverter (Figure 8-22)
CMOS NAND gate (Figure 8-23)
CMOS NOR gate (Figure 8-24)
CMOS INVERTER
CMOS NAND gate
CMOS NOR gate
8-9 CMOS Series Characteristics
Figure 8-25 Current spikes are drawn from the VDD supply each time the output switches from LOW to HIGH. This is due mainly to the
charging current of the load capacitance.
8-10 Low Voltage Technology
CMOS family:
74LVC (low voltage CMOS)
74ALVC (advanced low voltage CMOS)
74LV (low voltage)
74AVC (advanced very low voltage CMOS)
74AUC (advanced ultra-low voltage CMOS)
74AUP (advanced ultra-low power)
74CBT (cross bar technology)
74CBTLV (cross bar technology low voltage)
74GTLP (gunning transceiver logic plus)
74SSTV (stub series terminated logic)
74TVC (translation voltage clamp)
8-10 Low Voltage Technology
BiCMOS family:
74LVT (low voltage BiCMOS technology)
74ALVT (advanced low voltage BiCMOS
technology)
74ALB (advanced low voltage BiCMOS)
74VME (VERSA Module Eurocard)
Voltage-level comparison
8-11 Open Collector/Open Drain Outputs
Both devices
on or both off
Figure 8-45 Example 8-12: 74HC4016 bilateral switches used to switch an analog signal to two different outputs.
Problem 8-37. Determine the waveform at X assuming Ron = 200Ω
Problem 8-14
Figure 8-57 Problem 8-14. The master reset is active-high and is activated by a push-button switch. Resistor R is used to hold MR LOW
while the switch is open. (a) What is the maximum value that can be used for R? (b) Repeat if using a 74ALS193
Power drain generally increases with, an increase in VDD and frequency; therefore, (b) is
probably has the lowest average PD.
CMOS cross-section
Prob. 8.27 Determine the logic expression for
output X.
Outputs obtained
by using the inputs
to either “pull-up”
the network to
VDD, or “pull-
down”
E. John, S. Yamashita, D. Markovic, andto ground.
Y. Kado, CMOS Circuits, in Digital Design and
Fabrication, Ed. V. G. Oklobdzija , CRC Press 2008, eBook ISBN: 978-0-8493-8604-6.
ass Transistor/Transmission Gate Lo
output.
well.
For a XOR gate, when both A and B are low, the top
•
feedback loop.
continually.
sensing.
can be
combined to form an edge-triggered
flip-flop.
voltage.
ECL is 2 to 5 times faster than CMOS but ECL has high power
consumption which makes VLSI difficult
on causing Q1 to conduct,
while M2 and Q2 are off.
The results is a LOW output.
on causing Q2 to conduct,
while M1 and Q1 are off.
The results is a HIGH
output.
BiCMOS Inverter
•When input is HIGH
(output is LOW), current in
M2 is multiplied by β in Q2
resulting in more current at
the output and faster
operation than CMOS.
capacitance-driving
capabilities.
• Built-in voltages like VBE(on) do not scale, which limits the range of supply voltages
that can be used.
• The non-scalability of built-in voltages is one of the most important deficiencies of bipolar technology.
ECL Inverter
F = (X + Y + Z)’ F=X+Y+Z
50Ω resistors only used for protecting transistors from large current, and can often be eliminated
•
Emitter-Coupled Logic (ECL)
When the emitter circuits are connected together they may form
•
Procedure:
•Design a network for given logic function and its complement using NOR gates
Series gating
Series
gating