Instrumentation Amplifier

®
Instrumentation Amplifier Application Note
Application Note May 27, 2009 AN1298.2
Table of Contents
Introduction to the Instrumentation Amplifier................................................................................................................................... 2
Review of Standard Instrumentation Amplifier Design Techniques ................................................................................................ 2
Monolithic Instrumentation Amplifier Architecture ........................................................................................................................... 4
Introduction to Instrumentation Amplifier Product Family................................................................................................................ 4
Instrumentation Amplifier Specifications ......................................................................................................................................... 4
Instrumentation Amplifier Product Family Theory of Operation....................................................................................................... 6
Features of Instrumentation Amplifier Product Family .................................................................................................................... 7
Care and Feeding of Instrumentation Amplifiers ............................................................................................................................. 10
Application Circuits.......................................................................................................................................................................... 20
Pressure Sensor Interface Circuit ................................................................................................................................................... 21
Thermocouple Input with A/D Converter Output ............................................................................................................................. 22
Thermocouple Input with 4mA to 20mA Output Current ................................................................................................................. 23
RTD Input with A/D Converter Output ............................................................................................................................................. 24
Low Voltage High Side Current Sense............................................................................................................................................ 27
Multiplexed Low Voltage Current Sense ......................................................................................................................................... 30
Bi-Directional Current Sense........................................................................................................................................................... 32
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright Intersil Americas Inc. 2007, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1298
Introduction to the Instrumentation An Instrumentation Amplifier is a confused animal –

Amplifier confused by its cousin, the op amp.
This Application Note describes the Intersil bipolar and MOS • Its symbol looks like an op amp (see Figure 1)
input (see Table 1). Instrumentation Amplifiers, theory of • It has many of the same basic properties and
operation, advantages, and typical application circuits. specifications as an op amp Offset Voltage, Input Bias
These devices are micropower Instrumentation Amplifiers Current, CMRR, PSRR, etc.
which deliver rail-to-rail input amplification and rail-to-rail
• You can make an Instrumentation Amplifier from a simple
output swing on a single 2.4V to 5V supply. These
op amp circuit.
Instrumentation Amplifiers deliver excellent DC and AC
specifications while consuming only 60µA typical supply But the behavior of an Instrumentation Amplifier is
current. Because they provide an independent pair of profoundly different than an op amp! And it is very difficult to
feedback terminals to set the gain and to adjust output level, make a precision Instrumentation Amplifier from a simple op
these Instrumentation Amplifiers achieve high amp circuit – many have tried, but most have failed.
common-mode rejection ratios regardless of the tolerance of
An Instrumentation Amplifier provides a voltage subtraction
the gain setting resistors. The ISL28271 and ISL28272 have
block followed by a fixed gain block; i.e.
an ENABLE pin to reduce power consumption, typically less
V OUT = ( IN+ – IN- ) × Gain (EQ. 1)
than 5.0µA, while the Instrumentation Amplifier is disabled.
TABLE 1.
Often, there is an optional output reference input which
MINIMUM allows the output voltage to be shifted by a fixed voltage:
INPUT # OF CLOSED BW
PART STAGE AMPLIFIERS LOOP GAIN (kHz) ENABLE? V OUT = ( IN+ – IN- ) × Gain + V REF (EQ. 2)
EL8170 Bipolar 1 100 192 No
EL8171 PMOS 1 10 450 No IN+ +

VOUT
IN- -
EL8172 PMOS 1 100 170 No GAIN
EL8173 Bipolar 1 10 396 No

VREF
ISL28270 Bipolar 2 100 240 No
FIGURE 3.
ISL28271 PMOS 2 10 180 Yes
In contrast, an op amp by definition only provides extremely
ISL28272 PMOS 2 100 100 Yes
high gain with provisions to apply negative feedback to
ISL28273 Bipolar 2 10 230 No establish a fixed gain or unique transfer function, H(s), such
ISL28470 Bipolar 2 100 240 No as an integrator or filter.
+VCC +VCC Review of Standard Instrumentation

Amplifier Design Techniques
+ + Difference Amplifier
VOUT VOUT
-
- In its most basic topology, an Instrumentation Amplifier can
be configured from a single op amp and four resistors as
-VCC -VCC shown in Figure 4; this is often referred to as a Difference
Amplifier.
OP AMP INSTRUMENTATION AMPLIFIER
FIGURE 1.
R2 R1 R2
R1
-
-
IN- + VOUT = (IN+ - IN-) * (1 + R2/R1)
+
IN+
FIGURE 2. TWO OP AMP INSTRUMENTATION AMPLIFIER
2 AN1298.2
May 27, 2009
and a common voltage of 10V, the inputs to the op amp will

R2
be sitting at a voltage of 9.9V. This circuit would not be
R1 possible if the op amp was operated with VCC of +5V since
IN- - the op amp input’s voltage would exceed the supply voltage.
VOUT R2
IN+ +
R3 100k
R4 VCC
R1
1k
Vcm = 10V -
VREF VOUT
+
FIGURE 4. R3
1k
R4
In this configuration, the gain is set by resistors R1 and R2: 100k
Gain = R 2 ⁄ R 1 (EQ. 3)
VREF
V OUT = ( IN+ – IN- ) × Gain + V REF (EQ. 4) FIGURE 5.
For the ability to reject a voltage that appears on both IN- Two Amplifier Instrumentation Amplifier
and IN+ (i.e., common mode voltage), resistor values must
To provide a high input impedance, a two amplifier
match such that R1 = R3 and R2 = R4. The common mode
Instrumentation Amplifier can be used as in Figure 6.
rejection ratio (CMRR) is set by the matching ratio of R1:R3
R2 R1 R4
and R2:R4. High common mode rejection ratio requires a
very high degree of ratio matching.
It can be shown that the CMRR is: -

R3
-
CMRR = 20 × log 10 (x) (EQ. 5) IN- + VOUT
+
Where x = R 4 ⁄ ( R 3 + R 4 ) × ( R 1 + R 2 ) ⁄ R 1 – R 2 ⁄ R 1 (EQ. 6) IN+
FIGURE 6. TWO AMPLIFIER INSTRUMENTATION AMPLIFIER

Worse case CMRR occurs when the tolerance of R4 and R1
are at their maximum, and R2 and R3 are at their minimum In this configuration, the gain is set by resistors R3 and R4:
value. The following table shows the relationship between (EQ. 7)
resistor tolerance and CMRR for gains of 1, 10, and 100. Gain = 1 + R 4 ⁄ R 3
TABLE 2.
V OUT = ( IN+ – IN- ) × Gain (EQ. 8)
RESISTOR CMRR
TOLERANCE GAIN =1 GAIN = 10 GAIN =100

The ability to reject a voltage that appears on both IN- and
IN+ (i.e., common mode voltage), depends on matched
±5% -20.4dB -15.6dB -14.8dB resistor values such that, R1 = R3 and R2 = R4. The common
±1% -34.1dB -28.9dB -28.1dB mode rejection ratio (CMRR) is set by the matching ratio of
±0.1% -54.0dB -48.8dB -48.0dB
R1:R3 and R2:R4, and, high CMRR requires a very high
degree of ratio matching. For example, with 10V of common
±0.01% -74.0dB -68.8dB -68.0dB mode voltage, resistor tolerance’s must be at least ±0.01%
to achieve 12-bit accuracy (72dB).
The Difference Amplifier has the advantage of simplicity and
the ability to operate with high common mode voltage on its Classic Three Amplifier Instrumentation Amplifier
inputs, IN+ and IN-. However, the input resistance is set by By adding a third op amp, the “Classic Three Amplifier
the resistor values R3 and R4, and does not provide high Instrumentation Amplifier” can be configured as shown in
input resistance as is common in most Instrumentation Figure 7.
Amplifier circuits.
Additionally, the REF input must be driven by a very low

source impedance since the CMRR will be degraded by any
source resistance that contributes to the value of R4 and
causes increased mismatch between R2 and R4.
Also note that the common mode voltage will bias internal
nodes at a voltage that is set by the ratio of R3 and R4, or the
gain of the circuit. For example, in Figure 5, for a gain of 100
3 AN1298.2
May 27, 2009
R1 R2
Introduction to Instrumentation Amplifier
IN- +
-
Product Family
V2
IN+
R5
- VIN
Rg VOUT V1
IN-
R6 +
VOUT VOUT
V4
FB+
- R3 R4
VREF V3
FB- Rf
IN+ +
FIGURE 7. CLASSIC THREE AMPLIFIER INSTRUMENTATION

AMPLIFIER
Rg
Usually, resistors R1 through R6 are equal value resistors of
R and the gain:
Gain = ( 1 + 2 × R ⁄ R gain ) (EQ. 9) FIGURE 8. TWO AMPLIFIER INSTRUMENTATION AMPLIFIER
V OUT = ( IN+ – IN- ) × Gain + V REF (EQ. 10) This Application Note describes the Intersil Instrumentation
Amplifier Product Family, which includes the following
With this circuit, the Gain can be set with a single resistor, features:
RGAIN and the input impedance is very high. However, the
common mode rejection ratio, CMRR, just like the Difference 1. Bipolar transistor inputs for low voltage noise
Amplifier topology, is still set by the resistor matching 2. PMOS transistor inputs for low input bias current
between R1, R2, R3, and R4. Extremely low tolerance 3. Micropower operation requiring only 60μA supply current
resistors or precision resistor trimming is required to achieve 4. Rail-to-rail inputs and rail-to-rail output swing
high CMRR. The equations and Table shown for the 5. Single supply operation from 2.4V to 5V supply
Difference Amplifier apply directly to the Classic Three
6. An independent pair of feedback terminals to set the gain
Amplifier Instrumentation Amplifier configuration.
and to adjust output level allow these Instrumentation
Amplifier to achieve high CMRR (>104dB) regardless of
Monolithic Instrumentation Amplifier the tolerance of the gain setting resistors.
Architecture 7. Internal loop compensation to provide optimum
Each of the three basic Instrumentation Amplifier architectures bandwidth trade-off as shown in Table 1
that have been already discussed have been implemented in 8. The ISL28271 and ISL28272 have an ENABLE pin to
standard integrated circuit packages. To achieve a high CMRR, reduce the supply current to a typical of less than 5µA and
extensive resistor trimming is required with lasers or other tri-state the output stage to a high impedance state.
suitable techniques. While each of these devices provide
adequate specifications for a precision Instrumentation Instrumentation Amplifier Specifications
Amplifier, each device has its own compromise based on Many of the Instrumentation Amplifier specifications are very
operating voltage range, supply current, common mode similar to the standard specifications for operational
operating range, input impedance, etc. These instrumentation amplifiers. However, the unique architecture of the Intersil
amplifiers use one external resistor to set the gain; while this Instrumentation Amplifiers make some of these
may seem to be an advantage, there are considerations which specifications differ slightly. Table 3 summarizes the
make the single resistor configuration undesirable from a Specifications and Features of the Instrumentation Amplifier
design viewpoint. The temperature coefficient (TC) of the Product Family.
external resistor will be a direct gain drift. Also, an external filter
can not be applied to the feedback network because it is
internal to the device.
4 AN1298.2
May 27, 2009
TABLE 3.
PARAMETERS EL8170 ISL28270 ISL28470 EL8173 ISL28273 EL8171 ISL28271 EL8172 ISL28272 UNITS
Input Stage Bipolar Bipolar PMOS PMOS
Minimum Gain 100 10 10 100
Gain Set 2 Ext R 2 Ext R 2 Ext R 2 Ext R
Supply Current: Enabled 65 65 65 60 65 60 µA

per Channel
Supply Current: Shutdown - - - - - 4 - 4 µA
Minimum VCC 2.4 2.4 2.4 2.4 VDC
Maximum VCC 5.5 5.5 5.5 5.5 VDC

Input Offset Voltage 200 150 150 1000 600 1500 600 300 500 μV
Offset Drift 0.24 0.7 0.7 2.5 0.7 1.5 0.7 0.14 0.7 µV/°C
Input Bias Current, Maximum 3000 2000 2500 2000 2500 50 30 50 30 pA

Input Offset Current, Maximum 2000 2000 25 30 25 30 pA
Input Bias Current Cancellation Yes Yes - -
Bandwidth (-3dB) at AV = 10 - 396 265 450 180 - kHz

Bandwidth (-3dB) at AV = 100 192 240 240 - - 170 100 kHz
Slew Rate (Typ) 0.55 0.5 0.5 0.55 0.6 0.55 0.5 0.55 0.5 V/µs
Rail-to-Rail Input Yes Yes Yes Yes
Rail-to-Rail Output Yes Yes Yes Yes
Output Current Limit, V+ = 5V ±26 ±29 ±29 ±26 ±29 ±26 ±26 mA
Output in Shutdown Mode - - - HiZ - HiZ
Gain Accuracy ±0.35 ±0.5 ±0.5 ±0.1 ±0.12 ±0.15 0.08 ±0.2 -0.19 %
CMRR (Typ) 114 110 110 106 110 100 100 dB
PSRR (Typ) 106 110 110 90 95 90 100 100 dB
eN at 1kHz 58 60 60 220 210 220 240 80 78 nv/√Hz

eN 0.1Hz to 10Hz 3.5 3.6 3.5 14 10 10 6 µVP-P
Input Protection - Diodes to Yes Yes Yes Yes

Rails
Input Protection - Diodes Yes No No No

across Inputs
Max Input Diode Current 5 5 5 5 mA
Package SO8 SO8 SO8 SO8
Operating Temp. Range -40 to +85 -40 to +85 -40 to +85 -40 to +85 °C
RoHS Compliant Yes Yes Yes Yes
5 AN1298.2
May 27, 2009
+Ven
I I I I
Re Re
Va Vb
Ix1 Ix2
V1 V4
Q1 Q2 V2 V3 Q3 Q4
IN- IN+ FB+ FB-
I1 I2 I3 I4 V5
V6
VOUT
I5 I6 GAIN = A
Ry Ry
FIGURE 9. SIMPLIFIED SCHEMATIC
Instrumentation Amplifier Product Family

V5 = I5 × Ry = 2 × Ry × I + ( V1 – V2 ) × Ry ⁄ Re + ( V4 – V3 ) × Ry ⁄ Re
Theory of Operation
(EQ. 20)
Each of the features specifications of the Intersil
Instrumentation Amplifier Product Family will be discussed in V6 = I6 × Ry = 2 × Ry × I + ( V2 – V1 ) × Ry ⁄ Re + ( V3 – V4 ) × Ry ⁄ Re
more detail in a future section of this Application Note, but (EQ. 21)
first, let’s study the internal operation of this unique V OUT = A × ( V 5 – V 6 ) (EQ. 22)
Instrumentation Amplifier Product Family.
where A is the gain of the output stage
A simplified schematic is shown in Figure 9.
Assume Ry/Re = 1 (i.e., Re and Ry are equal value).
( V 2 + V be2 ) – ( V 1 + V be1 )
I x1 = ----------------------------------------------------------------------, and since V be1 = V be2
Re
V OUT = A × [ 2 × R y × I + ( V 1 – V 2 ) + ( V 4 – V 3 ) –
V2 – V1 [ 2 × R y × I + ( V 2 – V 1 ) + ( V 3 – V 4 ) ]]
I x1 = -------------------- (EQ. 11) (EQ. 23)
Re
V OUT = A × [ ( V 1 – V 2 ) + ( V 4 – V 3 ) + ( V 1 – V 2 ) + ( V 4 – V 3 ) ]
Assuming β high transistors: (EQ. 24)
V OUT = 2 × A × [ ( V 1 – V 2 ) + ( V 4 – V 3 ) ] (EQ. 25)
I 1 = I + I x1 = I + ( V 2 – V 1 ) ⁄ R e (EQ. 12)
V OUT ⁄ ( 2 × A ) = [ ( V 1 – V 2 ) + ( V 4 – V 3 ) ] (EQ. 26)
Since A is very large:
I 2 = I – I x1 = I – ( V 2 – V 1 ) ⁄ R e (EQ. 13) V OUT ⁄ ( 2 × A ) ⇒ 0 (EQ. 27)
Similarly for Q3 and Q4: 0 = ( V1 – V2 ) + ( V4 – V3 ) (EQ. 28)

Let VIN = V2 – V1, and V3 = FB+, V4 = FB-
I 3 = I + I x2 = I + ( V 4 – V 3 ) ⁄ R e (EQ. 14)
0 = -V IN + ( FB- – FB+ ) (EQ. 29)

I 4 = I – I x2 = I – ( V 4 – V 3 ) ⁄ R e (EQ. 15)
V IN + FB- – FB+ (EQ. 30)
Summing currents:
or
IN+ – IN- = FB- – FB+ (EQ. 31)
I5 = I2 + I3 = I – ( V2 – V1 ) ⁄ Re + I + ( V4 – V3 ) ⁄ Re (EQ. 16)
As you can see from Equation 31, negative feedback is
I5 = 2 × I + ( V1 – V2 ) ⁄ Re + ( V4 – V3 ) ⁄ Re (EQ. 17) applied around the amplifier so that the voltage applied to
the feedback terminals (FB+ - FB-) must be equal to the
I6 = I1 + I4 = I + ( V2 – V1 ) ⁄ Re + I – ( V4 – V3 ) ⁄ Re (EQ. 18) voltage applied to the input terminals (IN+ - IN-).
I6 = 2 × I + ( V2 – V1 ) ⁄ Re + ( V3 – V4 ) ⁄ Re (EQ. 19)
6 AN1298.2
May 27, 2009
For the standard data sheet connection: The input terminals (IN+ and IN-) and feedback terminals (FB+
and FB-) are single differential pair devices aided by an Input
V2 Range Enhancement Circuit to increase the headroom of
IN+
operation of the common-mode input voltage. As a result, the
VIN input common-mode voltage range for all these Instrumentation
V1
IN-
VOUT VOUT
Amplifiers is rail-to-rail. The parts are able to handle input
V4 voltages that are at or slightly beyond the supply and ground
FB+
making these in-amps well suited for single 5V or 3.3V low
voltage supply systems. There is no need then to move the
V3 Rf
FB- common-mode input voltage of the these Instrumentation
Amplifiers to achieve symmetrical input voltage.
The use of a bipolar transistor input stage vs. the MOSFET

Rg input stage allows the user to choose low bias current, high
input resistance.
Rail-to-rail operation for both the inputs and outputs is an

important and unique feature. The rail-to-rail inputs allow the
FIGURE 10. TWO AMPLIFIER INSTRUMENTATION AMPLIFIER
input voltages to be slightly below the VS- rail (typically
FB+ = 0V Ground) to slightly above the VS+ rail.
FB- = V OUT × R g ⁄ ( R g + R f ) The conventional technique to achieve a rail-to-rail input
V IN = FB- – FB+ stage is to use two separate input stages, as shown in
V IN = V OUT × R g ⁄ ( R g + R f ) – 0 Figure 12. One input stage (Q1 and Q2) provides common
mode input range to the top rail (VS+), and the other input
V OUT = V IN × ( 1 + R f ⁄ R g ) (EQ. 32)
stage (Q3 and Q4) provides common mode input range to
the bottom rail.
Features of Instrumentation Amplifier
Product Family
A simplified schematic and block diagram is shown in
Figure 11 to illustrate the rail-to-rail operation for both the
input stage and the output stage. The same schematic
applies to the PMOS input devices when the PNP transistors
(Q1 to Q4) are replaced with P-Channel MOSFETs for
ultra-low input bias current.
VS+
INPUT RANGE ENHANCEMENT CIRCUIT
Ven = VS+ + 2V
I I I I
Re Re
Va Vb
Q1 Q2
IN- IN+ FB+ Q3 Q4 FB-
Q5
IBC IBC IBC IBC P-Channel
OUT
Q6
N-Channel
Ry Ry
VS-
IBC => INPUT BIAS CURRENT CANCELLATION
FIGURE 11. SIMPLIFIED SCHEMATIC
7 AN1298.2
May 27, 2009
VS+ 250
VDD = 5.5V
200
INPUT OFFSET VOLTAGE (µV)

-40°C
I 150
100
+25°C
50
Q3 Q4 0
-50
+IN TRANSISTION -IN -100
CIRCUIT +85°C
TO OUTPUT STAGE
-150
-200
-250
Q1 Q2 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
COMMON-MODE INPUT VOLTAGE (V)
I
FIGURE 14. TYPICAL RAIL-TO-RAIL INPUT AMPLIFIER
VS- In addition to shifts in offset voltage as the input common
FIGURE 12. 2 AMPLIFIER INSTRUMENTATION AMPLIFIER mode voltage changes, the input bias current will change
dramatically as the input stages transition from a PNP
Unless the input stages transistors are exactly matched, transistor input stage to a NPN transistor input stage. The
changes in offset voltage and input bias current will result as following graphs compare the input bias current over the
the common mode input range transitions between the two common mode input range for the EL8170 (Figure 15) and a
input stages. typical rail-to-rail input amplifier (Figure 16).
In contrast, the Product Family uses a single input stage for 1500
AVERAGE INPUT BIAS CURRENT (pA)
the IN inputs and a single input stage for the FB inputs. An

Input Range Enhancement Circuit (IREC) provides a bias
voltage that is approximately 2V above the VS+ rail which is 1000
VS = 3.3V
used to bias the I current sources shown in the Block
Diagram. Since there is a single input stage, there is no input VS = 5.0V
500
stage transition point to create shifts in offset voltage and
bias current as the input common mode voltage changes.
0 VS = 2.9V
The effectiveness of the Single Input Stage and IREC circuit
technique is evident as shown in the following Figures for the
offset voltage of a EL8170 (Figure 13) and a typical rail-to- -500
rail input amplifier (Figure 14). -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
250 COMMON-MODE INPUT VOLTAGE (V)

FIGURE 15. EL8170
INPUT OFFSET VOLTAGE (µV)
200 +85°C
INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE

150 3
VDD = 5V
IIB - INPUT BIAS CURRENT - (nA)
2 TA = +25°C
100 +25°C
1
50 0
-45°C
0 -1
-0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
-2
COMMON-MODE INPUT VOLTAGE (V)
-3
FIGURE 13. EL8170
-4
-0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIC - COMMON-MODE INPUT VOLTAGE (V)

FIGURE 16. TYPICAL RAIL-TO-RAIL INPUT AMPLIFIER
8 AN1298.2
May 27, 2009
The PNP input stage transistors are biased with an adequate The operating voltage range of the Instrumentation Amplifier
amount of current for speed, and consequently, their base product family is from 2.4V to 5.5V making it ideally suited
current increases. In order to keep the input bias current low, for operation on 3.3V or 5V power supplies. Also, it will
an Input Bias Current Cancellation Circuit is used to apply operate with a single 4.2 lithium ion battery. Additionally, they
and equal but opposite compensation current to the inputs. are well suited for battery operation since the supply current
This compensation current subtracts from the base currents, is only 66µA maximum.
and the resulting input bias current is reduced to typically
Another unique feature built into the ISL28271 and ISL28272
around 500pA. This is shown in Figure 17 for the IN+ and IN-
is the ability to tri-state the output stage to a high impedance
inputs, where the FB+ and FB- are identical for proper
state when the part is disabled via the ENABLE pin. This
matching between stages. The compensation current,
allows several outputs to be wired together for a multiplexer
(Icomp) is derived from the IBC circuit and is equal to the
function. This feature will be shown in the Applications
base current of Q1 and Q2.
section.
Ven = VS+ + 2V
Because the Instrumentation Amplifier product family
provides an independent pair of feedback terminals to set the
I I
gain and to adjust output level, these Instrumentation
Re Amplifiers achieve high CMRR regardless of the tolerance of
Va Vb the gain setting resistors. The FB+ pin can be used as a REF
Q1 Q2 terminal to center or to adjust the output voltage. Because the
IN- IN+
FB+ pin is a high impedance input, an economical resistor
Icomp Icomp divider can be used to set the voltage at the REF terminal
without degrading or affecting the CMRR performance. Any
voltage applied to the REF terminal will shift the output
Q7 Q8
voltage by VREF times the closed loop gain, which is set by
IBC resistors RF and RG.
INPUT BIAS CURRENT
CANCELLATION Since the feedback terminals are differential inputs, they can
be used in applications such as current sources for a true
VS-
Kelvin sense of the feedback voltage. In addition, a complex
network can be placed in the feedback path for frequency
FIGURE 17. INPUT BIAS CURRENT CANCELLATION CIRCUIT shaping and filter circuits.
Input Bias Current Cancellation Circuit is typically active The basic Instrumentation Amplifier configuration is shown in
from 10mV above the negative rail (VS-) up to the positive Figure 19:
rail (VS+). V2
IN+
Not only does the Input Bias Current Cancellation
compensation circuit keep the input bias current very small, VIN
V1
IN-
it also maintains a very small input bias current variation VOUT VOUT
over a wide operating range as shown in Figure 18 for +25°C V4
FB+
to +85°C.
1500
AVERAGE INPUT BIAS CURRENT (pA)
V3 Rf
VS = 3.3V FB-
1000
500 +85°C Rg
0 +25°C
FIGURE 19. TYPICAL RAIL-TO-RAIL INSTRUMENTATION

-500
AMPLIFIER
-1000
-0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 The gain of this circuit is set by the ratio of Rf and Rg such
COMMON-MODE INPUT VOLTAGE (V) that:
V OUT = V IN × ( 1 + R f ⁄ R g ) (EQ. 33)
FIGURE 18.
9 AN1298.2
May 27, 2009
In this configuration, adjustable gain is possible with external In this case:

resistors for gains from unity up to 10,000. Two external gain V REF = V CC × R 2 ⁄ ( R 1 + R 2 ) (EQ. 37)
setting resistors are used to minimize temperature
coefficient (TC) mismatch as is common with a single gain The feedback terminals can also be used to apply a
setting resistor. reference voltage to shift the output voltage as shown in
Figure 22 with Rg connected to VREF instead of ground.
Notice that resistor value mismatches only effect the gain,
and CMRR is not degraded by resistor mismatches as is the IN+
case with the other basic Instrumentation Amplifier
configurations discussed previously. VIN
IN-
The feedback terminals can be used to apply a reference VOUT VOUT
voltage to shift the input voltage. These are a high VREF
FB+
impedance reference input that is not affected by gain. The
basic circuit is shown in Figure 20: Rf
FB-
IN+
VIN
Rg
IN-
VOUT VOUT
VREF FB+
FIGURE 22.
FB- Rf
V IN = FB- – FB+
FB- = V REF + R g × ( V OUT – V REF ) ⁄ ( R f + R g )
Rg V IN = V REF + R g × ( V OUT – V REF ) ⁄ ( R f + R g ) – V REF
V OUT = V IN × ( 1 + R f ⁄ R g ) + V REF (EQ. 38)
FIGURE 20. BASIC CIRCUIT Since the current in Rg must flow into VREF, the driving point
impedance of VREF will effect the accuracy of this
If we go back to the equations derived previously: configuration. Therefore, VREF should be a low impedance
V IN = FB- – FB+ (EQ. 34) from an op amp, voltage regulator, or voltage reference.
Alternately, if a resistor divider is used to obtain VREF, the
V IN = V OUT × R g ⁄ ( R f + R g ) – V REF (EQ. 35) Thevenin resistance of the divider network must be much
lower than the values of Rf and Rg, or the Thevenin
V OUT = ( V IN + V REF ) × ( 1 + R f ⁄ R g ) (EQ. 36) resistance must be included in the value of Rg and VREF.
However, the CMRR is not affected by the reference voltage
Since the FB+ is a high input impedance, a simple resistor or its source resistance.
divider could be used to set the VREF voltage as shown in
Figure 21. Care and Feeding of Instrumentation
IN+
Amplifiers
As in any low voltage, high accuracy measurement system,
VIN
extreme care must be taken with any of the Instrumentation
IN-
VOUT VOUT Amplifiers with respect to grounding scheme, Kelvin sense
VREF connections, guarding and shielding, and interface to the
VCC FB+
digital world. If the PCB connections are made incorrectly,
the most perfect measurement circuit can still have errors
Rf FB- Rf
resulting from poor grounding considerations and not
understanding the impact of Ohm’s Law. Any analog or
mixed signal PCB must have a well thought-out grounding
scheme with multiple ground planes or traces. There must
Rg Rg
be no heavy DC current or AC current in the analog ground
planes that connect system measurement points.
FIGURE 21.
10 AN1298.2
May 27, 2009
A one point measurement system must be established to be sure there is no digital noise introduced into the Analog
prevent high currents from interfering with the basic Ground, the two grounds are tied together at only one point
measurement. This is shown in Figure 23 for interfacing a at the A/D Converter. Furthermore, a 0Ω resistor can be
thermocouple to an A/D Converter. The “High quality used to connect the two grounds; this ensures a separate
measurement Ground” must only connect to the critical Net for each ground so the PCB layout software or layout
ground points in the analog front-end; this ground must person does not arbitrarily connect the two grounds. The use
make a single point connection to the A/D converter at its of a 0Ω resistor is cheap insurance against a noisy and
Analog Ground pin (AGND). There must be no other inaccurate analog system! This Thermocouple Circuit will be
connections such as digital grounds or power supply returns discussed in more detail in the Applications section.
to the “High quality measurement Ground” except a single
connection at the A/D Converter pins (AGND and DGND). To
+5V
7
+5V VS+
OPEN TC BIAS
R1 R4
R R
3 VS- 4 A/D CONVERTER
IN+
C1
INPUT FILTER C s
(Vtc) 2
IN- V VOUT = (Vtc + Vcjc) * (1 + Rf/Rg)
J-TYPE OUT 6
R2 VIN
THERMOCOUPLE R3 (Vcjc) 8
R FB+
IBIAS R
(51.7µV/C)
+5V RETURN 5 Rf
FB-
191k, 1%
ISL6007DIB825
GAIN = 1 + Rf/Rg VREF
LM35DM VOUT
GAIN = 1 + 191k/1k Rg (2.5V)
(10m/C) R5 GAIN = 192 GND
1k, 1%
191k,
1%
R6
1k, 1% HIGH QUALITY
AGND
MEASUREMENT GROUND
s DGND
CONNECT AGND AND DGND
d
AT ONE POINT AT ADC
FIGURE 23.
Rs
1.2V PROCESSOR LOAD
DC/DC CONVERTER
OUTPUT 10A, MAX
0.005Ω
10k 10k +5V

0.1µF
7 EL8171, EL8173, ISL28273, ISL28271
VS+
3 IN+
2 IN-
VOUT 6 VOUT = 0V to + 2.5V

8 FB+
5 FB- V - Rf
S 48.7k, 0.1%
4
GAIN = 50
Rg
1k, 0.1%
FIGURE 24.
11 AN1298.2
May 27, 2009
Instrumentation Amplifiers can be used in high accuracy mode as explained in the “Instrumentation Amplifier Product
current sense applications as shown in the circuit in Figure 24. Family Theory of Operation” on page 6 there is no possibility
of internal clipping.
Notice the use of a Kelvin connection shown on the current
sense resistor Rs as indicated by the slanted connections to If we review the classic three amplifier instrumentation
the resistor. To avoid errors caused by IR drops, the amplifier configuration shown in Figure 25, the effect of
connections must be made directly at the leads of the internal clipping can be clearly shown.
0.005Ω current sense resistor. Just 1mΩ of contact VCC
resistance or PCB trace resistance will cause a 20% error in IN- VO1
+
the current reading. A1
-
10k 10k
Guarding and driven guards is a PCB layout technique to
reduce errors caused by PCB leakage currents and improve
high frequency CMRR. This can be done by surrounding VIN R1
50k A3
-
high impedance input leads with traces that are driven by a Rg VOUT
R2 +
low source impedance voltage that is equal to the common 100 50k
mode voltage.
At any point in a circuit where dissimilar metals come in - 10k 10k

contact a small thermocouple voltage is developed. IN+ A2 VREF
+
VO2
Fortunately, the copper lead frame of a surface mount device
is the same copper material as PCB etch, and the Vcm
thermocouple effect is minimized. However, there are many
other places where thermocouples can be generated; for
example, across a connector finger, across relay contacts, or
even across a resistor! Yes, a poorly constructed resistor
FIGURE 25.
can show many µV/°C of thermocouple voltage. It has been
found that external components (resistors, contacts, sockets, Simple circuit analysis shows that the two internal voltage
etc.) can create thermocouple voltages that exceed VO1 and VO2 are:
10µV/°C.
V O1 = V IN × ( 1 + R 1 ⁄ R g ) + V cm (EQ. 39)
It must be recognized that thermocouple voltages are
developed by the difference in temperature between the two
V O2 = V cm – V IN × R 1 ⁄ R g (EQ. 40)
ends of dissimilar metal junctions, and not the absolute
ambient temperature. If both ends of the metal junctions are Two clipping conditions will occur if the effects of VIN and
isothermal (i.e., at the same temperature) there is no Vcm are not considered:
thermocouple voltage developed. Therefore, the first rule to
avoid thermocouple effects is to eliminate hot spots on a 1. VO1 cannot exceed the maximum output voltage for A1
PCB (e.g., linear voltage regulators). If hot spots cannot be which is the supply voltage (VCC) and the saturation
voltage of A1’s output stage.
avoided, then the two ends of metal junctions must be
oriented so they are on isothermal lines on the PCB. V IN × ( 1 + R 1 ⁄ R g ) + V cm < V CC + V sat (EQ. 41)
The second rule to minimize thermocouple effects is to 2. VO2 cannot go below Ground + the saturation voltage of
balance the number of junctions in a loop so that the error A2’s output stage.
voltages are cancelled or become a common mode voltage V cm > V IN × R 1 ⁄ R g + V sat (EQ. 42)
that is reduced by the CMRR of the op amps in the signal
In reality, this places a such a severe restriction on single
chain. If the number of junctions are not balanced, then it
supply operation that it makes this circuit almost impossible
may be necessary to create a junction by adding a series
to use as a general purpose single supply instrumentation
resistor that has no effect on circuit operation but balances
amplifier. For example, A2 output stage saturation voltage
the number of junctions.
prevents even 0V of common mode voltage!
Unknown to most design engineers is the danger of internal
To overcome this issue, modern monolithic IC
clipping when operating an instrumentation amplifier on a
instrumentation amplifiers add PNP level shift transistors (Q1
single supply. Unfortunately, the internal nodes are invisible
and Q2) to raise the input voltages off Ground as shown in
to the user and impossible to measure; manufacturer’s data
the circuit in Figure 26.
sheets often ignore the issue, or they have obscure “typical
characteristics” graphs or misleading paragraphs that
attempt to explain the phenomena. Since the
Instrumentation Amplifiers operate in a current summing
12 AN1298.2
May 27, 2009
there is no possibility of internal clipping. As long as the total

of the common mode voltage plus the input signal is
between 0V and the VS+ supply voltage there will be no
A1 internal clipping. The output voltage will swing within its rail-
+
VO1
Q1
to-rail output specification of 10mV to either rail for a 100kΩ
-
IN- load. There is no restriction on differential input voltage or
common mode voltage provided the output voltage does not
exceed its full scale range due to input voltage level, gain,
R1
VCC Rg 50k CMRR, and VREF level.
VIN
100 R2
50k All input and feedback terminals of the Instrumentation
Amplifiers have internal ESD protection diodes to both
positive (VS+) and negative supply (VS-) rails, limiting the
Q2 - input voltage to within one diode drop beyond the supply
IN+ + VO2 rails. The EL8170, EL8172, ISL28270 and ISL28470 have
A2
additional back-to-back diodes across the input terminals
and also across the feedback terminals. If overdriving the
Vcm
inputs is necessary, the external input current must never
exceed 5mA. On the other hand, the EL8171, EL8172,
ISL28271, ISL28272 and ISL28273 have no diode clamps to
FIGURE 26. limit the differential voltage on the input terminals allowing
higher differential input voltages at lower gain applications. It
The two internal voltage VO1 and VO2 are now: is recommended however, that the input terminals of these
V O1 = V IN × ( 1 + R 1 ⁄ R g ) + V cm + 0.7V (EQ. 43) devices are not overdriven beyond 1V to avoid offset drift.
An external series resistor may be used as an external

V O2 = V cm – V IN × R 1 ⁄ ( R g + 0.7V ) (EQ. 44) protection to limit excessive external voltage and current
from damaging the inputs. A 20k resistor can be used to
Now, the danger of internal clipping situation has been protect the inputs against 100V transients on the inputs. If
improved for A2 but made worse for A1 since an additional the overvoltage condition is continuous, the 20k resistor
0.7V has been added to VO1. For example, the maximum must be rated at 1W for adequate power dissipation.
common mode voltage is only 1.5V for this instrumentation
amplifier operating on a supply voltage of 5V ±5% with a
gain of 250 and a 10mV input signal! If you doubt the validity
of these statements, check vendor data sheets for analog
devices that exhibit these characteristics.
Since the Instrumentation Amplifiers operate in a current

summing mode as explained in the “Instrumentation
Amplifier Product Family Theory of Operation” on page 6,
Ven = VS+ + 2V
I I I I VS+
VS+ VS+ VS+
Re Re
IN- IN+ FB-
VS- VS- VS- VS-
EL8170 ONLY EL8170 ONLY
INPUT BIAS CURRENT INPUT BIAS CURRENT

CANCELLATION CANCELLATION
5mA MAXIMUM INTO ANY PROTECTION DIODE!
VS-
FIGURE 27. INPUT PROTECTION DIODES
13 AN1298.2
May 27, 2009
20k 3
TRANSFORMER
IN+ COUPLED SOURCE 3
IN+
VIN 20k VIN
2
IN- 2
6 IN-
VOUT VOUT 6
VOUT
8 VOUT
FB+ 8
FB+
5 Rf
FB- 5 Rf
FB-
Rg
Rg
FIGURE 28.
FIGURE 30.
Input bias current from the IN+ and IN- inputs of the
Instrumentation Amplifiers must find a DC path to their home
AC COUPLED SOURCE
(i.e., Ground). While it seems obvious to the casual user, this 3
IN+
is an often ignored principle when designing with an
VIN
Instrumentation Amplifier, and results in many telephone 2
IN-
calls to the Applications Engineer. Many voltage sources do
47k 47k VOUT 6
not provide a DC path to Ground such as thermocouples, VOUT
8
microphones, transformer coupled circuits, and AC coupled FB+
circuits. Without a DC return path, the input bias current will

5 Rf
accumulate on any stray capacitance on the inputs until they FB-
are clamped to the rails by the protection diodes. The output
of the Instrumentation Amplifier will slowly increase or
decrease until it saturates into the VS+ or VS- rail.
Rg
A DC return path as shown in the following circuits must be
supplied to provide a return path for the input bias current.
3 FIGURE 31.
IN+
An error budget can be calculated by summing the factors
VIN 2
IN- which contribute to the output voltage error. Most of the error
VOUT 6 sources are referred to the input and multiplied by the Gain
VOUT
10k 8 to get an output voltage error term as shown in the following.
FB+
Offset voltage: Normally instrumentation amplifiers have

5 Rf
FB- two offset voltage specifications - an input offset voltage
(VOSI) and output offset voltage (VOSO) specification such
that the input offset voltage is multiplied by the gain, and the
output offset voltage exhibits unity gain to the output voltage.
Rg
Therefore, the output voltage error from offset voltage is:
V OUT = Gain × V OSI + V OSO (EQ. 45)
Due to the unique architecture of the Instrumentation

FIGURE 29.
Amplifiers, there is only one offset voltage specification
required. The input offset voltage (VOSI) is the amount of
voltage applied the inputs terminals such that the voltage
across the FB is zero, or input offset voltage will be the
difference between the IN terminals and the FB terminals:
( IN+ – IN+ ) = ( FB+ – FB- ) + V OS (EQ. 46)
14 AN1298.2
May 27, 2009
0.1Hz to 10Hz Noise: The error introduced by voltage can

V OUT ( V OSI ) = Gain × V OSI (EQ. 47) be modeled the same as an input offset voltage, Vn. If noise
is required in a wider bandwidth than 0.1Hz to 10Hz, the
Offset bias current: Similar to an Op Amp circuit, the input
noise can be calculated by evaluating the Input Noise
resistance creates an error source that can be modeled the
Voltage Density (en) over the desired bandwidth. Multiplying
same as offset voltage such that:
the rms noise by six will give a good approximation for the
V IB = R S × I OS (EQ. 48) peak-to-peak noise.
V OUT ( I OS ) = Gain × R S × I OS V OUT ( V n ) = Gain × V n (EQ. 53)
(EQ. 49)
Common Mode Rejection Ratio: The error introduced by Gain Error: Gain error results from two factors. The first is
common mode voltage can be modeled the same as an the basic gain deviation from the ideal gain equation, Gain =
input offset voltage, VCMR. (1 + Rf/Rg); for the EL8173 this error (E.g.) is typically
CMRR = 20 × log ( V CMR ⁄ V CMV ) ±0.2%. Second is the tolerance (ERf and ERg) of the Rf and
10 (EQ. 50)
Rg resistors which set the Gain.
( CMRR ⁄ 20 ) V OUT = V IN × ( 1 + R f ⁄ R g ) × [ 1 – ( ER f + ER g + Eg ) ] (EQ. 54)
V CMR = V CMV × 10 (EQ. 51)
V OUT ( CMRR ) = Gain × V CMR (EQ. 52)

Temperature Drift: The effect of operating over the
expected temperature range must be included in all these
calculations based on the data sheet specifications.
Rs
1.2V PROCESSOR LOAD
DC/DC CONVERTER
OUTPUT 10A, MAX
0.005Ω
10k 10k +5V

0.1µF
7 EL8171, EL8173, ISL28273, ISL28271
VS+
3 IN+
2 IN-
VOUT 6 VOUT = 0V to + 2.5V

8 FB+
5 FB- V - Rf
S 48.7k, 0.1%
4
GAIN = 50
Rg
1k, 0.1%
FIGURE 32.
TABLE 4. ERROR BUDGET CALCULATION

ERROR SOURCE SPECIFIED VALUE REFEREED TO OUTPUT % FS ERROR
Offset voltage 400µV 20mV 0.8%
Input Offset Current 0.5nA 0.25mV 0.01%

CMRR 104dB 0.24mV 0.01%
0.1Hz to 10Hz Noise 10µV 0.5mV 0.02%
Gain Error 0.2% 0.2%
Rf, Rg Tolerance 0.1% 0.2%
Total Error 1.24%
15 AN1298.2
May 27, 2009
Example of an Error Budget Calculation within a few millivolts of the supply rails. At a 100kΩ load, the
Consider the circuit shown in Figure 32 for a CPU core PMOS sources current and pulls the output up to 4mV below
voltage current monitor circuit operating at +25°C. the positive supply, while the NMOS sinks current and pulls the
output down to 4mV above the negative supply, or ground in
The importance of an Error Budget as shown in Table 4 is the case of a single supply operation. As the load current is
that it is shows the overall accuracy which can be expected increased, the maximum output voltage will decrease as a
and which factors are determining the overall accuracy of result of the voltage drop caused by the sourced load current
the circuit. In this circuit, the Offset voltage is the factor times the top MOSFET ON resistance. Likewise, the minimum
which is driving the Total Error; if tighter accuracy is required output voltage will increase as a result of the voltage drop
for the application, the offset term could be removed by caused by the sink load current times FET ON resistance.
hardware calibration with a digital potentiometer or software
calibration. The Total Error could be reduced to 0.5% just by The current sinking and sourcing capability is internally
decreasing the offset voltage term by a factor of 10. limited to about 26mA with a 5V supply.
Because of the independent pair of feedback terminals Care must be taken with excessive load capacitance, CLOAD.
provided by Intersil’s Instrumentation Amplifiers, the CMRR As shown in the following graphs, excessive load capacitance
is not degraded by any resistor mismatches. Hence, unlike a will cause excessive peaking in the frequency response. The
three op amp and especially a two op amp instrumentation result will be ringing in the output voltage under transient
amplifier, the Intersil solution will reduce the cost of external conditions, and potentially oscillations resulting from unstable
components by allowing the use of 1% or more tolerance operation. If the Instrumentation Amplifiers are used in
resistors without sacrificing CMRR performance. The CMRR applications where there may be large load capacitance
will be greater than 100dB regardless of the tolerance of the (cable driving, filters, FET gates, etc.), a suitable buffer should
resistors used. be used on the output of the Instrumentation Amplifier.
The effects of loading the rail-to-rail output stage must also be Noise calculations for the Instrumentation Amplifiers are very
considered too since the output stage exhibits an “ON” state similar to those for an op amp circuit. The noise model is shown
resistance. A pair of complementary MOSFET devices with in the following where the Input Noise Voltage and Input Noise
approximately 50Ω ON resistance drives the output VOUT to Current noise sources are lumped into the IN+ terminal.
25 30
VS = ±2.5V 25
20 CL =
CL = 47pF
MAGNITUDE (dB)
MAGNITUDE (dB)
VS =
20
15
CL = 27pF
15
10 A = 10 VS =
V A = 10
RL = 1kΩ 10 VV = 5V
S
C = 10pF RL = 10kΩ
5 RL/R = 9.08Ω
F G 5 RF/RG = 9.08Ω
RF = 178kΩ RF = 178kΩ
RG = 19.6kΩ RG = 19.6kΩ
0 0
100 1k 10k 100k 1M 100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (Hz)
FIGURE 33. EL8171 FREQUENCY RESPONSE vs SUPPLY FIGURE 34. EL8171, EL8172 FREQUENCY RESPONSE vs
VOLTAGE CLOAD
30 50
25 CL = 45
CL = 47pF CL =
MAGNITUDE (dB)
MAGNITUDE (dB)
CL =
20
40
CL = 27pF
15 CL = 820pF
A = 10 35 AV = 100
10 VV = 5V VS = 5V
CL = 390pF
S
RL = 10kΩ RL = 10kΩ
R 30 RF/RG = 99.02Ω
5 F/RG = 9.08Ω
RF = 178kΩ RF = 221kΩ
RG = 19.6kΩ RG = 2.23kΩ
0 25
100 1k 10k 100k 1M 100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (Hz)
FIGURE 35. EL8171 FREQUENCY RESPONSE vs CLOAD FIGURE 36. EL8172 FREQUENCY RESPONSE vs CLOAD
16 AN1298.2
May 27, 2009
en(V) en(I1) en(I2) en(Rs) en(Rfg)
V V V V V IN+
IN-
Rs
VOUT VOUT
FB+
FB- Rf
NOISE MODEL Rg
FIGURE 37.
Where: en(V) is the Input Noise Voltage over the desired The 1.57 term in the equations is the noise equivalent
bandwidth en(I1) is the voltage noise generated by the Input bandwidth representing a 1st order roll-off equivalent as if
Noise Current over the desired bandwidth and the source there is a brick wall filter at 1.57*Fh. If we have a brick wall
resistance (Rs): filter that cuts off right (infinitely steep) at Fh then this term is 1.
e n ( I1 ) = I IN × R s (EQ. 55) 1st order = 1.57
2nd order = 1.11
en(I2) is the voltage noise generated by the Input Noise
3rd order = 1.05
Current over the desired bandwidth and the feedback and
4th order = 1.025
gain resistors (Rf || Rg):
e n ( I2 ) = I IN × R f || R g To determine the total rms output noise from all the sources,
(EQ. 56)
the rms summation is taken multiplied by the gain.
en(Rs) is the thermal noise over the desired bandwidth of Rs. 2 2 2 2 2 2
e n = ( 1 + R f ⁄ R g ) × ( e n ( V ) + e n ( I1 ) + e n ( I2 ) + e n ( I2 ) + e n ( Rs ) + e n ( Rfg ) )
en(Rfg) is the thermal noise over the desired bandwidth of
(EQ. 59)
Rf || Rg
Rs is the source resistance The peak-to-peak output noise is typically 6 times the rms
Rf and Rg are the gain setting resistors value (rule of thumb).
To calculate rms noise, N over a desired bandwidth:
en ( P – P ) = 6 × en (EQ. 60)
N = N O ( F C × ln ( F h ⁄ F l ) + 1.57 × F h – F l ) (EQ. 57)
eno(pp) = 6 * eno
where: NO is the specified noise density in nV/√Hz
Fc is the corner frequency
Fh is the upper frequency of interest
Fl is the lower frequency of interest
To calculate resistor thermal noise over a desired bandwidth:

Nr = 4kTR × ( 1.57 × F h – F l ) (EQ. 58)
where: R is the resistor value

k is Boltzman’s Constant, 1.39*10-23
T is temperature in Kelvins
Fh is the upper frequency of interest
Fl is the lower frequency of interest
17 AN1298.2
May 27, 2009
+5V
Rb1 Rb3 +5V

1k 1k 7
R1
7.5k 3 VS+
IN+
R2
7.5k 2
IN-
VOUT 6
VOUT + 0V to 2.5V
8
Rb2 Rb4 FB+
1k 1k
5 Rf
FB- VS- 100k
4
Rg
100k
FIGURE 38.
Example of Noise Calculation:

Consider the circuit shown in Figure 38 for a bridge amplifier operating in a 0.5Hz to 100Hz bandwidth with a full scale output
voltage of 2.V.
eN = 50nv/√Hz From the EL8170 data sheet specifications

Fc = 100Hz From the EL8170 data sheet performance curves
iN = 0.1pA/Hz From the EL8170 data sheet specifications
Fc = 50Hz From the EL8170 data sheet performance curves

Rs = 8kΩ Balanced bridge Thevenin resistance + 7.5kΩ resistor
Rfg = 990Ω Rf || Rg = 90.9k || 1k
e n ( V ) = 50nV ⁄ Hz × 100Hz × L n ( 100Hz ⁄ 0.5Hz ) + 1.57 × 100Hz – 0.5Hz

= 0.81 μV, rms (EQ. 61)
e n ( I1 ) = 0.1pA ⁄ Hz × 50Hz × L n ( 50Hz ⁄ 0.5Hz ) + 1.57 × 100Hz – 0.5Hz × 8k

= 0.12 μV, rms (EQ. 62)
e n ( I2 ) = 0.1pAnV ⁄ Hz × 50Hz × L n ( 50Hz ⁄ 0.5Hz ) + 1.57 × 100Hz – 0.5Hz × 990

= 0.0014 μV, rms (EQ. 63)
e n ( Rs ) = ( 4 × k × 300°K × 8k × ( 100Hz – 0.5Hz ) )

= 0.12 μV, rms (EQ. 64)
e n ( Rfg ) = ( 4 × k × 300°K × 990 × ( 100Hz – 0.5Hz ) )

= 0.04 μV, rms (EQ. 65)
18 AN1298.2
May 27, 2009
2 2 2 2 2 +5V
e n = ( 1 + R f ⁄ R g ) × ( e n ( V ) + e n ( I1 ) + e n ( I2 ) + e n ( Rs ) + e n ( Rfg ) )
7
2 2 2 2 2 3 VS+
= ( 1 + 90.9k ⁄ 1k ) × (0.81μV +0.012μV +0.0014μV +0.12μV +0.04μV ) IN+
= 100 × 0.82μV
(EQ. 66) VIN
2
= 82 μVrms IN-
To determine the total rms output noise from all the sources, VOUT 6 VOUT
8
the rms summation is taken multiplied by the gain. FB+ Rf
12k
Note that the total output noise is dominated by basic Input Rf
5
Noise Voltage and higher source resistance could be used FB- VS- 100k
without degrading the overall error resulting from noise. 4 Cx
0.1µF
e n ( P – P ) = 6 × 82μV (EQ. 67)
= 492 μV P – P GAIN = 100 BELOW 14Hz
GAIN = 100 BELOW 140Hz Rg
This represents an error of 0.02% for a 2.5V full scale output. 1k
A very unique feature of the Intersil Instrumentation

Amplifiers is the ability to put a filter circuit in the feedback GAIN = 100
network to shape the frequency response of the amplifier.

This ability is not possible with other monolithic
Instrumentation Amplifiers because they use a single
GAIN = 10
resistor at the input stage to set the gain. Adding filter circuits
in the feedback network of an Instrumentation Amplifier
implemented with discrete components (op amps and
resistors) is very difficult because capacitor mismatch will 14Hz 140Hz
Flp Fhp
result in very poor high frequency CMRR.
FIGURE 39.
A complex impedance network can be added as shown in
the following for a low pass function. The low frequency gain For this circuit, it can be shown that low frequency pole and
is set by Rf and Rg using the standard equation: higher frequency zero are:
Gain = 1 + Rf ⁄ R g (EQ. 68) Flp = 1 ⁄ ( 2 × π × C x × ( R f + R x ) ) Pole Frequency
= 1 ⁄ ( 2 × π × 0.1μF × ( 100k + 12k ) )
The Instrumentation Amplifiers are not unity gain stable; i.e.,
= 14Hz (EQ. 69)
they require gains greater than 10 or 100 depending on the
device. Therefore, they must never be allowed at unity gain
even at high frequencies! If Rx was not included in this Flp = 1 ⁄ ( 2 × π × C x × R x ) Zero Frequency
circuit, Cx would dominate at high frequencies, and the
= 1 ⁄ ( 2 × π × 0.1μF × 12k )
Instrumentation Amplifier would be unstable and oscillate.
= 140Hz
Lab tests have shown that Cx >33pF is enough to cause an (EQ. 70)
oscillation. Adding Rx in series with Cx creates a zero in the
transfer function so that at higher frequencies Rx parallels Rf
so that the new Rf = 10.7k, and the gain at high frequency is
11.7 which is a stable condition. Lab tests have shown that
any value can be used for Cx with no oscillations.
19 AN1298.2
May 27, 2009
SW0 CLOSED MEASURE VIN+ - VIN-

A2 6 A2 V+ 10 +5V U4
7 A1 4 SW1 CLOSED MEASURE CMRR TO ZERO
A1 INH
SW2 CLOSED MEASURE VOS TO ZERO EL8173
8 NO0
VIN+ SW3 CLOSED MEASURE 25mV CAL REFERENCE
3 NO1 VS+ 7 +5V
1 NO2
2 NO3 Com 9 3 IN+ VS- 4
GND U1
Vcm 5 ISL43640 2 IN- s
+5V VOUT 6 VOUT
6 A2 V+ 10 8 8 FB+
+5V
7 A1 INH 4 VCC
WRITE 1 WP-L RH 7 R8
8 NO0 5 FB-
VIN- PROTECT 150k, 1%
3 NO1 2 SCL RW 5
NO2 RP1
1 I2C BUS 50k
3 SDA +5V
2 NO3 Com 9 RL 6
8
GND U2 GND VCC
5 ISL43640 U5 4 R5 R9 7 RH WP-L 1 WRITE
R2, 1M 48.7k 309 PROTECT
ISL95810 s 5 RW SCL 2
RP2
6 2 +5V 50k I2C Bus
(VREF) VOUT VIN SDA 3
R1, 10k R7 R6 6 RL
REQ = 9900Ω GND 66.5k 1k GND
R3
R4, 2k 1 4 -5V R10 4 U6
100k
C2 1.37k, 1% s ISL95810
C1 U3 OFFSET CORRECTION (±25mV)
10µF 0.01µF s
ISL6007DIB825
PROGRAMMABLE GAIN, 90 TO 110
CALIBRATION REFERENCE (25mV)
FIGURE 40. ANALOG FRONT-END CIRCUIT
Application Circuits Since the offset calibration voltage is operating at very close
to zero voltages (±25mV), the driving point impedance is
Instrumentation Amplifier With Auto Zero and kept very low (1k, R6) to avoid variations caused by the
Auto Gain Calibration increasing bias current. The configuration of U5, R5, and R7
The circuit shown in Figure 40 shows an analog front-end is carefully selected so that the D-Pot never is operated at a
circuit with an Auto Zero and Auto Gain Calibration to eliminate negative voltage.
the offset voltage and gain errors of the EL8173. It is intended
The ±25mV offset calibration source is obtained by
to be part of an overall data acquisition system with an A/D
programming U5 with the appropriate digital code in
Converter and microprocessor to perform an auto zero/gain
Equation 71.
software routine. Figure 40 does not include the A/D Converter
5∗ ⎛ --------------------------⎞ – -------
1 1
or processor hardware/software. ⎝R + R ⎠ R
1 pot 2
TABLE 5. Vcal = -----------------------------------------------------------
-
⎛ -------------------------
1
-⎞ + ------- + -------
1 1
⎝R + R ⎠ R
SWITCH 1 pot 2 R3 (EQ. 71)
A2 A1 CLOSED MODE
The +25mV reference voltage is obtained with the ISL6007’s
0 0 SWO Measure the input voltage VIN+ - VIN-
2.5V output voltage divided down by a factor of 100 with R1,
0 1 SW1 Calibrate with external common mode R2, and R3. The accuracy of the gain calibration is
voltage applied
determined by the accuracy of the ISL6007 and the
1 0 SW2 Calibrate offset voltage to zero tolerance of resistors R1 and R2. Therefore, it is
1 1 SW3 Calibrate gain with 25mV reference recommended to use very low tolerance resistors for R1 and
voltage applied R2, or use a precision resistor divider network.
The gain of the EL8173 is programmed by D-Pot, U6

During the calibration mode, analog switches S1 and S2
according to Equation 72:
connect the inputs of the EL8173 to calibration source voltages
R 8 + R 9 + R 10
of zero volts, an external common mode voltage, or a 25mV Gain = ---------------------------------------------
-
Code
reference voltage. Digital potentiometer (D-Pot) U5 applies a R 10 + --------------- × R g
255
programmable offset voltage of ±25mV to the FB+ pin of the
EL8173 to adjust the EL8173 output to zero voltages. Digital 150000 + 309 + 1370
Gain = --------------------------------------------------------
potentiometer (D-Pot) U6 programs the gain of the EL8173 Code
1370 + --------------- × 309
255
from 90 to 110 for a 2.5V output with the +25mV reference
151.7k
voltage applied to the inputs. Gain = -------------------------------------------------- (EQ. 72)
1370 + 1.2 × Code
20 AN1298.2
May 27, 2009
Other nominal gains and gain adjustment range can be Another complication of SPPT application is the large
made by changing the values of R8, R9, and R10. temperature dependence of both total bridge resistance and
peizosensitivity (the ratio of bridge output to excitation
Pressure Sensor Interface Circuit voltage times pressure). Bridge resistance increases with
temperature while peizosensitivity decreases. Some SPPT
Programmable Pressure Transducer Circuit
designs (e.g. the Nova Sensor NPC-410 series) carefully
The silicon piezoresistive-bridge pressure transducer (SPPT) equalize these opposite-sign tempcos. The payoff comes
is a dominant technology in automotive, industrial, medical, when such SPPTs are excited with constant current because
and environmental pressure sensor applications. All SPPTs the increase with temperature of bridge resistance (and
share a similar architecture in which a thin (5µm to 200µm) therefore of bridge excitation voltage) then cancels the
micro machined silicon diaphragm incorporates an implanted simultaneous decrease of peizosensitivity.
piezoresistive Wheatstone-bridge strain-gauge. Applied
pressure bends the diaphragm, imbalances the strain gauge, A 10mV/psi pressure-proportional strain gauge signal is
and thereby produces a differential output signal proportional outputted differentially on pins 2 and 4 of the sensor; this signal
to the product of pressure times bridge excitation voltage. is superimposed on a common mode voltage of 1.2V from the
bridge excitation voltage. The low level differential output
SPPTs must be supported by appropriate signal conditioning voltage is amplified by the EL8173 with a nominal gain set at
and calibration circuits. Finite elasticity limits the SPPT 50. The high common mode rejection capability of the EL8173
diaphragm to relatively small deflections which generate only eliminates the common mode output voltage of the bridge. The
±1% modulation of the bridge resistance elements and low bridge is biased from a constant current source (Q2) and two
signal output levels, creating the need for high gain, low-noise, digitally controlled potentiometers provide for zero (DPOT1)
temperature-stable DC amplification. The signal conditioning and full scale (gain) adjustments (DPOT2).
circuit must also include stable, high resolution, preferably
non-interactive, zero and span trims. The automation of the In the detailed circuit shown in Figure 41, the U2b and U3
calibration of the sensor circuit is an enormous benefit in the circuit provides for the precision offset adjustment, via
production environment. DPOT1, of any transducer initial null offset error. To
+5V
R2 R3
402 402
CURRENT MIRROR FOR LOW HEADROOM
FROM +5V SUPPLY
Q2
DMMT3906
BRIDGE EXCITATION, 600µA CURRENT SOURCE
U2a +5V Zin = Zout = 4k, TYP

U1 Q1
1/2 ISL28276 (2.5k TO 6k)
2N3904 3
+5V IN OUT IN+ U4
GND EL8173
ISL60002-11 4k 4k 7
C1 VS+ +5V
(1.200V) 1000pF
OUT+ 2 3 4
IN+ VS-
R1 s
OUT- 4 2 VOUT
2k IN-
Vbridge, MAX = 600µA*6k = 3.6V 0.5V/PSI
4k 4k 6
VOUT
U2b 8
FB+
1/2 ISL28276
R8
+5V DPOT VOLTAGE ALWAYS POSITIVE IN- IN- 5 115k
FB-
BUFFERED R3 1 8
+Vbridge 39.2k GAIN = 40 TO 60
PS1
NPC-410 R9
DPOT1 0PSI TO 5PSI
1/2 X95820 DPOT2 1k
50k, 256 TAPS (±25mV AT MAX Vbridge = 3.6V) 50k, 256 TAPS
(±10mV AT MAX Vbridge = 1.5V) 1/2 X95820
R5
20k U3 GAIN CALIBRATION CIRCUIT R10
EL8176 1.96k
R6 R7
20k R4 1k OFFSET CALIBRATION CIRCUIT
54.9k
-Vbridge
-5V
FIGURE 41.
21 AN1298.2
May 27, 2009
accomplish this, the bridge excitation voltage is Thermocouples present several unique challenges when
programmably attenuated by DPOT1 and applied to the FB+ interfacing them to a real world measurement system.
pin of the EL8173. The range for the zero adjustment voltage
1. Thermocouples generate a very low output voltage that
is from +25mV to -25mV. The resolution is 200µV and is
must be amplified with a high gain amplifier. Each
proportional to the bridge excitation voltage, thus improving thermocouple type requires a different gain when
the temperature stability of the zero adjustment. interfacing to an A/D Converter with a fixed full scale
The 10mV/psi bridge output signal is amplified by 50x to a voltage, VFS/VoMAX.
convenient 0.5V/psi output level with the EL8173 its 2. Thermocouples do not generate an absolute voltage that
feedback and calibration network consisting of R8, R9, R10, is proportional to temperature. Instead, they generate a
and DPOT2. The gain of U3 can be varied from 40 to 60 with voltage that is a relative voltage that is the proportional to
the temperature difference between the “hot” end and the
a resolution of 0.10.
“cold” end. All thermocouple tables showing output
Bridge bias is provided by the constant current circuit (U1, U2a, voltage vs temperature are for the “cold” end placed in an
and Q1) which sets a current in Q1 of 1.2 V/2k = 600µA. A ice bath at 0°C. Since it is very impractical to place an ice
current mirror (Q2, R2, R3) reflects the output current so as to bath on a PCB, electronic cold junction compensation is
source the 600µA into the top of a grounded bridge (PS1). used. Each thermocouple type requires a cold junction
compensation rate, dVO/dT.
The net result of the combination of transducer and the 3. The output voltage of a thermocouple is non-linear, and is
EL8173 circuitry is a signal conditioned precision pressure dependant on the type of thermocouple. Linearization is
sensor that is compatible (thanks to DPOT1 and DPOT2) most often done with diode break-point techniques or via
with full automation of the calibration process, is very low in microprocessor software, and is not covered in this
total power draw (<2mA), most of which goes to transducer Application Note.
excitation and current mirror circuit. The circuit shown in Figure 42 uses the unique features of
the Intersil EL8173 Instrumentation Amplifier to simplify the
Thermocouple Input with A/D Converter Thermocouple interface to a high resolution A/D Converter
Output (U5). A programmable gain digital pot (U3) and
Thermocouples are the industry standard temperature programmable temperature sensor (U2) allows digital
sensor for measuring a wide range of temperatures from selection of the four most popular thermocouple types: E, J,
-250°C to + 2300°C. The four most popular thermocouple K, and T.
types are shown in Table 6; however, any time two dissimilar
metals are placed in contact, a thermocouple is created via
the Seebeck Effect.
TABLE 6. POPULAR THERMOCOUPLE TYPES
TEMPERATURE RANGE VO at TMIN VO at TMAX dVO/dT 0°C to +50°C
TYPE MINIMUM MAXIMUM (mV) (mV) (µV/°C)

E -200°C +900°C -8.83 68.79 61.00
-328°F +1652°F
J 0°C +750°C 0.00 42.30 51.70

+32°F +1382°F
K -200°C +1250°C -5.89 50.64 40.50

-328°F +2282°F
T -250°C +350°C -5.60 17.82 40.70
-328°F +662°F
22 AN1298.2
May 27, 2009
U1 U5 Y? 10Mhz
EL8173 HI7190
8Hz INPUT FILTER 17 16
E, J, K, T TYPE VS+ 7 +5V
R1 OSC1 OSC2
THERMOCOUPLE
1k 3 IN+ VS- 4 13 AVDD DVDD 15
+5V +5V
C1
10µF (VTC) s -5V 7 AVSS SCLK 1 CLOCK
2 IN-
R3 6 (VOUT) 12 VINHI SDIO 3
R2 (VCJC) VOUT DATA I/O
1k 1M 8 FB+
R6 11 VINLO SDO 2 DATA OUT
+5V 5 FB- 150.0k 10 VCM SYNC 19 SYNC
8 s
VCC CS 4 CS
5 14 AGND
SCL
6 R4 R7 DRDY 5 DATA READY
I2C BUS SDA 8 VRLO
3 7 357k 4.53k
A0 VOUT +5V 6 DGND RST 18
SLAVE 2 RESET
ADDRESS BUS A1 C2 8
(0101000x) 1 10µF VCC
9 VRHI MODE 20
A2 VSS
7 RH WP-L 1 WRITE
4 s PROTECT
1.6Hz LPF 5 RW SCL 2
U2 I2C BUS
50k 6
ISL21400 s R5 3 2 VIN VOUT
6 RL SDA +5V
10.7k
GND GND R9
U4 1 4 2k
COLD JUNCTION COMPENSATION 4 U3
R8 ISL21009-25
C3
s 1.05k s ISL95810 C4
0.01µF
PROGRAMMABLE GAIN 10µF
s GAIN = 30 TO 150
FIGURE 42.
The programmable gain amplifier (U1, U3) provide a gain Low pass filters (R1, R2, C1) provide noise filtering with a
from 30 to 150 that is programmed via the I2C bus with the 8Hz cut-off frequency. R3 is used for a return current path for
digital pot for each of the thermocouple types as shown in the EL8173 input bias current. An additional low pass filter
Table 7. (R4, R5, C2) attenuates the ISL21400’s output noise voltage
with a 1.6 Hz cut-off frequency.
TABLE 7. THERMOCOUPLE TYPES
D-POT A high resolution (24-bit) Sigma-Delta A/D Converter,

TC TYPE MAX VOUT GAIN CODE10 HI7190, converts the output of the instrumentation amplifier,
EL8173, with a full scale input voltage of 2.5V set by the
E 68.97mV 36.34 195
ISL21009-2.5 voltage reference.
J 42.30mV 59.10 094
K 50.64mV 49.37 126 Thermocouple Input with 4mA to 20mA

T 17.82mV 140.3 000
Output Current
Another output option for a thermocouple input circuit is an
Cold junction compensation is provided by a programmable industry standard 4mA to 20mA current transmitter. The
reference/temperature sensor (U2) and resistor divider theory of operation for a 4mA to 20mA current transmitter
network R4 and R5 according to the following table with circuit is described in Intersil Application Note AN177 with
AV = 1 and N register = 0. Figures 33, 34, and 35; this theory of operation applies to the
thermocouple circuit shown in Figure 43, and therefore, will
TABLE 8. COLD JUNCTION COMPENSATION not be repeated.
TC TYPE VCJC (µV) M REGISTER
E 61.0 0
J 51.7 20
K 40.5 43
T 40.7 43
23 AN1298.2
May 27, 2009
+5V U5
ISL60002BIH325Z-TK D1
U1 U4 LM2936M-5.0
VOUT VIN 1 VOUT VIN 8 B140
EL8173
J-TYPE
8Hz INPUT FILTER 7 GND
THERMOCOUPLE
VS+ C3 C4 GND
(51.7µV/C) R1, 1k
3 IN+ VS- 4 0.001µF 10µF 2 3 6 7
C1 C5
R2, 1k 10µF (VTC) 4.7µF
2 IN-
+5V
R8 U3
D2 R3
499k EL8176 Q1
BAT54C 1M
(0V TO 2.5V) 7 IRLL014N
+5V VOUT 6 3
6
+Vloop
(VCJC) 8 R9 2
+5V FB+ 7VDC TO 30VDC
PROG. 127k R10 R13
R6 80.6k 4 R12 10
R14 R15 8 5 FB-
VCC R4 57.6k, 1% 100k
LOOP
VOUT 7 357k (INTERNAL "GROUND") RESISTOR
5 SCL GAIN = 58.6
SCL (51.7µV/C) R11
6 SDA R7
SDA 100
1k, 1%
I2C BUS 4 VSS
A0 A1 A2 1.6Hz LPF
U2
ISL21400 3 2 1 R5 CURRENT TRANSMITTER
C2
SLAVE ADDRESS 10.7k, 1% 10µF
(010100x)
RTN
PROG.
COLD JUNCTION COMPENSATION
ISL21400 REGISTER VALUES

AV = 1, N = 0
J-TYPE M = 20 VCJC = 51.7µV/C
FIGURE 43.
The circuit uses the unique features of the Intersil EL8173 RTD Input with A/D Converter Output
Instrumentation Amplifier to simplify the Thermocouple
Another popular industry standard temperature sensor is the
interface to a 4mA to 20mA Current Transmitter circuit.
RTD whose resistance varies with temperature, and is
Since this is circuit is shown for a single J-type
typically specified with a nominal resistance at +25°C. For
thermocouple, a fixed gain of 58.6 is used so that the output
example, a PT100 RTD has a resistance of 100Ω at 0°C.
voltage of the EL8173 is +2.5V at the maximum
The shape of the resistance vs temperature curve is
thermocouple temperature. The ISL21400 programmable
described by Equation 73, a second order equation, with a
voltage reference/temperature sensor is used for cold
unique alpha value as defined by DIN EN 60751. For a
junction compensation. Since the ISL21400 has non-volatile
PT100 RTD with alpha = 0.385%/ °C:
storage of the register values, it can be programmed either
2 3
prior to PCB assembly or programmed via the I2C bus as RTD = R 0 ( 1 + A∗ T + B∗ T + C∗ ( T – 100 )∗ T ) (EQ. 73)
shown in this schematic. It must be cautioned that the I2C
programming “ground” is not at the same potential as the Where: A = 3.9083 E-3, B = -5.775 E-7, C = -4.183 E-12
“Internal Ground” or loop supply ground; therefore, when below 0°C and zero above 0°C.
programming U2, the loop supply power supply or
RTDs are typically biased with 1mA to 5mA to minimize self-
associated grounds must not be connected, or the I2C
heating effects; this low operating current generates very low
programming system must be floating off ground.
voltage levels shown in Table 9.
Low pass filters (R1, R2, C1) provide noise filtering with a
TABLE 9. TYPICALLY BIAS RTD’s
8Hz cut-off frequency. R3 is used for a return current path for
the EL8173 input bias current. An additional low pass filter TEMPERATURE RTD VRTD @ 1mA
(°C) (Ω) (mV)
(R4, R5, C2) attenuates the ISL21400’s output noise voltage
with a 1.6Hz cut-off frequency. -40 84.3 84.3
Since the 4mA to 20mA loop voltage can be as high as 0 100.0 100.0
24VDC, a high voltage linear voltage regulator (U5) is used +100 138.5 138.5
to generate an internal +5V supply.
+200 175.8 175.8
24 AN1298.2
May 27, 2009
Since the RTD is often operated a great distance from In the circuit shown in Figure 44, RTD excitation current is
receiving electronics, the use of differential voltage sensing supplied by R1 and R2 operating from +5V. It would appear
is used to reduce the errors generated by high mode voltage that this current is not accurate enough for a high precision
induced noise. temperature measurement. And, that is true except for the
trick that is played by utilizing the ratiometric mode of
The circuit in Figure 44 shows an RTD interface to a high
operation with the A/D Converter.
resolution A/D Converter using an EL8173 Instrumentation
Amplifier to differentially sense the RTD output and provide TABLE 10.
the proper gain for the input to the A/D Converter. Ratiometric
TEMP. RTD IEXT VRTD @ 1mA CODE
mode operation of the A/D Converter eliminates the error (°C) (Ω) (mA) (mV) OUT10
introduced by variations in the RTD excitation current.
-40 84.3 1.22 84.3 7 778 756
0 100.0 1.22 100.0 9 227 469

IEXT +100 138.5 1.21 138.5 12 780 044
Rw
+200 175.8 1.20 175.8 16 240 345
+
VOUT
RTD
Rw
-
Rw
FIGURE 44.
R1
2k Y1 10MHz
+5V
U1 17 16
EL8173 OSC1 OSC2
R2
2k VS+ 7 +5V 13 AVDD DVDD 15
+5V +5V
Rw1
3 IN+ VS- 4 9 VRHI SCLK 1 CLOCK
RTD s 8 VRLO SDIO 3
2 IN- DATA I/O
PT100
3-WIRE Rw2 VOUT 6 (VOUT) 12 VINHI SDO 2 DATA OUT
8 FB+
11 VINLO SYNC 19 SYNC
R3
Rw3 5 FB- 10k 10 VCM CS 4 CS
GAIN = 11 14 AGND DRDY 5 DATA READY
Rw1, Rw2, Rw3 - LEAD RESISTANCE
6 DGND RST 18
#22 AWG WIRE - 0.0168Ω/Ft RESET
R4
1k 7 AVSS MODE 20
+5V -5V
U5
HI7190
24 BIT SIGMA DELTA
A/D CONVERTER
GAIN = 11
R5
10k
R6
1k
FIGURE 45.
25 AN1298.2
May 27, 2009
Code = 2N*(VOUT - 0)/(IEXT*R1)

VCC A/D CONVERTER
Code = 2N*Gain*IEXT*RTD/(IEXT*R1)
REFHI
Code = 2N*Gain*RTD/R1
R1
Now, the output code is only dependant on the gain of the
EL8173 and value of R1, and the variations of IEXT are
REFLO
cancelled out by the ratiometric operation of the A/D
Iext
Converter.
Also, there is an error created by the wire resistance from

IN+ the RTD leads from the RTD to the voltage sensing point.
VOUT
Therefore, RTDs are often connected with 3-wire and 4-wire
Rtd IN+
lead configurations to reduce the effect of wire resistance.
By far, the most common configuration is the 3-wire
IN- IN-
connection, and many general purpose 3-wire RTDs are
EL8173 available. Three different configurations for RTD wiring are
GAIN
summarized in the following.
FIGURE 46. However, even with a 3-wire configuration, there is still an

error associated with the voltage drop caused by the wire
In the simplified circuit shown in Figure 46, IEXT = VCC/(R1 + resistance. The RTD circuit incorporates a technique which
RTD) and VRTD = IEXT*RTD, VOUT = Gain*IEXT*RTD provides 4-wire accuracy with a 3-wire RTD, and the effect of
wire resistance is eliminated completely.
For the A/D Converter, the digital output code,
N The voltage drop created by the wire resistance, Rw, is
2 × ( IN+ - IN- ) (EQ. 74)
CODE = -------------------------------------------------- multiplied by the same gain as the EL8173, and then the
REF HI – REF LOW
differential input of the A/D Converter (U5) subtracts off the
Where N = Resolution effect of the wire resistance, Rw.
REFHi - REFLo = IEXT*R1
Iext
Iext Rw
Iext Rw
Rw
RTD
RTD PT100 VOUT Rw
RTD
PT100 VOUT 3-WIRE PT100 VOUT
Rw
2-WIRE Rw 4-WIRE Rw
Rw
Rw
VOUT = Iext*(RTD + 2*Rw)
VOUT = Iext*(RTD + Rw)
ERROR = Iext*2*Rw VOUT = Iext*RTD
ERROR = Iext*Rw
ERROR = 0
FIGURE 47A. 2-WIRE CONNECTION FIGURE 47B. 3-WIRE CONNECTION FIGURE 47C. 4-WIRE CONNECTION
FIGURE 47.
26 AN1298.2
May 27, 2009
Rs
0.005Ω
1.2V OUTPUT
OUTPUT VOLTAGE 10A
REMOTE SENSE AFTER Rs AT POINT OF LOAD

Ra
FB OR SENSE
POWER SUPPLY CIRCUIT Rb

3.3V
7 EL8173
R1 R2
10k 10k VS+
Ra AND Rb SET THE 2 IN-
OUTPUT VOLTAGE
3 IN+
C1 C2 VOUT 6 VOUT = 0V to +2.5V

0.1µF 8 FB+ 0.25V/A
0.1µF
5 FB- Rf
VS- 48.7k
4
GAIN = 50
Rg
1k
FIGURE 48.
Low Voltage High Side Current there is often a current sense resistor used to monitor the
inductor current. If this is the case, the output current can be
Sense measured with that current sense resistor since the average
Due to the rail-to-rail input stage of the EL8173, high side value of the inductor current is equal to the load current in a
current sensing is very easy to implement, as shown in buck regulator.
Figure 48.
The circuit shown in Figure 49 is an example of using the
This circuit is appropriate for any power supply circuit with or current sense resistor, Rs, that is already a part of the current
without remote sense capability. The output current is mode control loop to sense load current. There is a ripple
measured by a current sense resistor, Rs that is scaled for voltage across Rs that is the inductor ripple current * Rs. The
the desired output voltage and resistor power rating. R1, R2, inductor ripple current is usually 30% to 50% of the load
C1, and C2 are a simple low pass filter to attenuate the current and is set by the switching frequency and inductor
power supply output ripple and noise. Resistors Rf and Rg value. This ripple voltage is essential for the current mode
set the gain of the EL8173 for the desired full scale output control loop, but must be filtered to obtain the output load
voltage. current; this filter is performed by R1, R2, C1, and C2. Notice
Rf that even though the input voltage of the DC/DC converter is
V OUT = I OUT × R S × 1 + ------- (EQ. 75)
R +12V, the common mode voltage that is applied to the
g
EL8173 is the output voltage; in this case, 1.2V. As long as
In this circuit, Equation 76 shows a full scale voltage of 2.5V. the output voltage is <5V, the input voltage can be much
higher.
V OUT = I OUT × 0.005 × ⎛ -------------------------⎞
1 + 48.7K
⎝ 1K ⎠ If the inductor current is sensed by using the switching FET’s
V OUT = 0.25 × I OUT (EQ. 76) ON resistance as a current sense element, this method is
not possible with the EL8173 circuit.
An accurate output voltage is obtained since remote sense is The output current can also be sensed by using the
used by connecting Ra after the sense resistor, Rs. If remote inductor’s DCR (DC Resistance) as a current sense element
sense is not possible, care should be exercised to minimize as shown in the following circuit. This example in Figure 50
the voltage drop across Rs. shows using the EL7566, but this method applies to any
The previous circuit uses an external sense resistor to buck mode switching regulator.
monitor the output current. If the DC/DC is a buck converter
which uses an internal controller with current mode control,
27 AN1298.2
May 27, 2009
VIN = 12V
Q1 Rs
TG
L1 0.005Ω
1.2V OUTPUT
10A
Cout
CURRENT MODE BG Q2
PWM CONTROLLER
+IS
-IS
3.3V
R2 7 EL8173
R1
10k 10k VS+
2 IN-
3 IN+
C1 C2 VOUT 6 VOUT = 0V TO +2.5V

0.1µF 8 FB+ 0.25V/A
0.1µF
5 FB- Rf
VS- 48.7k
4
GAIN = 50 Rg
1k
FIGURE 49.
L1
P/O EL7566
COILCRAFT, DO3316P-272HC
2.7µH
DCR = 12mΩ
+5V LX 2.5V OUTPUT
6A
C5
150µF
EL7566 DEMO BOARD
+5V
R1 7 EL8173
R2
10k VS+
10k
2 IN-
3 IN+
C2 VOUT 6 VOUT = 0V to +3.0V

C1
0.1µF 8 FB+ 0.5V/A
0.1µF
5 FB- Rf
VS- 40.2k
4
GAIN = 41.7 Rg
1k
FIGURE 50.
28 AN1298.2
May 27, 2009
In the circuit shown in Figure 50, the R1 and C1 filter is sensing the output current. Due to the high currents, the use
extremely important because it remove the voltage square of current sense resistors become very impractical due to
wave (swinging between the input voltage and ground) that their low values to minimize their power dissipation. For
is applied to the inductor. The values for R1 and C1 should example, with a 50A output current, the current sense
be selected to attenuate the signal to a level that is resistor must be <400µΩ to keep the power dissipation <1W.
appropriate for the VOUT noise that is acceptable. In addition, it is very difficult from a PCB layout viewpoint to
break a high current power plane to insert a current sense
Since the DCR of the inductor is being used as a current sense
resistor, and that forces the plane to neck-down to a very
resistor, there are several factors which degrade the accuracy
narrow current flow path.
of this approach. First, most inductors are specified for only
maximum DCR; for example, the Coilcraft DO3316P-27HC High current DC/DC converter outputs now take advantage
shown above is specified for a DCR of 12mΩ, maximum. Actual of advances in multi-phase DC/DC converters where a
lab measurements should the DCR to be 9mΩ. Vishay offers a multiple lower current DC/DC conversion stages are
product line of inductors with a specified tolerance on the connected in parallel to obtain the necessary high output
inductor DCR; for example, IHLP2525CZ-07 product family current. Rule of thumb operates each phase at 15A to 20A
guarantees a DCR with ±5% tolerance. so that for a 40A output current either 2- or 3-phases can be
operated in parallel.
Second, the inductor’s internal winding’s have a temperature
coefficient of +0.393%/°C (copper wire) which can be a large With multi-phase DC/DC converters the output current of
error source if the inductor is allowed to get hot from ambient each phase can be measured with a current sense resistor
temperature or self-heating due to core losses and DCR or DCR current sensing. The output from each current sense
power loss. If the error from this source is critical to the circuit is summed together to get the total load current. An
application, a thermistor could be mounted in close proximity additional feature of this scheme is that the current balance
to the inductor and be used to compensate the temperature of each phase can be monitored. The circuit using a
coefficient of the copper windings. ISL28273 (dual EL8173) current sense circuit is shown in
Figure 51 for a 30A, two phase circuit.
High current (>30A) DC/DC converter outputs for
microprocessor cores present very unique challenges for
VIN = 5V
Q1 L1
0.33µH
VOUT = 1.2V AT 30A
Cout U1
Q2 +5V
16 ISL28273
R1 VS+
10k 6 IN+A OUTA 2 PHASE 1 Iout
Vout1
R2
R5 200mV/A
10k 5 IN-A
61.9k R9
VIN = 5V C1 C2 FB-A 4 4.99k
0.1µF 0.1µF TOTAL Iout
Q3 L2 R6 Vout = 0V to +3.0V
0.33µH 1k 100mV/A
FB+A 3 R10
4.99k
Q4
R3
10k 11 PHASE 2 Iout
IN+B OUTB 15
Vout2
U2 R4
200mV/A
ISL6568 10k 12 IN-B R7
F = 600kHz L1, L2: 61.9k
C3 C4 FB-B 13
IHLP-2525CZ-07 GAIN = 62.5
0.1µF 0.1µF
±5% DCR TOLERANCE
DCR = 3.2mΩ R8
1k
FB+B 14
VS-
8
FIGURE 51.
29 AN1298.2
May 27, 2009
The output current of each phase is measured by the DCR For this application, it is assumed VOUT would be measured
of L1 and L2 as explained in the previous example. VOUT1 with a microprocessor A/D Converter with a full scale voltage
and VOUT2 are proportional to the output current of each of 2.5V. Each channel is scaled for an output voltage, VOUT,
phase with a scale factor of 200mV/A. The two outputs, equal to 2.0V at maximum load current to provide an
VOUT1 and VOUT2, are summed together with R9 and R10 to overload measurement capability of 25%.
give a total output current, Total IOUT, with a scale factor of
For each amplifier,
100mV/A.
Sensed voltage, Vs = IOUT*Rs
This basic scheme can be extended to any number of
phases for extremely high output currents exceeding 100A. VOUT = Gain*Vs
VOUT = Gain*Rs*IOUT
Multiplexed Low Voltage Current
TABLE 11. SENSED VOLTAGE
Sense
VOUT AT
In a multiple voltage computer power supply, it is often VOUT MAX LOAD
necessary to monitor the output current from each DC/DC SENSITIVITY CURRENT
converter with an A/D Converter. When the EN pin of the EN IOUT(AMPS) (V/A) (V) GAIN
ISL28271 and ISL28272 are enabled (i.e., device shutdown), 1 20 0.10 2.0 100
the output stage goes into a high impedance state. This
2 10 0.20 2.0 100
allows multiple VOUT pins to be connected together for
multiplexed output applications. Since the output stage is in 3 4.0 0.50 2.0 100
a high impedance state, only one set of feedback resistors 4 7.5 0.27 2.0 134
(Rf, Rg) are required if all the amplifiers are operating with
the same gain. Likewise, if different gains are required for
The gains of the two amplifiers of U1 are both set to 100 by a
each amplifier, separate feedback resistors can be used to
single feedback resistor divider network, R9 and R10. The
set a unique gain on each amplifier.
gains of U2 are different in order to get the same VOUT
Figure 52 demonstrates the multiplexing scheme for a power sensitivity using standard current sense resistor values.
system with four output voltages; 1.2V at 20A, 1.8V at 10A, Gain A is set to 100 by R11 and R12, and Gain B is set to 134
3.3V at 4A, and 5.0V at 7.5A. by R13 and R14.
The dual instrumentation amplifier, ISL28271, is used to The EN lines (EN1, EN2, EN3, EN4) select the desired
minimize parts count and circuit size. Each power supply measurement channel.
load current is monitored with a low value current sense
resistor (RS1, RS2, RS3, and RS4) to minimize voltage drop
across the resistor. Input protection resistors (R1 to R8) limit
the input fault current to <5mA in case of a short circuit on
the OUT connection.
30 AN1298.2
May 27, 2009
Rs1 0.001Ω
1.2V IN 1.2V OUT, 20A
Rs2 0.002Ω
1.8V IN 1.8V OUT, 10A
R1 R2 R3 R4
EN1 U1
1k 1k 1k 1k ISL28271
7 6 5 11 12
2
16 VS+ ENA IN+A IN-A IN+B IN-B VOUTA VOUT
+5V
8 15
VS- ENB FB+A FB-A FB+B FB-B VOUTB
10 3 4 14 13 R9
EN2 97.6k
GAIN A = GAIN B = 100

R10
1.0k
Rs3 0.005Ω
3.3V IN 3.3V OUT, 4A
Rs4 0.002Ω
5.0V IN 5.0V OUT, 7.5A
R5 R6 R7 R8
EN3 U1
1k 1k 1k 1k ISL28271
7 6 5 11 12
2
16 VS+ ENA IN+A IN-A IN+B IN-B VOUTA
+5V
8 15
VS- ENB FB+A FB-A FB+B FB-B VOUTB
R11 R13
10 3 4 14 13
97.6k 133k
EN4
GAIN A = 100
GAIN B = 133.5
R12 R14
1.0k 1.0k
FIGURE 52. MEASUREMENT OF POSITIVE AND NEGATIVE CURRENT FLOW
31 AN1298.2
May 27, 2009
LOAD CURRENT = 2A, MAX

X1 AND X2 MUST BE 0V TO +5V
Rs
0.01Ω
X1 X2
+5V
R1 R2 U1
EL8170
4.7k 4.7k
+5V
7 VS+
D1 4 VS- VOUT 6
BAT54S VOUT = IOUT + 2
2 IN- R3 R5
250k 100k
3 IN+
8 (20mv)
FB+
5
FB-
R4 R6
1.0k 1.0k
FIGURE 53. CURRENT MONITORED WITH LOW VALUE RESISTOR
Bi-Directional Current Sense TABLE 12.
The use of the FB pins of the EL8170 make it an ideal choice LOAD CURRENT (ILOAD) VOUT
for a bi-directional current sense circuit for battery gas -2A 0.0V
gauging or current monitor in a H-bridge configuration as
0A +2.0V
shown in the following circuits.
+2A +4.0V
In Figure 53, current is monitored with the use of a low value
resistor Rs. R1, R2, and D1 protect the EL8170 from The range of the measured current can easily be changed
overvoltage which would be applied with excessive load by proper selection of Rs, Gain and FB+ voltage.
current or a short circuit on the output, X1 or X2. The
amplifier is set for a gain of 100 with R5 and R6. R4 and R5 The circuit in Figure 54 shows the EL8170 set-up as a
offset the FB+ pin at 20mV to center 0A at mid-range of the battery gas gauge to monitor both charging current and
output voltage VOUT. discharging current.
Sensed voltage is shown in Equation 77. In this circuit, when the battery is charging, the current in Rs
V S = I LOAD∗ R S will be negative (i.e., flowing from X2 to X1). The EL8170
output voltage will be between 0V and +2V. When the
V OUT = Gain∗ ( V S + V FB+ ) battery is being discharged, the current flow will be from X1
to X2, and the EL8170 output voltage will be between +2V
V OUT = Gain∗ ( I LOAD × R S + V FB+ )
and +4V.
+5 × R 4
V FB+ = ---------------------
R4 + R5
V OUT = 100∗ ( I LOAD × 0.01 + 0.02 )
V OUT = ( I LOAD + 2 ) (EQ. 77)
32 AN1298.2
May 27, 2009
BATTERY CHARGER, POWER SUPPLY
Rs D3
0.01Ω
SYSTEM LOAD
X1 X2 D2
+5V
BT1
R1 R2 U1
LITHIUM-ION 4.7k 4.7k EL8170
+5V
(4.2V) 7 VS+
D1 4 VS- VOUT 6
BAT54S VOUT = IOUT + 2
2 IN-
R3 R5
250k 100k
3 IN+
8 (20 mv)
FB+
5
FB-
R4 R6
1.0k 1.0k
FIGURE 54. EL8170 SETUP AS A BATTERY CHARGER
If a more direct measurement for the current polarity and Figure 56 shows the bi-directional current source circuit
increased output voltage sensitivity is required, the circuit configured to monitor the motor current in a H-bridge circuit.
shown in Figure 55 can be used. The direction of the motor (CW, CCW) is monitored by the
polarity bit depending on the direction of current flow in the
In Figure 55, U1 is used to measure positive current flow (X1
motor. The rail-to- rail input capability of the EL8170 allows
to X2) and U2 is used to measure negative current flow (X2
current sensing at ground level (Q1 and Q4 ON) or at +5V
to X1). The polarity of the current is detected by U3 which is
(Q3 and Q2 ON). If pulse width modulation is used to control
being used a zero crossing detect comparator. The EN pins
the speed of the motor, filter capacitors C1 and C2 should be
of the EL8170 (U1, U2) are used to turn on the proper
used to obtain the average value of the motor current. The
amplifier depending if the current flow is positive or negative.
value of the capacitors should be selected based on the
In the above circuit, current is monitored with the use of a
PWM frequency and desired overall accuracy.
low value resistor Rs. R1, R2, and D1 protect the EL8170’s
from over-voltage which would be applied with excessive
load current or a short circuit on the output, X1 or X2. When
this bi-directional current sense circuit is used in a PWM
application such as a H-bridge, C1 and C2 can be added to
filter the PWM signal for an average current value.
The amplifiers are set for a gain of 100 with R5 and R6. The
minimum sensed current is set by the EL8170 offset voltage.
V OS
I MIN = ------------
RS
0.25mV
I MIN = ---------------------
0.01Ω
I MIN = 25mA (EQ. 78)
33 AN1298.2
May 27, 2009
Rs
0.01Ω
X1 X2
R1 R2
4.7k D1 +5V
4.7k
BAT54S
U1 10k
C1 C2 ISL28271
SEE TEXT SEE TEXT +5V
7 VS+ ENA 7
4 VS- VOUTA 2
3 IN+ FB+A 3
2 IN- FB-A 4
+Iout AMP
U1
ISL28271
+5V
7 VS+ ENB 10
4 VS- VOUTB 15
VOUT
1V/A
3 IN+ FB+B 14 R3
100k
2 IN- FB-B 13
-Iout AMP R4
AV = 100
1.0k
U2
ISL28271
+5V +Iout
7 VS+ ENA 7
-Iout
4 VS- VOUTA 2 Q1
2N7002
3 IN+ FB+A 3
2 IN- FBA- 4
POLARITY DETECT
FIGURE 55. MEASUREMENT OF POSITIVE AND NEGATIVE CURRENT FLOW
34 AN1298.2
May 27, 2009
+5V
Q1 Q3
Rs
0.01Ω
+ -
X2 VOUT VOUT = Imotor

MOTOR
X1 POLARITY CLOCKWISE = +5V

COUNTER CLOCKWISE = 0V
EL8170 CIRCUIT
Q2
Q4 (GAIN = 100)
FIGURE 56. BI-DIRECTIONAL CURRENT SOURCE CIRCUIT
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
35 AN1298.2
May 27, 2009

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Instrumentation Amplifier Application Note

Application Note May 27, 2009 AN1298.2

Review of Standard Instrumentation Amplifier Design Techniques ................................................................................................ 2

Monolithic Instrumentation Amplifier Architecture ........................................................................................................................... 4

Introduction to Instrumentation Amplifier Product Family................................................................................................................ 4

Instrumentation Amplifier Specifications ......................................................................................................................................... 4

Instrumentation Amplifier Product Family Theory of Operation....................................................................................................... 6

Features of Instrumentation Amplifier Product Family .................................................................................................................... 7

Care and Feeding of Instrumentation Amplifiers ............................................................................................................................. 10

Pressure Sensor Interface Circuit ................................................................................................................................................... 21

Thermocouple Input with A/D Converter Output ............................................................................................................................. 22

Thermocouple Input with 4mA to 20mA Output Current ................................................................................................................. 23

RTD Input with A/D Converter Output ............................................................................................................................................. 24

Low Voltage High Side Current Sense............................................................................................................................................ 27

Multiplexed Low Voltage Current Sense ......................................................................................................................................... 30

Bi-Directional Current Sense........................................................................................................................................................... 32

Introduction to the Instrumentation An Instrumentation Amplifier is a confused animal –

EL8170 Bipolar 1 100 192 No

EL8171 PMOS 1 10 450 No IN+ +

EL8173 Bipolar 1 10 396 No

+VCC +VCC Review of Standard Instrumentation

and a common voltage of 10V, the inputs to the op amp will

V OUT = ( IN+ – IN- ) × Gain + V REF (EQ. 4) FIGURE 5.

It can be shown that the CMRR is: -

Where x = R 4 ⁄ ( R 3 + R 4 ) × ( R 1 + R 2 ) ⁄ R 1 – R 2 ⁄ R 1 (EQ. 6) IN+

FIGURE 6. TWO AMPLIFIER INSTRUMENTATION AMPLIFIER

TOLERANCE GAIN =1 GAIN = 10 GAIN =100

Additionally, the REF input must be driven by a very low

FIGURE 7. CLASSIC THREE AMPLIFIER INSTRUMENTATION

Input Stage Bipolar Bipolar PMOS PMOS

Minimum Gain 100 10 10 100

Gain Set 2 Ext R 2 Ext R 2 Ext R 2 Ext R

Supply Current: Enabled 65 65 65 60 65 60 µA

Supply Current: Shutdown - - - - - 4 - 4 µA

Minimum VCC 2.4 2.4 2.4 2.4 VDC

Maximum VCC 5.5 5.5 5.5 5.5 VDC

Input Bias Current, Maximum 3000 2000 2500 2000 2500 50 30 50 30 pA

Input Bias Current Cancellation Yes Yes - -

Bandwidth (-3dB) at AV = 10 - 396 265 450 180 - kHz

Rail-to-Rail Input Yes Yes Yes Yes

Rail-to-Rail Output Yes Yes Yes Yes

Output in Shutdown Mode - - - HiZ - HiZ

PSRR (Typ) 106 110 110 90 95 90 100 100 dB

eN at 1kHz 58 60 60 220 210 220 240 80 78 nv/√Hz

Input Protection - Diodes to Yes Yes Yes Yes

Input Protection - Diodes Yes No No No

Max Input Diode Current 5 5 5 5 mA

Package SO8 SO8 SO8 SO8

RoHS Compliant Yes Yes Yes Yes

FIGURE 9. SIMPLIFIED SCHEMATIC

Instrumentation Amplifier Product Family

Similarly for Q3 and Q4: 0 = ( V1 – V2 ) + ( V4 – V3 ) (EQ. 28)

0 = -V IN + ( FB- – FB+ ) (EQ. 29)

The use of a bipolar transistor input stage vs. the MOSFET

Rail-to-rail operation for both the inputs and outputs is an

INPUT OFFSET VOLTAGE (µV)

the IN inputs and a single input stage for the FB inputs. An

250 COMMON-MODE INPUT VOLTAGE (V)

INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE

VIC - COMMON-MODE INPUT VOLTAGE (V)

FIGURE 19. TYPICAL RAIL-TO-RAIL INSTRUMENTATION

In this configuration, adjustable gain is possible with external In this case:

FB- = V REF + R g × ( V OUT – V REF ) ⁄ ( R f + R g )

Code = 2N(VOUT - 0)/(IEXTR1)