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LECTURE NOTES

ON Embedded systems

2018

2019

IV B. Tech I Semester (JNTUA-R15)

Mr. M. Jagadeesh Babu, Associate Professor

LECTURE NOTES ON Embedded systems 2018 2019 IV B. Tech I Semester (JNTUA-R15) Mr. M. Jagadeesh
LECTURE NOTES ON Embedded systems 2018 2019 IV B. Tech I Semester (JNTUA-R15) Mr. M. Jagadeesh

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Unit 1 :Introduction to Embedded System

Page No

1.1 Embedded system introduction

Unit 1 :Introduction to Embedded System Page No 1.1 Embedded system introduction 1.2 Host and Target

1.2 Host and Target Concept

1.3 Embedded Applications 1.4 Features and Architecture considerations for Embedded systems- ROM, RAM, Timers 1.5
1.3 Embedded Applications 1.4 Features and Architecture considerations for Embedded systems- ROM, RAM, Timers 1.5
1.3 Embedded Applications 1.4 Features and Architecture considerations for Embedded systems- ROM, RAM, Timers 1.5
1.3 Embedded Applications 1.4 Features and Architecture considerations for Embedded systems- ROM, RAM, Timers 1.5
1.3 Embedded Applications 1.4 Features and Architecture considerations for Embedded systems- ROM, RAM, Timers 1.5

1.3 Embedded Applications

1.4 Features and Architecture considerations for Embedded systems-

ROM, RAM, Timers

1.5 Data and Address Bus concept

1.6 Embedded Processor and their types

1.7 Memory types (Student seminar)

1.8 Overview of design process of embedded systems

1.9 Programming languages and tools for embedded design

Unit -II Embedded Processor Architecture

2.1

CISC Vs RISC design philosophy

2.2

Von-Neumann Vs Harvard architecture

2.3

Introduction to ARM architecture and Cortex

M series

2.4

Introduction to the TM4C family viz.TM4C123x & TM4C129x and

its targeted applications.

2.5

TM4C block diagram

2.6

Address space

2.7

on-chip peripherals (analog and digital) Register sets

2.8

Addressing modes and instruction set basics.

Unit III : Overview of Microcontroller and Embedded Systems

3.1

Embedded hardware and various building blocks

3.2

Processor Selection for an Embedded System

3.3

Interfacing Processor, Memories and I/O Devices

3.4

I/O Devices and I/O interfacing concepts

3.5

I/O Devices and I/O interfacing concepts

3.6

Timer and Counting Devices,

3.7

Serial Communication and Advanced I/O,

3.8

Buses between the Networked Multiple Devices

3.9

Embedded System Design

3.10

Co-design Issues in System Development Process

3.11

Design Cycle in the Development Phase for an Embedded System

3.12

Uses of Target System or its Emulator and In-Circuit Emulator (ICE)

Development Phase for an Embedded System 3.12 Uses of Target System or its Emulator and In-Circuit
 
  UNIT-IV : Microcontroller fundamentals for basic programming Unit-V : Embedded communications protocols and
 

UNIT-IV : Microcontroller fundamentals for basic programming

Unit-V : Embedded communications protocols and Internet of Things

Unit-V : Embedded communications protocols and Internet of Things
Unit-V : Embedded communications protocols and Internet of Things
fundamentals for basic programming Unit-V : Embedded communications protocols and Internet of Things 4    
fundamentals for basic programming Unit-V : Embedded communications protocols and Internet of Things 4    
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fundamentals for basic programming Unit-V : Embedded communications protocols and Internet of Things 4    
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fundamentals for basic programming Unit-V : Embedded communications protocols and Internet of Things 4    
fundamentals for basic programming Unit-V : Embedded communications protocols and Internet of Things 4    
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fundamentals for basic programming Unit-V : Embedded communications protocols and Internet of Things 4    
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1.1 Embedded System

UNIT I Introduction to Embedded System

An embedded system is a combination of hardware and software with some attached

peripherals to perform a specific task or a narrow range of tasks with restricted resources. It is

an electronic system that is not directly programmed by the user, unlike a personal computer.

An embedded system is a device that incorporates a computer within its implementation,

primarily as a means to simplify the system design, and to provide flexibility; and the user of

the device is not even aware that a computer is present. It is a microcontroller-based, software-

driven, reliable, real time control system,. Autonomous or human or network interactive,

operating on diverse physical variables and in diverse environments, and sold in a competitive

and cost conscious market. Generally, an embedded system is a subsystem in ~ larger system

and it is application specific. The generic block diagram of an embedded system is shown in

Figure 1.1. Every embedded system consists of certain input devices such as: key boards,

switches, sensors, actuators; output devices such as: displays, buzzers, sensors; processor along

with a control program embedded in the off-chip or on-chip memory, and a real time operating

system (RTOS).

Input Output

memory, and a real time operating system (RTOS). Input Output Figure 1.1: Block Diagram of a

Figure 1.1: Block Diagram of a Generic Embedded System.

memory, and a real time operating system (RTOS). Input Output Figure 1.1: Block Diagram of a

An embedded system exhibits different characteristics such as: Single functionality, No re- programmability, Security, Reliability, Dependability, Robustness and Efficiency in terms of cost, weight, energy, size, and speed. Designing the system to meet these characteristics is very important in the success of the final product. A specialized computer system. That is part of a larger system or machine. Typically, an embedded system is housed on a single microprocessor board with the programs stored in ROM. Virtually all appliances that have a digital Interface -- watches, microwaves, VCRs, cars -- utilize embedded systems. Some embedded systems include an operating system, but many are so specialized that the entire logic can be implemented as a single program. Embedded systems programming is the development of programs intended to be part of a larger operating system or, in a somewhat different usage, to be incorporated on a microprocessor that can then be included as part of a variety of hardware devices. Several other definitions are:

A combination of computer hardware and software, and perhaps additional mechanical

A

combination of computer hardware and software, and perhaps additional mechanical

or other parts, designed to perform a dedicated function. In some cases, embedded systems are part of a larger system or product, as in the case of an antilock braking system in a car. Contrast with general-purpose computer.

A specialized computer system which is dedicated to a specific task. Embedded systems

A

specialized computer system which is dedicated to a specific task. Embedded systems

range in size from a single processing board to systems with operating systems (ex, Linux, Windows® NT Embedded). Examples of embedded systems are medical

equipment and manufacturing equipment.

A computer system that is a component of a larger machine or system. Embedded

A

computer system that is a component of a larger machine or system. Embedded

systems can respond to events in real time. Most digital appliances, such as watches or cars, utilize an embedded system.

Hardware and software that forms a component of some larger system and is expected to

Hardware and software that forms a component of some larger system and is expected to function without human intervention. Typically an embedded system consists of a single-board microcomputer with software in ROM, which starts running a dedicated application as soon as power is turned on and does not stop until power is turned off.

An embedded system is some combination of computer hardware and software, either fixed in capability

An embedded system is some combination of computer hardware and software, either fixed in capability or programmable, that is specifically designed for a particular kind of application device. Industrial machines, automobiles, medical equipment, cameras, household appliances, airplanes, vending machines, and toys (as well as the more obvious cellular phone and PDA) are among the myriad possible hosts of an embedded system.

and toys (as well as the more obvious cellular phone and PDA) are among the myriad

A phrase that refers to a device that contains computer logic on a chip inside it. Suchequipment is electrical or battery powered. The chip controls one or more functions of the

equipment is electrical or battery powered. The chip controls one or more functions of

the equipment, such as remembering how long it has been since the device last received

maintenance,

An embedded system is a special-purpose computer system, which is completelylong it has been since the device last received maintenance, encapsulated by the device it controls.

encapsulated by the device it controls. An embedded system has specific requirements

and performs pre-defined tasks, unlike a general-purpose personal computer.

1.1.2 Characteristics of an Embedded System:

The important characteristics of an embedded system are

Speed (bytes/sec) : Should be high speedThe important characteristics of an embedded system are Power (watts) : Low power dissipation Size and

Power (watts) : Low power dissipationembedded system are Speed (bytes/sec) : Should be high speed Size and weight : As far

: Should be high speed Power (watts) : Low power dissipation Size and weight : As

Size

and weight

: As far as possible small in size and low weight

Accuracy (% error) : Must be very accurateand weight : As far as possible small in size and low weight Adaptability: High adaptability

Adaptability: High adaptability and accessibility.and low weight Accuracy (% error) : Must be very accurate Reliability: Must be reliable over

Reliability: Must be reliable over a long period of time.accurate Adaptability: High adaptability and accessibility. So, an embedded system must perform the operations at a

So, an embedded system must perform the operations at a high speed

so that it can be

readily used for real time applications and its power consumption must be very low and the

size of the system should be as for as possible small and the readings must be accurate with

minimum error. The system must be easily adaptable for different situations.

1.1.3 Categories of Embedded systems:

Embedded systems can be classified into the following 4 categories based on their

functional and performance requirements.

based on their functional and performance requirements. Functional 1. Stand-alone embedded systems 2. Real time
based on their functional and performance requirements. Functional 1. Stand-alone embedded systems 2. Real time

Functional

1. Stand-alone embedded systems

2. Real time embedded system

a) Hard real time E.S

b) Soft Real time E.S

Performance

1. Small scale embedded system

2. Medium scale embedded s/m

3. Large scale embedded system Or

Real time E.S Performance 1. Small scale embedded system 2. Medium scale embedded s/m 3. Large

3. Networked embedded system

4. Mobile embedded system

Stand-alone Embedded systems:

Sophisticated Embedded Systems

A stand-alone embedded system works by itself. It is a self-contained device which

does not require any host system like a computer. It takes either digital or analog inputs from

its input ports, calibrates, converts, and processes the data, and outputs the resulting data to its

attached output device, which either displays data, or controls and drives the attached devices.

EX: Temperature measurement systems, Video game consoles, MP3 players, digital

cameras, and microwave ovens are the examples for this category.

Real-time embedded systems:

An embedded system which gives the required output in a specified time or which

strictly follows the time deadlines for completion of a task is known as a Real time system i.e.

a Real Time system, in addition to functional correctness, also satisfies the time constraints

.

There are two types of Real time systems. (i) Soft real time system and (ii) Hard real time

system.

Soft Real-Time system: A Real time system in which, the violation of time constraints A Real time system in which, the violation of time constraints

will cause only the degraded quality, but the system can continue to operate is known

as a Soft real time system. In soft real-time systems, the design focus is to offer a

guaranteed bandwidth to each real-time task and to distribute the resources to the tasks.

Ex: A Microwave Oven, washing machine, TV remote etc.

Hard Real-Time system: A Real time system in which, the violation of time A Real time system in which, the violation of time

constraints will cause critical failure and loss of life or property damage or catastrophe

is known as a Hard Real time system.

These systems usually interact directly with physical hardware instead of through a human

being .The hardware and software of hard real-time systems must allow a worst case execution

(WCET) analysis that guarantees the execution be completed within a strict deadline. The chip

selection and RTOS selection become important factors for hard real-time system design.

within a strict deadline. The chip selection and RTOS selection become important factors for hard real-time

Ex: Deadline in a missile control embedded system , Delayed alarm during a Gas leakage ,

car airbag control system , A delayed response in pacemakers ,Failure in RADAR functioning

etc.

Networked embedded systems:

The networked embedded systems are related to a network with network interfaces to

access the resources. The connected network can be a Local Area Network (LAN) or a Wide

Area Network (WAN), or the Internet. The connection can be either wired or wireless.

The networked embedded system is the fastest growing area in embedded systems

applications. The embedded web server is such a system where all embedded devices are

connected to a web server and can be accessed and controlled by any web browser.

Ex: A home security system is an example of a LAN networked embedded system where all

sensors (e.g. motion detectors, light sensors, or smoke sensors) are wired and running on the

TCP/IP protocol.

Mobile Embedded systems:

The portable embedded devices like mobile and cellular phones, digital cameras, MP3

players, PDA (Personal Digital Assistants) are the example for mobile embedded systems. The

basic limitation of these devices is the limitation of memory and other resources.

Based on the performance of the Microcontroller they are also classified into (i) Small

scaled embedded system (ii) Medium scaled embedded system and (iii) Large scaled embedded

system.

1.1.4 Classifications of Embedded systems

1. Small Scale Embedded Systems: These systems are designed with a single 8- or 16-

bit microcontroller; they have little hardware and software complexities and involve

board- level design. They may even be battery operated. When developing embedded

software for these, an editor, assembler and cross assembler, specific to the

microcontroller or processor used, are the main programming tools. Usually, C used

for developing these systems. C program compilation is done into the assembly, and

executable codes are then appropriately located in the system memory. The software

has to fit within the memory available and keep in view the need to limit power

fit within the memory available and keep in view the need to limit power dissipation when

dissipation when system is running continuously.

fit within the memory available and keep in view the need to limit power dissipation when

2. Medium Scale Embedded Systems: These systems are usually designed with a single or few 16- or 32-bit microcontrollers or DSPs or Reduced Instruction Set Computers (RISCs). These have both hardware and software complexities. For complex software design, there are the following programming tools: RTOS, Source code engineering tool, Simulator, Debugger and Integrated Development Environment (IDE). Software tools also provide the solutions to the hardware complexities. An assembler is of little use as a programming tool. These systems may also employ the readily available ASSPs and IPs (explained later) for the various functions for example, for the bus interfacing, encrypting, deciphering, discrete cosine transformation and inverse transformation, TCP/IP protocol stacking and network connecting functions.

3. Sophisticated Embedded Systems: Sophisticated embedded systems have enormous hardware and software complexities and may need scalable processors or configurable processors and programmable logic arrays. They are used for cutting edge applications that need hardware and software co-design and integration in the final system; however, they are constrained by the processing speeds available in their hardware units. Certain software functions such as encryption and deciphering algorithms, discrete cosine transformation and inverse transformation algorithms, TCP/IP protocol stacking and network driver functions are implemented in the hardware to obtain additional speeds by saving time. Some of the functions of the hardware resources in the system are also implemented by the software. Development tools for these systems may not be readily available at a reasonable cost or may not be available at all. In some cases, a compiler or retarget able compiler might have to be developed for these.

1.2 Host and Target machine

An embedded system is a special-purpose system in which the computer is completely encapsulated by the device it controls. Each embedded system has unique characteristics. The components and functions of hardware and software can be different for each system. Nowadays, embedded software is used in all the electronic devices such as watches, cellular phones etc. This embedded software is similar to general programming. But the embedded hardware is unique. The method of communication between interfaces can vary from processor to processor. It leads to more complexity of software. Engineers need to be aware of the software developing process and tools. There are a lot of things that software development tools can do automatically when the target platform is well defined. This automation is possible because the tools can exploit features of the hardware and operating system on which your

This automation is possible because the tools can exploit features of the hardware and operating system

program will execute. Embedded software development tools can rarely make assumptions about the target platform. Hence the user has to provide some explicit instructions of the system to the tools. Figure 1.2 shows how an embedded system is developed using a host and a target machine.

system is developed using a host and a target machine. Figure 1.2 Embedded system using host

Figure 1.2 Embedded system using host and target machine

Host machine:

The application program developed runs on the host computer. The host computer is also called as Development Platform. It is a general purpose computer. It has a higher capability processor and more memory. It has different input and output devices. The compiler, assembler, linker, and locator run on a host computer rather than on the embedded system itself. These tools are extremely popular with embedded software developers because they are freely available (even the source code is free) and support many of the most popular embedded processors. It contains many development tools to create the output binary image. Once a program has been written, compiled, assembled and linked, it is moved to the target platform.

Program Development Tool Kit

1.

Program development tool kit or IDE

2.

assembly mnemonics or C++ or Java or Visual C++ using the keyboard of the host system (PC) for entering the program.

assembly mnemonics or C++ or Java or Visual C++ using the keyboard of the host system

3.

Using GUIs for allowing the entry, addition, deletion, insert, appending previously written lines or files, merging record and files at the specific positions.

4.

Create source file that stores the edited file.

5.

File given an appropriate name by the programmer

4. Create source file that stores the edited file. 5. File given an appropriate name by

6.

Can use previously created files

7. Can also integrate the various source files.

8. Can save different versions of the source files.

9. Compiler, cross compiler, assembler,

of the source files. 9. Compiler, cross compiler, assembler, Target machine The output binary image is

Target machine

The output binary image is executed on the target hardware platform. It consists of two entities - the target hardware (processor) and runtime environment (OS). It is needed only for final output

1. Target system differs from a final system

2. Target system interfaces with the computer as well works as a standalone system

3. In target system might be repeated downloading of the codes during the development phase

4. Target system copy made that later on functions as embedded system

5. Designer later on simply copies it into final system or product.

6. Final system may employs ROM in place of flash, EEPROM or EPROM in embedded system.

ROM in place of flash, EEPROM or EPROM in embedded system. Figure 1.3 Host and Target

Figure 1.3 Host and Target interfacing

Examples:

1. Phillips LPC 21xx development board

2. MSP 430 development board

Figure 1.3 Host and Target interfacing Examples: 1. Phillips LPC 21xx development board 2. MSP 430

3.

TIVA TM4Cxxx development board

4.

4.
3. TIVA TM4Cxxx development board 4. TIVA 1.3 Embedded Applications MSP430 LPC 21xx Embedded systems used

TIVA

1.3 Embedded Applications

development board 4. TIVA 1.3 Embedded Applications MSP430 LPC 21xx Embedded systems used in various

MSP430

board 4. TIVA 1.3 Embedded Applications MSP430 LPC 21xx Embedded systems used in various applications are

LPC 21xx

Embedded systems used in various applications are listed in Table 1.1. It shows that embedded

systems have rapidly emerged as important computing discipline because of the technology

convergence in computers, consumer electronics, communications, entertainment etc. Further,

new applications m medical electronics, mobile communications etc., are being continuously

evolving and are being added to fulfil the ever growing requirements of the users.

S.No

Embedded System

Application

1

Home Appliances

Dishwasher, washing machine, microwave, Top-set box, security system, HVAC system, DVD, answering machine, garden sprinkler systems etc Fax, copy machine, smart phone system, modern, scanner, printers. Face recognition, finger recognition, eye recognition, building security system, airport security system, and alarm system. Smart board, smart room, OCR, calculator, smart cord. Signal generator, signal processor, power supplier, Process instrumentation, Router, hub, cellular phone, IP phone, web camera

2

Office Automation

3

Security

4

Academia

5

Instrumentation

6

Telecommunication

3 Security 4 Academia 5 Instrumentation 6 T e l e c o m m u

7 Automobile

8 Entertainment

9 Aerospace

10 Industrial automation

11 Personal

12 Medical

13 Banking & Finance

14 Miscellaneous:

Fuel injection controller, anti-locking brake system, air-bag system, GPS, cruise control. MP3, video game, Mind Storm, smart toy.

Navigation system, automatic landing system, flight

space explorer, space robotics.

Assembly line, data collection system, monitoring systems on pressure, voltage, current, temperature, hazard detecting system, industrial robot. PDA, iPhone, palmtop, data organizer.

attitude controller,

CT scanner,

monitor, blood

diagnostic device. ATM, smart vendor machine, cash register ,Share market Elevators, tread mill, smart card, security door etc.

ECG, EEG, EMG, MRI, Glucose

pressure monitor, medical

1.4 Features of an Embedded System

Embedded systems products have been effectively used not only in our day to day used

products but these are also used as wholly or partially unavoidable components in many high

end uses like military, scientific research, telecommunication etc. Its size may confined from

hand held cell phones to components of nuclear missile. Irrespective of its size it necessarily

consist of some hardware and software designed to work on hardware. So

Embedded Systems are called Product of Hardware and Software Co-design. Features of

different hardware and software units of embedded systems are explained in the following

sections.

1.4.1 Hardware features of standalone embedded systems

Standalone embedded system includes different types of processors, power supply unit, clock,

reset circuit, memories which are considered to be most essential hardware components of

standalone embedded systems. A brief discussion on important features of these components

are given below

1.4.1.1 Different types of processors used

Processor: A processor is the heart of the embedded system. It is responsible for execution of

instruction and controlling flow of data to and from processor. Designer should have proper

knowledge regarding efficiency of different types of processor and based on which one should

select the appropriate processor as per requirement. Different types of processors available can

based on which one should select the appropriate processor as per requirement. Different types of processors

be categorized into four broad categories (l) General purpose processor (GPP) (2) Application specific System processor (ASSP) (3) Multiprocessor system and (4) GPP core or ASIP core.

A GPP has the usage advantages over other processors because of

a). Having predefined known instruction set resulting fast system development. b). Board and I/O Interfaces designed for GPP can be used for different system changing the software. c) Ready availability of computer facilities in high level language along with compiler and debugger, resulting in fast development of a new system.

a) General Purpose Processor (GPP) may be any one of Microprocessor, Microcontroller, Embedded processor, Digital Signal Processor (DSP) and Media processor. Microprocessor is a single VLSI chip that has a CPU with caches, floating point processing arithmetic unit, pipelining and super scaling, units. Later units may present for faster processing. RAM is externally connected to CPU. Microcontroller is also a single chip VLSI unit with limited computational capability keeping all functional units /components inside the chip. Embedded processor may be microprocessor or microcontroller when design specially to achieve capabilities of fast context switching resulting lower latency, atomic ALU operation with no shared data problem RISC core for fast and precise calculations. ARM family processors, Intel i960 etc. belongs to this class. DSP as a GPP is a single chip VLSI having computational capabilities of a microprocessor and a multiply and Accumulate (MAC) unit(s). DSP is an essential units of an embedded system with very large instruction word (VLWI) processing capabilities. It process very efficiently Single Instruction Multiple Data (SIMD), Discrete Cosine Transformation (DCT) and Inverse Discrete Cosine Transformation (IDCT). DCT and IDCT are most useful for algorithms for signal analysing, coding, filtering noise cancellation, echo-elimination etc.

b) Application Specific System Processor (ASSP): ASSP is dedicated for faster processing and useful for applications like real time video processing which incorporates lots of processing before transmitting. It may also include some features of RTOS. ASSP provides hardwired solution for most of its time consuming tasks. For example ASSP chip i2ehip has TCP, UDP, IP, ARP and Ethernet 10/100 MAC Media Access Control) hardwired logic included into it. In practice, an ASSP is used as an additional processing unit for running the application specific tasks in place of processing using embedded software.

an additional processing unit for running the application specific tasks in place of processing using embedded

c) Multiprocessor System: As embedded algorithm has to work within strict deadline, sometimes it may not be possible to carry out the same with a single processor. In a real time video processing number of MAC operations required may be more than possible from one DSP unit. In such a case an embedded system may go for two or more processors. Similar requirement may be needed in modem cell phones which has to perform number of tasks. Multiprocessors are different tasks that have to be performed concurrently. The operations of all processors are synchronized to obtain an optimum performance.

are synchronized to obtain an optimum performance. d ) GPP or ASEP core: GPP core or

d) GPP or ASEP core: GPP core or ASIP core is integrated into either an Application Specific Integrated Circuit (ASIC) or a VLSI or an FPGA (Field programming Gate Array) core integrated with processor units. Lately a new innovation in this area is System on Chip (SOC). A SOC may be embedded with multiple processors, memories, multiple standard source solutions called IP (Intellectual Property) core and other logic and analog units. It may have also a network protocol embedded on it. It can embed DSP applications and FPGA core. For a number of applications GPP core may not be a suitable solution. For various security application, smart card, video game, mobile Internet, Gbps transceiver, Gbps LAN, missile system needs a special processing unit on a VLSI design circuit to function as a processor. These units are called Application Specific Instruction Processor (ASIP). Sometime for an application both configurable processor (FPGA or ASIP) and non - configurable processor (DSP or microprocessor or microcontroller) might be needed on a chip. Generally this type of applications are very important in some killer applications (application which is useful to millions of people) such as HDTV, cell-phone etc.

1.4.1.2 Power supply unit

Generally embedded system has its own Power supply unit. Four range of voltage (i) 5.0V + 0.25V (ii) 3.3V+ 0.3V (iii) 2.0V +0.2V (iv) 1.5V+0.2V are used for operation of different units. Additionally 12V+0.2V supply is needed for a flash or EEPROM and RS232 Serial Interfaces. Supply of voltage to the chip depends on number of pins provided in the chip which is generally in pair supply and ground. A processor may have more than two pins of Vdd Vss which are responsible for distribution of power and reduction of inferences in all the sections. Supply should separately power the (a) External I/O driving port (b) timers and (c) clock and reset circuits. Clock and reset circuit should be specially designed to be free from radio frequency inference

clock and reset circuits. Clock and reset circuit should be specially designed to be free from
either connected to an external power supply or use charge pump for necessary power supply.

either connected to an external power supply or use charge pump for necessary power supply. Example of first type may be Network Interface Card (NIC) and Graphics accelerator which do not have their own power supply are connected to PC power-supply line. In the second type charge pump brings power from a non-supply line. It consist of a diode in the series followed by a charging capacitor. The diode gets forward bias input from an external signal, say RTS (Request to Send) signal in case a mouse used with the computer. The charge pump inside the mouse store charge in inactive state and dissipate power when the mouse is used. An embedded system has to perform tasks continuously from power-up to power-off and may even be kept on continuously. Real Time Systems (RTOS) use Wait and Stop instructions and disabling certain units when not needed. This indeed is very important for saving power during program execution. Performing tasks at reduce clock rate is also a way to control power dissipation. Performance of software analysis during design phase can include power dissipation considerations also. A good design must optimize the conflicting needs of low power dissipation and fast efficient program execution.

1.4.1.3 Clock Oscillator

The function of this oscillator circuit is to provide an accurate and stable periodic clock signal to a processor. The processor needs a clock oscillator as clock controls the various clocking requirements of CPU. The clocking requirements are the system timers and CPU machine cycles. The machine cycle includes (i) Fetching code and data from memory and Decoding and execution and (ii) Transferring results to memory. The clock controls the time for executing an instruction. The clock circuit uses either a crystal (External to the processor) or a ceramic resonator (internally associated with the processor) or an external IC attached to the processor. (a)The crystal resonator gives the highest stability in frequency with temperature and drift in the circuit. The crystal in association with an appropriate resistance in parallel and a pair of series capacitance at both pins. The crystal is kept as near as feasible to the two pins of the processor, (b) The internal ceramic generator, if available in a processor, saves the use of the external crystal and gives a reasonable though not very high frequency (c) The external IC based clock oscillator has a significantly higher power dissipation compared to the internal processor resonator. It provides a higher driving capability, which might be needed when various embedded circuits of embedded systems concurrently driven for e.g. in multiprocessor based systems.

be needed when various embedded circuits of embedded systems concurrently driven for e.g. in multiprocessor based

1.4.1.4

Real time clock or timer units

A timer is suitably configured as system clock sometime referred as RTC (Real Time Clock). RTC is used by scheduler for real time programming. A hardware timer is a counter that is incremented at a fixed rate when the system clock pulses. There are several different types of timers available. A timer/counter can perform several different tasks. The CPU uses the timer to keep track of time accurately. The timer can generate a stream of pulses or a single pulse at different frequencies. It can be used to start and stop tasks at desired times A COP (computer operating properly) or watchdog timer checks for runaway code execution. The hardware implementation of watchdog timers varies considerably between different processors. In general watchdog timers must be turned on once within the first few cycles after reset and then reset periodically with software. Some watchdog timers can programmed for different time-out delays. The reset sequence is sometimes as simple as a specialized instruction or as complex as sending a sequence of bytes to a port. Watchdog timers either reset the processor or execute an interrupt when they time out.

More than one timers using the RTC may be needed for various timing and counting need. There may be hardware and software implementations of timers. At least one hardware timer device is must in a system which is used as system clock. The hardware timer gets the input from a clock out signal from processor and activates the system clock as per the number ticks present at the hardware timer. Number of hardware timers present are generally limited.

A software timer is a software that executes and increases or decreases a count variable

(count value) or an interrupt on a timer output or on a real time clock interrupt. A software timer can also generate interrupt on overflow of count value or the final value of count variable. Software timers are used as virtual timing devices. There are number of control

bits and time out status flags in each timer device. A timer device when given count inputs, in place of clock pulses performs as a counting device.

1.4.1.5 Interrupt Handlers

A system possesses a number of devices and the system processor has to control and

handle the requirements of devices by running appropriate Interrupt Service Routine (ISR) for each. An interrupt handling mechanism must exist in each system to handle interrupt from various processes in the system. An interrupt is an event that suspends regular

in each system to handle interrupt from various processes in the system. An interrupt is an

program operation while the event is serviced by another program. Interrupts increase the response speed to external events. Different microcontrollers have different interrupt sources which can include external, timer and serial port interrupts. When an interrupt is received the current operation is suspended, the interrupt is identified and the controller jumps (vectors) to an interrupt service routine. There are two sources of interrupt: hardware and software. Hardware interrupts include a signal to a pin, timer overflow, and serial port interrupts. Software interrupts are commands given by the programmer. There are two different interrupt types: maskable and non-maskable. A maskable interrupt can be disabled and enabled while non-maskable interrupts cannot be disabled and are therefore always enabled. Most 8 bit microcontrollers use vectored arbitration interrupts. Vectored arbitration means that when a specific interrupt occurs the interrupt handler automatically branches to an address associated with that interrupt. The servicing of interrupts in general is dictated by the status of the GIE (Global Interrupt Enable). GIE is cleared when an interrupt occurs and all interrupts are delayed until it is set.

1.4.1.6 Reset circuit and Watchdog tinier

Reset instruction start execution from starting address otherwise execution start from this address when it is powered up. The reset circuit activates for a fixed period (a few clock cycles) and then deactivates to let the program proceed from a default beginning address. On deactivation of the reset that succeed the processor activation, a program executes from start-up address. Reset can be activated either by external reset circuit that activates on power up or by software instruction or by a programmed timer known as watchdog timer. Watchdog timer is a timing device that resets the system after a predefined timeout this time is usually configured and the watchdog timer is activated within the first few clock cycles after power up. It has many applications. In many embedded systems reset by a watchdog timer is very essential because it helps in rescuing the system from program hangs. On restart program can function normally.

1.4.1.7 Memories

because it helps in rescuing the system from program hangs. On restart program can function normally.

Embedded system makes use of different types of memories based on their features. These can be viewed with following chart. These may be briefly explained based on their functionality (i) Internal RAM used for registers, temporary data and stack. (ii) Internal ROM/PROM/EPROM for application program (iii) External RAM for temporary data and stack (iv) Intemal cache available in case of some microcontroller or microprocessor. (v)EEPROM of flash memory for saving the results (vi) External ROM or PROM for embedding software used in non - microcontroller based systems. (vii) RAM memory buffers at ports. Caches for superscalar microprocessors.

buffers at ports. Caches for superscalar microprocessors. Figure 1.4: Various forms of system memory Different types

Figure 1.4: Various forms of system memory

Different types of memory devices in varying sizes are available for use as per requirement. These are (a) Masked ROM or EPROM of flash which stores the embedded software (ROM image). Masked ROM is for bulked manufacturing. (2)EPROM or EEPROM is used for testing and design stages. (3)EEPROM (5V form) is used to store the results during the system program run time. It is erased byte by byte and written during the system run. It is useful to store modifiable bytes for example run time system status, time and date. Flash is very useful when a processed image or voice is to be stored or a data set or system configuration data is to be stored which can be upgraded as and when required. In a flash new images after compressing and processing can be stored and the old one is erased from a sector in a single instruction cycle. In boot block flash a OPT sector is reserved to store once only at the time of first boot. It stores boot program and initial data or permanent system configuration data. This OTP sector can be used to store ROM image. (4)RAM is mostly used in SRAM form in a system. Advanced system uses RAM in the form of a DRAM, SDRAM, or RDRAM (5) Parameterised distributed RAM is used when I/O devices and subunits require a memory buffer. (6) Subunits like MAC which operates at fast speed uses separate blocks of RAM.

and subunits require a memory buffer. (6) Subunits like MAC which operates at fast speed uses

1.4.18 Input / Output units and buses

The system gets input from physical devices such as keypads/boards, sensors, transducer circuits etc. It gets the values by read operations at the port address. The system has output ports through which it sends output bytes to the real world. It sends the values to output by a write operation at the port address. In case of some devices a port may be used as both input as well as output port. One example is mobile phone which sends as well as receives signals. There are two types of I/O ports (i) Parallel port and (ii) Serial port. In a serial port, system gets a serial stream of bits at an input and sends the signal as bits through a modem. A serial port facilitates long distance communications and interconnections. A serial port may be serial URAT, a serial synchronous port or serial interfacing port. A system may get inputs from multiple channels or may have to send multiple output channels. A demultiplexer takes input from various channels and transfers the input to a selected channel. A multiplexer takes output from the system and sends it to another system. A system might have to be connected to a number of other devices and systems. For networking system there are different types of buses e.g., I2C, CAN, USB, ISA, EISA and PCI.

1.4.1.8 DAC/ADC

For automatic control and signal processing applications, a system must provide necessary interfacing circuit and software for Digital to Analog Conversion (DAC) unit and Analog to Digital Conversion (ADC) unit. A DAC operation is done with the help of a combination of PWM (Pulse Width Modulation) unit in the microcontroller and External Integrator chip. ADC operations are needed in systems for voice processing, Instrumentation, Data acquisition systems and automatic control.

1.5 Data and Address Bus concept

We refine the high level functional diagram to illustrate a typical bus configuration comprising the address, data and control lines

the high level functional diagram to illustrate a typical bus configuration comprising the address, data and
Address bus and data bus: According to computer architecture, a bus is defined as a
Address bus and data bus: According to computer architecture, a bus is defined as a

Address bus and data bus:

According to computer architecture, a bus is defined as a system that transfers data between hardware components of a computer or between two separate computers.Address bus and data bus: Initially, buses were made up using electrical wires, but now the

Initially, buses were made up using electrical wires, but now the term bus is used more broadly to identify any physical subsystem that provides equal functionality as the earlier electrical buses.components of a computer or between two separate computers. Computer buses can be parallel or serial

Computer buses can be parallel or serial and can be connected as multi drop, daisy chain or by switched hubs.equal functionality as the earlier electrical buses. System bus is a single bus that helps all

System bus is a single bus that helps all major components of a computer to communicate with each other.be connected as multi drop, daisy chain or by switched hubs. It is made up of

It is made up of an address bus, data bus and a control bus. The data bus carries the data to be stored, while address bus carries the location to where it should be stored.components of a computer to communicate with each other. Address Bus Address bus is a part

Address Bus

Address bus is a part of the computer system bus that is dedicated for specifying a physical address.the location to where it should be stored. Address Bus When the computer processor needs to

When the computer processor needs to read or write from or to the memory, it uses the address bus to specify the physical address of the individual memory block it needs to access (the actual data is sent along the data bus).bus that is dedicated for specifying a physical address. More correctly, when the processor wants to

More correctly, when the processor wants to write some data to the memory, it will assert the write signal, set the write address on the address bus and put the data on to the data bus.the physical address of the individual memory block it needs to access (the actual data is

the memory, it will assert the write signal, set the write address on the address bus

Similarly, when the processor wants to read some data residing in the memory, it will assert the read signal and set the read address on the address bus.After receiving this signal, the memory controller will get the data from the specific memory

After receiving this signal, the memory controller will get the data from the specific memory block (after checking the address bus to get the read address) and then it will place the data of the memory block on to the data bus.the read signal and set the read address on the address bus. The size of the

The size of the memory that can be addressed by the system determines the width of the data bus and vice versa. For example, if the width of the address bus is 32 bits, the system can address 232 memory blocks (that is equal to 4GB memory space, given that one block holds 1 byte of data).

Data Bus

A data bus simply carries data. Internal buses carry information within the processor, while external buses carry data between the processor and the memory.space, given that one block holds 1 byte of data). Data Bus Typically, the same data

Typically, the same data bus is used for both read/write operations. When it is a write operation, the processor will put the data (to be written) on to the data bus.buses carry data between the processor and the memory. When it is the read operation, the

When it is the read operation, the memory controller will get the data from the specific memory block and put it in to the data bus.will put the data (to be written) on to the data bus. What is the difference

What is the difference between Address Bus and Data Bus?

Data bus is bidirectional, while address bus is unidirectional. That means data travels in both directions but the addresses will travel in only one direction.What is the difference between Address Bus and Data Bus? The reason for this is that

The reason for this is that unlike the data, the address is always specified by the processor. The width of the data bus is determined by the size of the individual memory block, while the width of the address bus is determined by the size of the memory that should be addressed by the system.in both directions but the addresses will travel in only one direction. 1 . 6 Embedded

1.6 Embedded Processor and their types

determined by the size of the memory that should be addressed by the system. 1 .
1.7 Memory Types Data memory types: 1. Random Access Memory which can be read &

1.7 Memory Types

Data memory types:

1. Random Access Memory which can be read & written Static & Dynamic RAM

which can be read & written Static & Dynamic RAM 2. Read Only Memory which retains

2. Read Only Memory which retains data

PROM, EPROM, EEPROM, Flash& Dynamic RAM 2. Read Only Memory which retains data Programmable Logic: 1. Programmable Arrays PLDs,

Programmable Logic:

1. Programmable Arrays PLDs, PALs, GALs

Programmable Logic: 1. Programmable Arrays PLDs, PALs, GALs 2. Complex Programmable Devices CPLD, FPGA technology

2. Complex Programmable Devices

1. Programmable Arrays PLDs, PALs, GALs 2. Complex Programmable Devices CPLD, FPGA technology Summary of Characteristics

CPLD, FPGA technology

Summary of Characteristics

1. Programmable Arrays PLDs, PALs, GALs 2. Complex Programmable Devices CPLD, FPGA technology Summary of Characteristics

1.7.1 SRAM, DRAM, SDRAM, DDR SDRAM

There are many kinds of RAM and new ones are invented all the time. One of aims is to make RAM access as fast as possible in order to keep up with the increasing speed of CPUs.

SRAM (Static RAM) is the fastest form of RAM but also the most expensive. Due to its cost it is not used as main memory but rather for cache memory. Each bit requires a 6-transistor circuit.

DRAM (Dynamic RAM) is not as fast as SRAM but is cheaper and is used for main memory. Each bit uses a single capacitor and single transistor circuit. Since capacitors lose their charge, DRAM needs to be refreshed every few milliseconds. The memory system does this transparently. There are many implementations of DRAM, two well-known ones are SDRAM and DDR SDRAM.

SDRAM (Synchronous DRAM) is a form of DRAM that is synchronised with the clock of -side bus (FSB). As an example, if the system bus operates at 167Mhz over an 8-byte (64-bit) data bus , then an SDRAM module could transfer 167 x 8 ~ 1.3GB/sec.

DDR SDRAM (Double-Data Rate DRAM) is an optimisation of SDRAM that allows data to be transferred on both the rising edge and falling edge of a clock signal. Effectively doubling the amount of data that can be transferred in a period of time. For example a PC-3200 DDR- SDRAM module operating at 200Mhz can transfer 200 x 8 x 2 ~ 3.2GB/sec over an 8-byte (64-bit) data bus.

200 x 8 x 2 ~ 3.2GB/sec over an 8-byte (64-bit) data bus. 1.7.1.1 Static RAM

1.7.1.1 Static RAM (SRAM)

Static Random Access Memory Static: Data value is retained as long as V DD is present.

Data value is retained as long as V D D is present. sequential addresses) SRAM can

sequential addresses)

SRAM can be built using either: D-type latch or 6-transistor CMOS RAM cell

D-type Latch: Used for building CPU registers, etc. Derived from inverted S-R flip-flop

Inverted S-R flip-flop:

/S

/R

/R
/S /R

0

0

1

1

0

X

1

1

0

Q

0

1

/S /R 0 0 1 1 0 X 1 1 0 Q 0 1
inverted S-R flip-flop Inverted S-R flip-flop: /S /R 0 0 1 1 0 X 1 1
D-type latch D /S /R En When the Enable line is zero (En=0)
D-type latch
D
/S
/R
En
When the Enable line is zero (En=0)

Q

/Q

E D /S /R 0 0 1 1 0 1 1 1 1 0 1
E D /S /R 0 0 1 1 0 1 1 1 1 0 1

E

D

/S

/R

0

0

1

1

0

1

1

1

1

0

1

0

1

1

0

1

/S /R 0 0 1 1 0 1 1 1 1 0 1 0 1 1
/S /R 0 0 1 1 0 1 1 1 1 0 1 0 1 1

No Change

No Change

0

1

/S /R 0 0 1 1 0 1 1 1 1 0 1 0 1 1
/S /R 0 0 1 1 0 1 1 1 1 0 1 0 1 1
/S /R 0 0 1 1 0 1 1 1 1 0 1 0 1 1

/S = /R = 1 and the inverting SR flip-flop retains its previous value. When the enable line is high (En=1)0 1 1 0 1 No Change No Change 0 1 The value of data line

The value of data line D is latched into the flip-flop.its previous value. When the enable line is high (En=1) Each BIT would need 16 transistors

Each BIT would need 16 transistors (NAND gate = 4 transistors)

For large SRAM modules not very efficient.BIT would need 16 transistors (NAND gate = 4 transistors) 1-MB SRAM -> 8-Mb -> 128

1-MB SRAM -> 8-Mb -> 128 Million transistors= 4 transistors) For large SRAM modules not very efficient. 1.7.1.2 Transistor Cell (Cross Coupled Inverter)

1.7.1.2 Transistor Cell (Cross Coupled Inverter)

For larger SRAM modules the above circuit is not very efficient1.7.1.2 Transistor Cell (Cross Coupled Inverter) Transistor count per bit is too high TO READ: BIT

Transistor count per bit is too highlarger SRAM modules the above circuit is not very efficient TO READ: BIT lines are charged

is not very efficient Transistor count per bit is too high TO READ: BIT lines are

TO READ:

BIT lines are charged highvery efficient Transistor count per bit is too high TO READ: Enable line WL is pulled

Enable line WL is pulled high, switching access transistors M5 and M6 on`per bit is too high TO READ: BIT lines are charged high If value stored in

If value stored in /Q is 0, value is accessed through access transistor M5 on /BL.is too high TO READ: BIT lines are charged high Enable line WL is pulled high,

access transistors M5 and M6 on` If value stored in /Q is 0, value is accessed
If value stored in Q is 1, charged value of Bit line BL is pulled

If value stored in Q is 1, charged value of Bit line BL is pulled up to VDD.

TO WRITE:

Apply value to be stored to Bit lines BL and /BLcharged value of Bit line BL is pulled up to VDD. TO WRITE: Enable line WL

Enable line WL is triggered and input value is latched into storage cellTO WRITE: Apply value to be stored to Bit lines BL and /BL BIT line drivers

BIT line drivers must be stronger than SRAM transistor cell to override previous valuesWL is triggered and input value is latched into storage cell While Enable line is held

While Enable line is held low, the inverters retain the previous value could use tri-state WE line on BIT to drive into specific state.

Transistor count per bit is only 6 + (line drivers & sense logic)

1.7.1.3 Addressed SRAM

Can view RAM as N-bit by M-word black box:6 + (line drivers & sense logic) 1.7.1.3 Addressed SRAM N input lines D I N

N input lines D I N

N

input lines

D

IN

N output lines D O U T

N

output lines

D

OUT

A address lines (2 A = M) A

A

address lines (2 A = M)

A

W E write enable line WE

W

E write enable line

WE

1.7.1.4 Single SRAM Bit

Data IN DI

Write W

Address A

Line

D Q EN
D
Q
EN

DO

Data OUT

When A = 0,

Latch Enable is off.DI Write W Address A Line D Q EN DO Data OUT When A = 0,

Data cannot be written into the D-type latchA Line D Q EN DO Data OUT When A = 0, Latch Enable is off.

D O U T = 0. OUT = 0.

When A = 1

Latch is Enabledwritten into the D-type latch D O U T = 0. When A = 1 If

If W = 1 (Data-Write) Data at D I N can be written into the D-type latch IN can be written into the D-type latch

Data at D I N can be written into the D-type latch Output gate is enabled

Output gate is enabledData at D I N can be written into the D-type latch IF W = 0

IF W = 0 New value on D I N is not stored. Output gate is enabled. IN is not stored. Output gate is enabled.

value on D I N is not stored. Output gate is enabled. Not very efficient since
value on D I N is not stored. Output gate is enabled. Not very efficient since

Not very efficient since 1-bit address line can access 2 memory locations.value on D I N is not stored. Output gate is enabled. This memory is 1-bit

This memory is 1-bit X 1-word RAMgate is enabled. Not very efficient since 1-bit address line can access 2 memory locations. Stores

Stores one 1-bit data valueis enabled. Not very efficient since 1-bit address line can access 2 memory locations. This memory

since 1-bit address line can access 2 memory locations. This memory is 1-bit X 1-word RAM

A

W

DI Flip Flop Out

DO

A W DI Flip Flop Out DO
A W DI Flip Flop Out DO
A W DI Flip Flop Out DO

0

0

0

0

1

1

1

1

0

0

Q(t-1)

0

0

1

Q(t-1)

0

1

0

Q(t-1)

0

1

1

Q(t-1)

0

0

0

Q(t)

Q(t)

0

1

Q(t)

Q(t)

1

0

0

0

1

1

1

1

1 1 Q(t-1) 0 0 0 Q(t) Q(t) 0 1 Q(t) Q(t) 1 0 0 0
1 1 Q(t-1) 0 0 0 Q(t) Q(t) 0 1 Q(t) Q(t) 1 0 0 0
1 1 Q(t-1) 0 0 0 Q(t) Q(t) 0 1 Q(t) Q(t) 1 0 0 0
1 1 Q(t-1) 0 0 0 Q(t) Q(t) 0 1 Q(t) Q(t) 1 0 0 0

1.7.1.5 1-bit X 2-word SRAM

DI

W

A1

DI

W

A

1-Bit Memory Cell

0

X 2-word SRAM DI W A1 DI W A 1-Bit Memory Cell 0 DI W A
X 2-word SRAM DI W A1 DI W A 1-Bit Memory Cell 0 DI W A

DI

WDI A 1-Bit Memory Cell 1

ADI W 1-Bit Memory Cell 1

1-Bit Memory Cell

1

When address bit AI = 0

DI W A 1-Bit Memory Cell 1 When address bit AI = 0 Cell1 is disabled

Cell1 is disabled and Cell0 is enabled IF W = 1 : Value of D IN is written to cell0

enabled IF W = 1 : Value of D I N is written to cell0 IF

IF W = 0 : Data out is Cell0 OR 0enabled IF W = 1 : Value of D I N is written to cell0 When

When address bit AI = 1

Cell0 is disabled and Cell1 is enabled IF W = 1 : Value of D I N is written to cell1 IF W = 0 : Data out is Cell1 IN is written to cell1 IF W = 0 : Data out is Cell1 OR 0

Only 1 cell can be active at one timeN is written to cell1 IF W = 0 : Data out is Cell1 OR 0

Output line is always driven by one cell Important for shared busto cell1 IF W = 0 : Data out is Cell1 OR 0 Only 1 cell

active at one time Output line is always driven by one cell Important for shared bus
active at one time Output line is always driven by one cell Important for shared bus
active at one time Output line is always driven by one cell Important for shared bus

1.7.1.6 4-bit X 16-word SRAM

active at one time Output line is always driven by one cell Important for shared bus

DataOut

active at one time Output line is always driven by one cell Important for shared bus
DI1 DI2 DI3 DI4 DI A4 A a 0 . DO A3 . . A2
DI1
DI2
DI3
DI4
DI
A4
A
a
0
.
DO
A3
.
.
A2
.
.
A1
.
a
15
CS
Chip Select
W => to all cells
DO1
DO2
DO3
DO4

When CS = 1 AND A4 A3 A2 A1 = 0000 Address decoder decodes A4-A1 to

= 1 AND A4 A3 A2 A1 = 0000 Address decoder decodes A4-A1 to 1000000000000000 (a

1000000000000000 (a 0 = 1, a 1 -a 1 5 = 0 0 = 1, a 1 -a 15 = 0

Data at DI1 DI2 DI3 DI4 is written to address 0 when W = 1to 1000000000000000 (a 0 = 1, a 1 -a 1 5 = 0 If W =

If W = 0, No new data is stored and address0 drives the output bus0 Data at DI1 DI2 DI3 DI4 is written to address 0 when W = 1

Contents of memory address 0 appear at output0, No new data is stored and address0 drives the output bus Address decoder maps input

Address decoder maps input address bits to row control signals

Should only set one bit for every possible inputdecoder maps input address bits to row control signals 2 A states where A is the

2 A states where A is the number of address lines A states where A is the number of address lines

The CS (chip select) line allows the memory to be doubled with only one inverter [+ OR gates].

1.7.1.7 Tri-State Outputs:

In previous examples, one location is enabled during each operation which can drive the output

In previous examples, one location is enabled during each operation which can drive the output bus.

If RAM is on shared bus, the RAM cannot be allowed to drive the bus

If RAM is on shared bus, the RAM cannot be allowed to drive the bus at all times

Must have method of removing RAM from busIf RAM is on shared bus, the RAM cannot be allowed to drive the bus at

Solution is to use Tri-State logicIf RAM is on shared bus, the RAM cannot be allowed to drive the bus at

be allowed to drive the bus at all times Must have method of removing RAM from

A1

A2

A3

A4

A5

A1 DI0 .DI3 A2 A3 A4 CS DO0 .DO3 A1 DI0 DI3 A2 A3 A4
A1
DI0
.DI3
A2
A3
A4
CS
DO0
.DO3
A1
DI0
DI3
A2
A3
A4
CS
DO0
DO3

Data Bus

Outputs from each cell are tri-state outputs.DO0 .DO3 A1 DI0 DI3 A2 A3 A4 CS DO0 DO3 Data Bus When not active

When not active the outputs are in high impedance.DO3 Data Bus Outputs from each cell are tri-state outputs. Can either use CS line to

Can either use CS line to control when Hi- controls the output OEoutputs. When not active the outputs are in high impedance. Allows both other RAM cells and

Allows both other RAM cells and other devices to control data bususe CS line to control when Hi- controls the output OE 1.7.2 Dynamic RAM (DRAM) SRAM

both other RAM cells and other devices to control data bus 1.7.2 Dynamic RAM (DRAM) SRAM

1.7.2 Dynamic RAM (DRAM)

SRAM requires a number of transistors per bitother devices to control data bus 1.7.2 Dynamic RAM (DRAM) Difficult to cost-effectively scale for larger

Difficult to cost-effectively scale for larger memoriesRAM (DRAM) SRAM requires a number of transistors per bit DRAM utilises MOSFET capacitance to store

DRAM utilises MOSFET capacitance to store data bitbit Difficult to cost-effectively scale for larger memories Transistor per bit cost is approx. 1 X

Transistor per bit cost is approx. 1memories DRAM utilises MOSFET capacitance to store data bit X Row select Y Storage Cell Si0

X

Row select Y Storage Cell
Row select
Y
Storage
Cell

Si0 2 insulates gate and substrate 2 insulates gate and substrate

Data I/O

Creating dielectric capacitor between gate and substrateCell Si0 2 insulates gate and substrate Data I/O Data bit is stored in this capacitance

Data bit is stored in this capacitanceI/O Creating dielectric capacitor between gate and substrate Each bit now only requires 1 MOSFET per

Each bit now only requires 1 MOSFET per bit.gate and substrate Data bit is stored in this capacitance However the charge stored in cell

However the charge stored in cell dissipates over time and must be recharged over time to avoid corruptioncapacitor between gate and substrate Data bit is stored in this capacitance Each bit now only

MOSFET per bit. However the charge stored in cell dissipates over time and must be recharged

DRAM Refresh Must read data bit and write value back to cell.

Refresh Must read data bit and write value back to cell. JEDEC standardises DRAM row refreshes

JEDEC standardises DRAM row refreshes at least every 64 ms.

JEDEC standardises DRAM row refreshes at least every 64 ms. All bits in row must be
JEDEC standardises DRAM row refreshes at least every 64 ms. All bits in row must be

All bits in row must be refreshed. Dedicated hardware control DRAM refreshJEDEC standardises DRAM row refreshes at least every 64 ms.

must be refreshed. Dedicated hardware control DRAM refresh Refresh is transparent to user Above 64 Kbits,

Refresh is transparent to usermust be refreshed. Dedicated hardware control DRAM refresh Above 64 Kbits, DRAM more economic than SRAM

Above 64 Kbits, DRAM more economic than SRAM logic Even with refresh.

Kbits, DRAM more economic than SRAM logic Even with refresh. X Rowselect Y Storage Cell Data

X

Rowselect Y Storage Cell
Rowselect
Y
Storage
Cell

Data I/O

Write Operation

X

0

Y

X

X 0 Y X Data I/O C X - 0

Data I/O

C

X

-

X 0 Y X Data I/O C X - 0

0

X 0 Y X Data I/O C X - 0 X - 0 1 1 X

X

-

0

1

1

X - 0 1 1

X 0

1 1

1 1

X 0 Y X Data I/O C X - 0 X - 0 1 1 X

Read Operation

X Y Data I/O C 0 X X C X 0 X C 1 1

X

Y

Data I/O

C

0

X

X

C

X

0

X

C

1

1

0

0

X Y Data I/O C 0 X X C X 0 X C 1 1 0
X Y Data I/O C 0 X X C X 0 X C 1 1 0
X Y Data I/O C 0 X X C X 0 X C 1 1 0
X Y Data I/O C 0 X X C X 0 X C 1 1 0
X Y Data I/O C 0 X X C X 0 X C 1 1 0
X Y Data I/O C 0 X X C X 0 X C 1 1 0
X Y Data I/O C 0 X X C X 0 X C 1 1 0

1

1 1

1

1.7. 2.1 DRAM Organization

1 0 0 1 1 1 1 1.7. 2.1 DRAM Organization Matrix stores n 1-bit words
1 0 0 1 1 1 1 1.7. 2.1 DRAM Organization Matrix stores n 1-bit words

Matrix stores n 1-bit words N is determined by the number of address lines available

N is determined by the number of address lines available Each matrix is parallelised to create

Each matrix is parallelised to create word size memories i.e. : 8 parallel 4Kx1-bit DRAM matrices creates an 4K * 8-bit RAM module

i.e. : 8 parallel 4Kx1-bit DRAM matrices creates an 4K * 8-bit RAM module Example An

Example An 8x8 array forms a 64 x 1 dynamic RAM

i.e. : 8 parallel 4Kx1-bit DRAM matrices creates an 4K * 8-bit RAM module Example An
Column Address (CAS)
Column Address (CAS)

The row and column select logic are comprised of address decoders.Column Address (CAS) 8-rows and 8-columns need 3-address bits each. Above block is 64x1-bit DRAM Diagram

8-rows and 8-columns need 3-address bits each.and column select logic are comprised of address decoders. Above block is 64x1-bit DRAM Diagram omits

Above block is 64x1-bit DRAMdecoders. 8-rows and 8-columns need 3-address bits each. Diagram omits but matrix has 1 data I/O

Diagram omits but matrix has 1 data I/O line.need 3-address bits each. Above block is 64x1-bit DRAM Row and Column address control which bit

Row and Column address control which bit is active64x1-bit DRAM Diagram omits but matrix has 1 data I/O line. 1.7.3 ROM, PROM, EPROM, EEPROM,

1.7.3 ROM, PROM, EPROM, EEPROM, Flash

In addition to RAM, they are also a range of other semi-conductor memories that retain their contents when the power supply is switched off.

ROM (Read Only Memory) is a form of semi-conductor that can be written to once, typically -up program (so called firmware) that a computer executes when powered on, although it has now fallen out-of-favour to more flexible memories that support occasional writes. ROM is still used in systems with fixed functionalities, e.g. controllers in cars, household appliances etc.

PROM (Programmable ROM) is like ROM but allows end-users to write their own programs and data. It requires a special PROM writing equipment. Note: users can only write-once to PROM.

EPROM (Erasable PROM). With EPROM we can erase (using strong ultra-violet light) the contents of the chip and rewrite it with new contents, typically several thousand times. It is

with new contents, typically several thousand times. It is this firmware, the BIOS (Basic I/O System).
with new contents, typically several thousand times. It is this firmware, the BIOS (Basic I/O System).

this firmware, the BIOS (Basic I/O System). Other systems use Open Firmware. Intel-based Macs use EFI (Extensible Firmware Interface).

the BIOS (Basic I/O System). Other systems use Open Firmware. Intel-based Macs use EFI (Extensible Firmware

EEPROM (Electrically Erasable PROM). As the name implies the contents of EEPROMs are erased electrically. EEPROMSs are also limited to the number of erase-writes that can be performed (e.g., 100,000) but support updates (erase-writes) to individual bytes whereas EPROM updates the whole memory and only supports around 10,000 erase-write cycles.

FLASH memory is a cheaper form of EEPROM where updates (erase-writes) can only be performed on blocks of memory, not on individual bytes. Flash memories are found in USB sticks, flash cards and typically range in size from 32M to 2GB. The number of erase/write cycles to a block is typically several hundred thousand before the block can no longer be written.

Characteristics of the various memory types

Erase Max Erase Cost (per Type Volatile? Writeable? Speed Size Cycles Byte) SRAM Yes Yes
Erase
Max Erase
Cost (per
Type
Volatile?
Writeable?
Speed
Size
Cycles
Byte)
SRAM
Yes
Yes
Byte
Unlimited
Expensive
Fast
DRAM
Yes
Yes
Byte
Unlimited
Moderate
Moderate
Masked
No
No
n/a
n/a
Inexpensive
Fast
ROM
PROM
No
Once, with a
device
programmer
n/a
n/a
Moderate
Fast
Yes, with a
device
programmer
Limited
Entire
EPROM
No
(consult
Moderate
Fast
Chip
datasheet)
Limited
EEPROM
No
Yes
Byte
(consult
Expensive
datasheet)
Fast to read,
slow to
erase/write
Limited
Flash
No
Yes
Sector
(consult
Moderate
datasheet)
Fast to read,
slow to
erase/write
Expensive
NVRAM
No
Yes
Byte
Unlimited
(SRAM +
Fast
battery)
datasheet) Fast to read, slow to erase/write Expensive NVRAM No Yes Byte Unlimited (SRAM + Fast

1.8 Overview of design process of embedded systems

Figure1.3 shows a high level flow through the development process and identifies the major elements of the development life cycle.

identifies the major elements of the development life cycle. Figure 1. Embedded system life cycle The

Figure 1. Embedded system life cycle

The traditional design approach has been traverse the two sides of the accompanying diagram

separately, that is,

cycle The traditional design approach has been traverse the two sides of the accompanying diagram separately,

Design the hardware componentsDesign the software components. Bring the two together. Spend time testing and Debugging the system.

Design the software components.Design the hardware components Bring the two together. Spend time testing and Debugging the system. The

Bring the two together.the hardware components Design the software components. Spend time testing and Debugging the system. The major

Spend time testing andDesign the software components. Bring the two together. Debugging the system. The major areas of the

Debugging the system.components. Bring the two together. Spend time testing and The major areas of the design process

The major areas of the design process are

Ensuring a sound software and hardware specification.the system. The major areas of the design process are Formulating the architecture for the system

Formulating the architecture for the system to be designed.are Ensuring a sound software and hardware specification. Partitioning the h/w and s/w. Providing an iterative

Partitioning the h/w and s/w.Formulating the architecture for the system to be designed. Providing an iterative approach to the design

Providing an iterative approach to the design of h/w and s/wfor the system to be designed. Partitioning the h/w and s/w. 1.8.1 Requirements Informal descriptions gathered

1.8.1 Requirements

Informal descriptions gathered from the customer are known as requirements. The requirements are refined into a specification to begin the designing of the system architecture. Requirements can be functional or non-functional requirements. Functional requirements need output as a function of input. Non-functional requirements includes performance, cost, physical size, weight, and power consumption. Performance may be a combination of soft performance metrics such as approximate time to perform a user-level function and hard deadlines by which a particular operation must be completed. Cost includes the manufacturing, nonrecurring engineering (NRE) and other costs of designing the system. Physical size and weight are the physical aspects of the final system. These can vary greatly depending upon the application. Power consumption can be specified in the requirements stage in terms of battery life.

depending upon the application. Power consumption can be specified in the requirements stage in terms of
depending upon the application. Power consumption can be specified in the requirements stage in terms of

1.8.2 Specification

Requirements gathered is refined into a specification. Specification serves as the contract between the customers and the architects. Specification is essential to create working systems with a minimum of designer effort. It must be specific, understandable and accurately reflect

It must be specific, understandable and accurately reflect Example: Considering the example of the GPS system,

Example:

Considering the example of the GPS system, the specification would include details for several components:

Data received from the GPS satellite constellationspecification would include details for several components: Map data User interface Operations that must be performed

Map dataData received from the GPS satellite constellation User interface Operations that must be performed to satisfy

User interfaceData received from the GPS satellite constellation Map data Operations that must be performed to satisfy

Operations that must be performed to satisfy customer requestsfrom the GPS satellite constellation Map data User interface Background actions 1.8.3 Architecture Design The

Background actionsthat must be performed to satisfy customer requests 1.8.3 Architecture Design The specification describes only

1.8.3 Architecture Design

The specification describes only the functions of the system. Implementation of the system is described by the Architecture. The architecture is a plan for the overall structure of the system. It will be used later to design the components. The architecture will be illustrated using block diagrams as shown below.

Example:

be illustrated using block diagrams as shown below. Example: This block diagram (figure 3) is an
be illustrated using block diagrams as shown below. Example: This block diagram (figure 3) is an
be illustrated using block diagrams as shown below. Example: This block diagram (figure 3) is an

This block diagram (figure 3) is an initial architecture that is not based either on hardware or on software but combination of both. This block diagram explains about GPS navigating system where GPS receiver gets current position and the destination is taken from user, digital map for source to destination is found from database and displayed by the renderer. The system block diagram may be refined into two block diagrams - hardware and software

and displayed by the renderer. The system block diagram may be refined into two block diagrams

1.3.1 Hardware block diagram:

1.3.1 Hardware block diagram: Hardware consists of one central CPU surrounded by memory and I/O devices.
1.3.1 Hardware block diagram: Hardware consists of one central CPU surrounded by memory and I/O devices.

Hardware consists of one central CPU surrounded by memory and I/O devices. We have chosen to use two memories that is frame buffer for the pixels to be displayed and separate program/data memory for general use by the CPU. The GPS receiver is used to get the GPS coordinates, and the panel I/O is used to get the destination from the user.

1.3.2 Software block diagram

the destination from the user. 1.3.2 Software block diagram The software block diagram closely follows the
the destination from the user. 1.3.2 Software block diagram The software block diagram closely follows the

The software block diagram closely follows the system block diagram. We have added a timer to control when we read the buttons on the user interface and render data onto the screen.

To have a truly complete architectural description, we require more details, such as where units in the software block diagram will be executed in the hardware block diagram and when the operations will be performed in time.

Architectural descriptions must be designed to satisfy the functional and non-functional requirements. Not only must all the required functions be present, but we must meet cost, speed, power and other non- functional constraints. Starting out with a system architecture and refining that to hardware and software architectures is one good way to ensure that we meet all specifications. We can concentrate on the functional elements in the system block diagram, and

to ensure that we meet all specifications. We can concentrate on the functional elements in the

then consider the non- functional constraints when creating the hardware and software architectures.

How do we know that our hardware and software architectures in fact meet constraints on speed, cost, and so on?

Estimate the properties of the components in the block diagrams (Example: search and rendering functions in the moving map system)in fact meet constraints on speed, cost, and so on? Accurate estimation derives in part from

Accurate estimation derives in part from experience, both general design and particular experience.search and rendering functions in the moving map system) All the non- functional constraints are estimated.

All the non- functional constraints are estimated. If the decisions are based on bad data, those results will show up only during the final phases of design.experience, both general design and particular experience. 1.4 Hardware and Software components The architectural

1.4 Hardware and Software components

The architectural description tells us what components we need. The component design effort builds those components in conformance to the architecture and specification. The components in general includes both hardware and software modules. Some of the components will be ready-made (example: CPU, memory chips).

Example:

In the moving map, GPS receiver is a predesigned standard hardware component. Topographic software is a standard software module which uses standard routines to access the database. Printed circuit board are the components which needs to be designed. Lots of custom programming is required.

When creating these embedded software modules, ensure the system runs properly in real time and that it does not take up more memory space than allowed. The power consumption of the moving map software example is particularly important. You may need to be very careful about how you read and write memory to minimize power. For example, memory transactions must be carefully planned to avoid reading the same data several times, since memory accesses are a major source of power consumption.

1.8.5 System integration

After the components are built, they are integrated. Bugs are typically found during the system integration. Good planning can help us to find the bugs quickly. By debugging a few modules at a time, simple bugs can be uncovered. By fixing the simple bugs early, more complex or obscure bugs can be uncovered. System integration is difficult because it usually uncovers problems. The debugging facilities for embedded systems are usually much more limited than the desktop systems. Careful attention is needed to insert appropriate debugging facilities during design which can help to ease system integration problems.

1.9 Programming languages and tools for embedded design

during design which can help to ease system integration problems. 1.9 Programming languages and tools for

The software is the most important aspect of the embedded system, hardware perform the task as per software instruction. It is actually the brain of the system. An Embedded system processor and the system need software that is specific to a given application of that system. The processor of the system processes instructions coded and data. In the final stage these are placed in the memory (ROM) for all the tasks that have to be executed. Assembly as well as high level language like C, C++, and Java etc. are used for software development. Challenging in designing and implementing embedded software comes from reliability, performance and cost. Reliability expectation brings greater responsibility to eliminate bugs and fault tolerant as many embedded system has to run 24 hours a day, a week and 365 days in a year. Sometime rebooting is not possible, so good programming and thorough testing is must for embedded software development Performance issue may come from different considerations, such as proper multitasking and scheduling any considerably effect the performance. At the same time systems using sensors depends on how accurately sensor value is converted into real world value. Input/output device may effect speed, complexity and cost. For better productivity sometime it may be needed to program directly in assembly in place of high level language. Embedded consumer products as produced in large so it is possible to keep in minimal production cost and no modification is performed once it start produced.

1.9.1Creation of ROM image

In the final stage processed codes and instructions are placed in ROM which is called creation of ROM image. All executions of tasks are carried out from there. A brief description of creation of ROM image in assembly and High level language is described below There are different stages in converting an assembly language program into machine implementable software file and then finally obtaining ROM image file. These steps are explained with the following figure 1.9.

In the assembling step assembler translate assembly software into machine codes. Next in linking phase linker links no of codes with other assembled codes. There are certain codes having certain beginning address. Linking produces the final binary file by linking all these. The linked file in a computer is commonly known as .exe file. In the third phase reallocation of codes is done by placing it in physical memory by a program called loader. Loader find out appropriate position in RAM that is ready to run. Finally in locating phase ROM image is permanently placed in actually available address of ROM. In embedded system since there is only one program so designer has to define the available address to load and create files for

system since there is only one program so designer has to define the available address to

permanent location. The locator locates the I/O task and hardware device driver codes at unchanged address as port address of these are fixed. In the last phase device programmer takes the ROM image and is burnt in to the PROM or EPROM.

takes the ROM image and is burnt in to the PROM or EPROM. Figure 1.9.1 :

Figure 1.9.1 : Process of converting assembly language program into ROM image

In the conversion process of a high level language like C to ROM image file first compiler generates the object codes. As per processor instruction compiler assemble the codes and then code optimization is carried out by code optimizer Optimization is carried out before linking. After compilation linker links codes including various standard codes like printf, scanf and device driver codes. After linking subsequent steps for creating ROM image is same as explained for assembly language

ROM image is same as explained for assembly language Figure 1.9.2 :Proeess of converting C Program

Figure 1.9.2 :Proeess of converting C Program into ROM image

A comparative view of build and load process of desktop and embedded application can be

C Program into ROM image A comparative view of build and load process of desktop and

depicted with following figures 1.9.3 and 1.9.4

depicted with following figures 1.9.3 and 1.9.4 Figure 1.9.3: The build and load process for desktop

Figure 1.9.3: The build and load process for desktop application program

The build and load process for desktop application program Fig 1.9.4: The build and load process

Fig 1.9.4: The build and load process for embedded application program

1.9. 2 Software for embedded system device driver, multiple tasks, RTOS

There may be a number of physical devices attached with embedded systems. Device driver is the program needed to drive these devices. A driver uses hardware status flag and control register. It controls three functions (a)Initializing by placing appropriate bits at the control register.(b)Calling Interrupt service routine(ISR) for setting status flag (c)Resetting the status flag after interrupt service. Device driver coding is made using operating system functions such that underlying hardware is hidden. Device management software module provides codes for detecting the presence of devices. In designing the software for this category two types of devices are considered -Physical and Virtual. Physical devices includes Keyboard, Printers, display matrix etc. Virtual device could be a file which may be used for reading and writing the stream of bytes. Operating system has modules for insertion of both device driver and device management module. Sometime embedded systems has to control multiple devices for scheduling of multiple functions (task). To implement this embedded system must have a multitasking operating system above application level which is generally a Real Time Operating System (RTOS). In

have a multitasking operating system above application level which is generally a Real Time Operating System

multitasking OS each process (task) has different memory allocation of its own and task has one or more than one procedures for a specific job [12]. A task may share memory (data) with other task. Processor may process different task separately or concurrently. An OS or RTOS has a kernel which is responsible for scheduling the transition of task from ready state to running state. Kernel may select a task for processing based on its priority value out of many ready state tasks. Calling ISR kernel may temporarily halt a running task and allow another task to run and resume the same after completion of new task. An embedded system in multitasking environment always need not require an RTOS. An RTOS is required in a multitasking environment when real time constraints becomes must (i.e. task has to be completed in defined deadline). An RTOS main functions includes Real time task scheduling, Interrupt latency control, Time allocation and de-allocation to attain efficiency, predictable timing behaviour, priority management and time slicing of process soft real time. Hard real time strictly adhere task schedule whereas in soft real time precedence and sequence of task is defined.

soft real time precedence and sequence of task is defined. 1.9.3 Tools for designing embedded software

1.9.3 Tools for designing embedded software Different software tools for assembly language programming, high level language programming, RTOS, debugging and integrated tools can be summarized as given below. Editor: It enables users to write codes for high level as well as assembly language in computer. Different features like addition, deletion, copy, insertion are made available for easy writing. It saves the content in a file with user defined or default extension. User can make necessary modification of saved files as and when required. Compiler: It takes the input of whole high level source code and converts it to machine readable object code. It may include functions, library routines etc. for compilation. Interpreter: It converts high level codes to machine readable form line by line. Like compiler it may also include functions, library routines etc. for conversion. Assembler: It is used for conversion of assembly language programs to executable binary files. It creates the list file which has address, source code and hexadecimal object codes. It is processor specific. Cross assembler: Cross assembler assembles the assembly code of target processor as assembly code of the processor of the PC used in the system development. Later it provides the object codes for the target processor. These will be the final codes used for the developed system.

Later it provides the object codes for the target processor. These will be the final codes

Simulator: It is the program which can simulate all the functions of an embedded system circuit including additional memory and peripherals. It is independent of a particular target system. RTOS: Explained in above Stethoscope: This program is used to keep track of dynamic change in program variables and parameters. It can demonstrate the sequences of multiple processes, tasks, threads that execute and keeps entire time history. Trace scope: It traces the change in module according to time. Accordingly list of actions to be initiated at desired time is also prepared. Integrated Development Environment (IDE): Total software and hardware environment consist of simulator, compiler, assembler, cross assembler, logic analyser EPROM/EBPROM, application codes, burners defines the integrated development environment of the system. Locator: Locator program uses cross-assembler output and a memory allocation map and provides locator program output.

Locator: Locator program uses cross-assembler output and a memory allocation map and provides locator program output.

Unit -II Embedded Processor Architecture

2.1 CISC Vs RISC design philosophy

Processor Architecture 2.1 CISC Vs RISC design philosophy hitectural designs of CPU are RISC (Reduced instruction

hitectural designs of CPU are RISC (Reduced instruction set computing) and CISC (Complex instruction set computing). CISC has the ability to execute addressing modes or multi-step operations within one instruction set. It is the design of the CPU where one instruction performs many low-level operations. For example, memory storage, an arithmetic operation and loading from memory. RISC is a CPU design strategy based on the insight that simplified instruction set gives higher performance when combined with a microprocessor architecture which has the ability to execute the instructions by using some microprocessor cycles per instruction.

.
.

Fig 2.1: CISC Vs RISC

We discusses about the RISC and CISC architecture with suitable diagrams.

1. Hardware of the Intel is termed as Complex Instruction Set Computer (CISC)

2. Apple hardware is Reduced Instruction Set Computer (RISC).

What is RISC and CISC Architectures?

Set Computer (CISC) 2. Apple hardware is Reduced Instruction Set Computer (RISC). What is RISC and

UNIT -2

EMBEDDED PROCESSOR ARCHITECTURE

Instruction Set Architecture

Instructin sst can bs dsfnsd as ths cimmunicatin intsrfacs bstwssn ths pricsssir and ths prigrammsr. Evsry pricsssir has its iwn instructin sst imppsmsntsd in ths hardwars ti sxscuts instructins such as mivs, add ir muptppy data in a dsfnits way. Prigrammsrs can sithsr uss any high psvsp panguags such as C, C++, Java stc. ir asssmbpy panguags ti writs ths prigram. Accirdingpy, a cimpipsr ir asssmbpsr can bs ussd ti transpats ths prigram inti machins undsrstandabps panguags fippiwing ths pricsssir instructin sst. Thsrs ars twi cpassic architscturss if instructin sst imppsmsntatin, ths cimppsx instructin sst cimputsr (CISC) and ths rsducsd instructin sst cimputsr (RISC). Each has its iwn advantagss and disadvantagss. Ths CISC architscturs has mirs cimppsxity in ths hardwars itsspf whips RISC architscturs ifsrs mirs cimppsxity ti ths sifwars. Ths fsaturss if sach architscturs ars summarizsd as bspiw.

Features of Complex Instruction Set Computer (CISC):

Mist if ths instructins ars cimppsx in typs.

Instructins rsquirs muptpps cpick cycpss fir sxscutin.

Mirs addrsssing midss ars avaipabps in ths instructin sst.

Fswsr wirking rsgistsrs and mirs frsqusnt msmiry accsss.

Liad and Stirs ipsratins ars incirpiratsd in instructins.

High cids dsnsity is achisvsd bscauss if avaipabipity if muptfunctinap instructins.

Pipspins imppsmsntatin is diffcupt.

Mirs cimppsxity is givsn ti ths hardwars dssign.

Features of Reduced Instruction Set Computer (RISC):

Mist if ths instructins ars simpps in naturs.

App ths instructins ars sxscutsd in singps cpick duratin.

Ths addrsssing midss avaipabps ars fswsr than in cass if CISC.

Instructin sst has ssparats Liad/Stirs architscturs.

Highsr numbsr if wirking rsgistsrs si psss frsqusnt msmiry accsss.

Mist if ths data transfsr happsns frim rsgistsr ti rsgistsr.

Largs cids sizs cimparsd ti CISC architscturs.

Psrfirmancs if RISC architscturs is apways bstsr than CISC architscturs.

Pipspins imppsmsntatin is sasisr cimparsd ti CISC.

Mirs cimppsxity is ifsrsd ti ths cimpipsr dssign.

Memory Block

Ths msmiry bpick cinsists if prigram and data msmiry. ROM is ussd as ths prigram msmiry and RAM is ussd as ths data msmiry. Thsrs ars twi msmiry architscturss: Harvard and Vin- Nsumann. In Harvard architscturs, ths prigram and data msmiriss ars ssgrsgatsd with

ssparats addrsss and data bus drawn ti sach. Si thsrs can bs parappsp accsss ti bith and psrfirmancs if ths systsm can bs imprivsd at ths cist if hardwars cimppsxity. On ths ithsr- hand, ths Vin-Nsumann architscturs has ins unifsd msmiry ussd fir bith prigram and data. Ths systsm is cimparatvspy spiwsr, but ths dssign imppsmsntatin is simpps and cist sfsctvs fir an smbsddsd systsm. Variius ROM and RAM dsvicss ars ussd in smbsddsd systsms bassd in ths apppicatins.

ars ussd in smbsddsd systsms bassd in ths apppicatins. ARM Architecture ARM cirss ars dssignsd spscifcappy

ARM Architecture

ARM cirss ars dssignsd spscifcappy fir smbsddsd systsms. Ths nssds if smbsddsd systsms can bs satsfsd inpy if fsaturss if RISC and CISC ars cinsidsrsd tigsthsr fir pricsssir dssign. Si ARM architscturs is nit a purs RISC architscturs. It has a bpsnd if bith RISC and CISC fsaturss.

Tabps 1.1. ARM Architscturs Fsaturss and Bsnsfts

Fsaturss

Bsnsfts ti smbsddsd systsm

High Psrfirmancs

Ensurss ths systsm has a fast rsspinss

Liw piwsr cinsumptin

Makss ths systsm mirs snsrgy sfcisnt

Liw sipicin arsa

Rsducss ths sizs and apsi cinsumss psss piwsr

High Cids dsnsity

Hspps smbsddsd systsm ti havs psss msmiry fiitprint

Liad/stirs architscturs

Ussd ti piad data frim ths msmiry ti ths ARM CPU rsgistsr ir stirs data frim ths CPU rsgistsr ti ths msmiry; snabpss ths msmiry accsss whsn rsquirsd

Rsgistsr bank with pargs numbsr if wirking rsgistsrs

Rsquirsd ti psrfirm mist if ths ipsratins within ths CPU and prividss fastsr cintsxt switch in a mupttasking apppicatins

prividss fastsr cintsxt switch in a mupttasking apppicatins A Basic architecture of the ARM7core ARM 7,

A Basic architecture of the ARM7core

ARM 7, ths basic architscturs if ARM ssriss if cirss, is intriducsd hsrs in this ssctin. A brisf intriductin abiut sach functinap bpick if ths architscturs if ARM7 cirs shiwn in Figurs.1.2 is prsssntsd bspiw.

Ths Rsgistsr Bank has sixtssn gsnsrap purpiss rsgistsrs (R0-R15) and a currsnt prigram status rsgistsr (CPSR) which ars accsssibps by ussr apppicatins. In additin ti that, it has twsnty numbsrs if banksd rsgistsrs spscifcappy ussd fir difsrsnt ipsratng midss if ARM cirs. Thsss ars invisibps ti ussr apppicatins. Ths rsgistsr bank has twi rsad pirts ti rsad ipsrand1 and ipsrand2 and ins writs pirt ti writs back ths rssupt if ipsratin ti ths any rsgistsr spscifsd in

ths instructin. It has an additinap bidirsctinap pirt ti updats ths prigram ciuntsr with addrsss rsgistsr and incrsmsntsr. Addrsss rsgistsr cintsnt is incrsmsntsd at svsry ssqusntap byts accsss by ths incrsmsntsr but ths prigram ciuntsr is incrsmsntsd by fiur in ARM stats if ths cirs ir is incrsmsntsd by 2 in Thumb stats if ths cirs at svsry instructin accsss. ARM and Thumb statss if ths cirs ars discusssd in ssctin 1.3. Addrsss rsgistsr is dirsctpy cinnsctsd ti ths addrsss bus.

Ths barrsp shifsr can shif ir ritats ipsrand 2 by spscifsd numbsr if bits priir ti arithmstc ir pigic ipsratins.

Ths 32 bit ALU psrfirms ths arithmstc and pigic functins.

Ths data in and data iut rsgistsrs hipd ths input and iutput data frim and ti ths msmiry.

Ths instructin dscidsr and assiciatsd cintrip pigic gsnsratss appripriats cintrip signaps fir ths data path afsr dsciding ths fstchsd instructin.

Ths MAC unit is ti muptppy twi rsgistsr ipsrands and accumupats with anithsr rsgistsr hipding ths partap sum if ths priducts.

Ths sncidsd instructin byts if ths prigram savsd in ths cids msmiry is fstchsd thriugh ths data bus and frst sntsrs inti ths data-in rsgistsr if ths ARM architscturs frim whsrs it is dspivsrsd ti ths instructin dscidsr. Afsr ths instructin is dscidsd, appripriats cintrip signaps ars gsnsratsd fir ths data path. Ths rsquirsd rsgistsrs ars actvatsd in ths rsgistsr bank and ths ipsrands fiw iut frim twi rsad pirts if rsgistsr bank ti ths ALU: ipsrand1 thriugh A-bus and ipsrand2 thriugh B- bus afsr prspricsssing at barrsp shifsr. Ths rssupt if ipsratin at ALU is writsn back ti ths rssupt rsgistsr thriugh a writs pirt at rsgistsr bank. Fir Liad/Stirs instructins, afsr dsciding ths instructin, ths data msmiry addrsss is frst capcupatsd at ALU as spscifsd in ths instructin and ths piintsr rsgistsr is updatsd at ths rsgistsr bank. Ths addrsss in ths piintsr rsgistsr is givsn ti ths addrsss rsgistsr ti accsss ths msmiry and transfsr data. If it is a piad muptpps ir stirs muptpps instructin, ths cirs diss nit hapt bsfirs cimppstng ths rsquirsd numbsr if data transfsrs unpsss it is a rssst sxcsptin.

Migration to Cortex Series

In ths path if architscturap sviputin, ARM has cintributsd many vsrsiins if IP cirss ti ths smbsddsd cimputng wirpd. ARM piinssrsd smbsddsd priducts ars sxcspping in svsry visibps spsctrum. Sincs its incsptin, ARM has migratsd ivsr a ping msaningfup riad map startng frim v4T ARM7TDMI ti v7 Cirtsx ssriss if architscturss achisving many string mipsstinss in bstwssn. It is currsntpy ths nsw sra if fsaturs rich ARM Cirtsx ssriss architscturss trupy smpiwsring ths smbsddsd cimputng wirpd.

ARM architecture evolution

ARM architecture evolution Fig 1.13. Performance and capability graph of Classic ARM and Cortex application processors

Fig 1.13. Performance and capability graph of Classic ARM and Cortex application processors

ARM architscturs has bssn imprivsd a pit in ths riad map frim cpassic ARM ti ARM Cirtsx. Fig1.7 and fg117 dspict ths psrfirmancs and capabipity cimparisin if cpassic ARM with smbsddsd cirtsx and apppicatin cirtsx ssriss if pricsssirs. Evsn thiugh ARM had sarpisr vsrsiins if priducts i.s.,v1, v2, v3 and v4, ths cpassic griup if ARM starts with v4T. Ths cpassic griup is dividsd inti fiur basic famipiss cappsd ARM7, ARM9, ARM10 and ARM11.

ARM7 has thrss-stags (fstch, dscids, sxscuts) pipspins, Vin-Numann architscturs whsrs bith addrsss and data uss ths sams bus. It sxscutss v4T instructin sst. T stands fir Thumb.

ARM9 has fvs-stags (fstch, dscids, sxscuts, msmiry, writs) pipspins with highsr psrfirmancs, Harvard architscturs with ssparats instructin and data bus. ARM9 sxscutss v4T and v5TE instructin ssts. E stands fir snhancsd instructins.

ARM10 has six-stags (fstch, issus, dscids, sxscuts, msmiry, writs) pipspins with iptinap vsctir fiatng piint unit and dspivsrs high fiatng piint psrfirmancs. ARM10 sxscutss v5TE instructin ssts.

Microcontroller profle (Cortex -M)

Cirtsx M ssriss if architscturss havs v6-M as cirtsx M0, M0+ and M1 and v7-M with Cirtsx M3, M4 and ithsr succsssirs. This ssriss if architscturss dsvspipsd fir dssppy smbsddsd micricintrippsr prifps, ifsr piwsst gats ciunt si smappsst sipicin arsa. Thsss ars fsxibps and piwsrfup dssigns with cimppstspy prsdictabps and dstsrministc intsrrupt handping capabipitss by intriducing ths nsstsd vsctir intsrrupt cintrippsr (NVIC). Ths smapp instructin ssts suppirt fir high cids dsnsity and simppifsd sifwars dsvspipmsnt. Dsvspipsrs ars abps ti achisvs 32-bit psrfirmancs at 1-bit prics. Ths vsry piw gats ciunt if Cirtsx M0 facipitatss its dsppiymsnt in anapig and mixsd mids dsvicss. Dus ti furthsr dsmanding apppicatins rsquiring svsn bstsr snsrgy sfcisncy, Cirtsx M0+ was dssignsd with twi stags pipspins and achisvsd high psrfirmancs with vsry piw dynamic piwsr cinsumptin, rsducsd branch shadiw and rsducsd numbsr if fash msmiry accsss. Cirtsx M1 was dssignsd fir imppsmsntatin in FPGA. It is functinappy a subsst if Cirtsx M3 and runs ARM v6 instructin sst with OS sxtsnsiin iptins. It has 32-bit AHB pits bus intsrfacs, ssparats tghtpy ciuppsd msmiry intsrfacs and JTAG intsrfacs ti facipitats dsbug iptins. It has thrss stags pipspins imppsmsntatin and cinfgurabps NVIC fir rsducing intsrrupt patsncy.

Introduction to TIVA Microcontrollers

In this text book, TIVA platforms and launch pads are used to develop various embedded applications. So in this section two TIVA series microcontrollers are introduced.

TIVA TM4C123GH6PM Microcontroller

The microcontroller block diagram shown in Fig 1.20 and Fig 1.21 have six functional units.

The microcontroller block diagram shown in Fig 1.20 and Fig 1.21 have six functional units. The cortex M4F core, on-chip memory, analog block, serial interface, motion control and system integration.

Features:

o

TM4C123GH6PM microcontroller has 32 bit ARM Cortex M4 CPU core with 80 MHz clock rate.

o

Memory protection unit provides protected operating system functionality and floating point unit supports IEEE single precision operations.

o

JTAG/SWD/ETM for serial wire debug and trace.

o

Nested vector interrupt controller (NVIC) reduces interrupt response latency.

o

Serial control block holds the system configuration information.

o

The microcontroller has a set of memory integrated in it: 256 KB flash memory, 32 KB SRAM, 2 KB EEPROM and ROM loaded with TIVA software library and bootloader.

o

Serial communications peripherals such as: 2 CAN controllers, full speed USB controller, 8 UARTs, 4 I2C modules and 4 Synchronous serial interface modules.

o

On chip voltage regulator, two analog comparators and two 12 channel 12-bit analog to digital converter with sample rate I million samples per second are the analog functions in built to the device.  Two quadrature encoder with index module and two PWM modules are the advanced motion control functions integrated into the device that facilitate wheel and motor controls.

o

Various system functions integrated into the device are: Direct Memory Access controller, clock and reset circuitry with 16 MHz precision oscillator, six 32-bit timers, six 64-bit timers, twelve 32/64 bit capture compare PWM, battery backed hibernation module and RTC hibernation module, 2 watchdog timers and 43 GPIOs.

Few Applications:

o

Building automation system

o

Lighting control system

o

Data acquisition system

o

Motion control

o

IoT and Sensor networks.

1.2.16.2 TIVA TM4C129CNCZAD Microcontroller

networks. 1.2.16.2 TIVA TM4C129CNCZAD Microcontroller Features: o TM4C129CNCZAD microcontroller has 32 bit ARM

Features:

o

TM4C129CNCZAD microcontroller has 32 bit ARM Cortex M4F CPU core with 120 MHz clock rate.

o

Memory protection unit provides a privileged mode for protected operating system functionality and floating point unit supports IEEE 754 compliant single precision operations.

o

JTAG/SWD/ETM for serial wire debug and trace.

o

Nested vector interrupt controller (NVIC) reduces interrupt response latency and high performance interrupt handling for time critical applications.

o

The microcontroller has a set of memory integrated in it: 1MB flash memory, 256 KB SRAM, 6 KB EEPROM and ROM loaded with TIVAware, software library and bootloader.

o

Serial communications peripherals such as: 2 CAN controllers, full speed and high speed USB controller, 8 UARTs, 10 I2C modules and 4 Synchronous serial interface modules.

o

On chip voltage regulator, three analog comparators and two 12 channel 12-bit analog to digital converter with sample rate 2 million samples per second and temperature sensor are the analog functions in built to the device.

o

One quadrature encoder and one PWM module with 8 PWM outputs are the advanced motion control functions integrated into the device that facilitate wheel and motor controls.

o

Various system functions integrated into the device are: Micro Direct Memory Access controller, clock and reset circuitry with 16 MHz precision oscillator, eight 32-bit timers, low power battery backed hibernation module and RTC hibernation module, 2 watchdog timers and 140 GPIOs.

o

Cyclic Redundancy Check (CRC) computation module is used for message transfer and safety system checks. CRC module can be used in combination with AES and DES modules.

o

Advanced Encryption Standard (AES) and Data Encryption Standard (DES) accelerator module provides hardware accelerated data encryption and decryption functions.

o

Secure Hash Algorithm/ Message Digest Algorithm (SHA/MD5) provides hardware accelerated hash functions for secured data applications.

Registers

Rsgistsrs ars fir tsmpirary data stirags within pricsssir architscturs. As shiwn in Fig.1.1, ARM pricsssir has sixtssn numbsrs if gsnsrap purpiss rsgistsrs, R0-R15 and a currsnt prigram status rsgistsr (CPSR) dsfnsd fir ussr mids if ipsratin. Each if thsss rsgistsrs is if 32-bits. Out if thsss rsgistsrs, R13, R14 and R15 havs spsciap purpisss

R13: Ussd as ths stack piintsr that hipds ths addrsss if ths tip if ths stack in ths currsnt pricsssir mids.

R14: Ussd as ths pink rsgistsr that savss ths cintsnt if prigram ciuntsr in cintrip transfsr dus ti ths iccurrsncs if sxcsptins ir using ths branch instructins in ths prigram.

R15: Ussd as ths prigram ciuntsr that piints ti ths nsxt instructin ti bs sxscutsd. In ARM stats, app instructins ars if 32-bits (fiur bytss) fir which, PC is apways apignsd ti a wird biundary. This msans that ths psast signifcant twi bits if ths PC ars apways zsri. Ths PC can apsi bs hapfwird (16- bit) apignsd fir Thumb stats (16 bit instructins) ir byts apignsd fir Jazspps stats (1-bit instructins) suppirtsd by difsrsnt vsrsiins if ARM architscturs

Current Program Status Register (CPSR) CPSR, a 32-bit status rsgistsr, hipds ths currsnt stats if

Current Program Status Register (CPSR)

Current Program Status Register (CPSR) CPSR, a 32-bit status rsgistsr, hipds ths currsnt stats if ths

CPSR, a 32-bit status rsgistsr, hipds ths currsnt stats if ths ARM cirs. As shiwn in Fig 1.4, ths rsgistsr is dividsd inti fiur difsrsnt fspds- fags, status, sxtsnsiin and cintrip; sach if 1-bits. Ths fag fspd has ths bit spscifcatin fir fiur cinditin fags; N, a, C and V and is ussd fir arithmstc and pigic instructins.

N-(Nsgatin fag)

1 indicatss nsgatvs rssupt frim ALU.

a- (asri fag)

1 indicatss zsri rssupt frim ALU.

C- (Carry fag)

V- (Ovsrfiw fag)

1 indicatss ALU ipsratin gsnsratsd carry.

1 indicatss ALU ipsratin ivsrfiwsd.

Mist if ths ARM instructins ars cinditinappy sxscutsd. Bassd in ths status if thsss cinditin fags, cinditin cidss ars ussd aping with instructin mnsminics ti cintrip whsthsr ir nit ths instructin wipp bs sxscutsd. Status and sxtsnsiin fspds ars rsssrvsd fir futurs usags. In ths cintrip fspd, ths psast signifcant fvs bits ars ussd ti savs ths midss if ipsratin if ARM cirs. Pricsssir

mids can bs changsd by dirsctpy midifying thsss cintrip bits. Ths mist signifcant thrss bits I, F and T havs signifcancs as bspiw:

1 indicatss IRQ is disabpsd ;

I

0 indicatss IRQ is snabpsd.

1 indicatss FIQ is disabpsd

F

;

0 indicatss FIQ is snabpsd.

1 indicatss ths Thumb stats is actvs

T

;

0 indicatss ARM stats is actvs.

Thsss ars pricsssir spscifc fsaturss.

Addressing modes

Addrsssing mids is ths way if addrsssing data ir ipsrand in ths instructin. Evsry pricsssir instructin sst ifsrs difsrsnt addrsssing midss ti dstsrmins ths addrsss if ipsrands. Sims fundamsntap addrsssing midss ussd by mist if ths pricsssirs ars: rsgistsr addrsssing, immsdiats addrsssing, dirsct addrsssing and rsgistsr indirsct addrsssing. In rsgistsr addrsssing mids, ths ipsrand is hspd in a rsgistsr which is spscifsd in ths instructin. In immsdiats addrsssing mids, ths ipsrand is hspd in ths instructin. In dirsct addrsssing mids, ths ipsrand rssidss in ths msmiry whiss addrsss is spscifsd in ths instructin. Simiparpy in rsgistsr indirsct addrsssing mids, ths ipsrand is hspd in ths msmiry whiss addrsss rssidss in a rsgistsr that is spscifsd in ths instructin

ARM Addressing modes:

Rsgistsr Addrsssing: Ths ipsrands ars in ths rsgistsrs. MOV R1, R2 R2 ti R1 //

// mivs cintsnt if

SUB R0, R1, R2

//subtract cintsnt if R2 frim R1 and mivs ths rssupt ti R0 //

Rspatvs Addrsssing: Addrsss if ths msmiry dirsctpy spscifsd in ths instructin. Bsubriutns1// branch ti suriutns1 // BEQ LOOP // branch ti LOOP if prsviius instructin ssts ths zsri fag i.s, a 1 //

Immsdiats Addrsssing: Opsrand2 is an immsdiats vapus. SUB R0, R0, #1// Savs (R0 –1) ti R0 // MOV R0, #0xFF00 // Put 0xFF00 ti R0 //

Rsgistsr Indirsct Addrsssing: Addrsss if ths msmiry picatin that hipds ths ipsrands thsrs in a rsgistsr. LDR R1, [R2]//Liad R1 with ths data piintsd by rsgistsr R2. // ADD R0, R1, [R2]//add R1 with ths data piintsd by R2 and put ths rssupt inti R0//

Rsgistsr Ofsst Addrsssing: Opsrand2 is in a rsgistsr with sims ifsst capcupatin. MOV R0,

R2, LSL #3

AND R0, R1, R2, LSR R3// (R2 >> R3), pigicappy AND with R1 and mivs rssupt ti R0 //

// (R2 << 3), thsn mivs ti R0 //

Rsgistsr bassd with Ofsst Addrsssing: Efsctvs msmiry addrsss has ti bs capcupatsd frim a bass addrsss and an ifsst. Ofsst can bs an immsdiats ifsst, rsgistsr ifsst ir scapsd rsgistsr ifsst.

Prs-Indsxsd Addrsssing LDR R2, [R3, #0x0F]

// Immsdiats ifsst. // Taks vapus in R3, add

ti 0x0F, uss it as addrsss and piad data frim that addrsss ti R2 //

STR R1, [R0, -R2]

data if R1 ti that addrsss.//

// Rsgistsr ifsst // Uss (R0-R2) as addrsss if ths msmiry and stirs

LDR R3, [R1, R2 LSR #1] // Scapsd rsgistsr ifsst// // Uss (R1+ (R2>>1)) as addrsss and piad ths data frim that addrsss ti R3. //

Prs-Indsxsd with writs back apsi cappsd auti-indsxing with prs-indsxsd addrsssing. symbip indicatss that ths instructin savss ths capcupatsd addrsss in ths bass addrsss rsgistsr. LDR

// Immsdiats ifsst // // Uss (R1+4) as addrsss and piad ths data frim that

R0, [R1, #4]!

addrsss ti R0 and updats R1 by

(R1+4)//

STR R1, [R2, R0]!

ti that addrsss. Updats R2 by

// Rsgistsr ifsst // // Uss (R2+R0) as addrsss and stirs ths data frim R1

(R2+R0) //

STR R3, [R1, R2 LSL #4]!

stirs ths data frim R3 ti that addrsss. Updats R1 by (R1+ (R2<<4)) //

// Scapsd rsgistsr ifsst //

// Uss (R1+ (R2<<4)) as addrsss and

Pist-Indsxsd apsi cappsd auti-indsxing with pist-indsxsd addrsssing. LDR R0, [R1], #4

//

Immsdiats ifsst // // Liad ths data piintsd ti by R1 ti R0 and thsn updats R1 by (R1+4). //

STR R1, [R3], R4 // Rsgistsr ifsst // // Stirs ths data in R1 ti ths msmiry picatin piintsd ti by R3 and thsn updats R3 by (R3+R4)//

LDR R2, [R0], -R3, LSR #4

piintsd ti by R0 ti R2 and thsn updats R0 ti (R0- (R3>>4)). //

// Scapsd rsgistsr ifsst // // Liad ths data frim ths addrsss

ARM Instruction Set

In any pricsssir architscturs, an instructin incpudss an ipcids that spscifss ths ipsratin ti psrfirm, such as add cintsnts if twi rsgistsrs ir mivs data frim a rsgistsr ti msmiry stc, with spscifsd ipsrands, which may spscify rsgistsrs, msmiry picatins, ir immsdiats data. Instructin sst if a pricsssir givss infirmatin abiut ths instructins, addrsssing midss and ths tming rsquirsmsnt fir ths sxscutin if sach instructin. Ths instructin sst is apways spscifsd by ths pricsssir dssignsr. Evsry pricsssir imppsmsnts its instructin sst in ths architscturs. ARM Ltd bsing ths pricsssir cirs dssignsr and nit ths sipicin manufactursr, it dsfnss ths instructin sst ti bs imppsmsntsd by ths chip manufactursrs.

Features

ARM architscturs has twi instructin ssts. Ths ARM instructin sst and Thumb instructin sst. In ARM instructin sst, app instructins ars 32 bits wids and ars apignsd at 4-bytss biundariss in msmiry. On ths ithsr hand, in thumb instructin sst, app instructins ars if 16 bits wids and ars apignsd at svsn ir twi bytss biundariss in msmiry.

Ths impirtant fsaturss if ths ARM and Thumb instructin sst ars:

o

Mist if ths instructins ars sxscutsd in ins cycps.

o

Liad/Stirs architscturs fir accsssing data frim sxtsrnap msmiry with piwsrfup auti-indsxing addrsssing midss.

o

Incpusiin if piad and stirs muptpps rsgistsr instructins.

o

3-addrsss instructins: twi siurcs ipsrand rsgistsrs and ths rssupt rsgistsr ars app distnctpy spscifsd.

o

Data pricsssing instructins act inpy in rsgistsrs.

o

Evsry instructin can bs cinditinappy sxscutsd which imprivss ths psrfirmancs and cids dsnsity by rsducing ths numbsr if branch instructins.

o

Ths abipity ti sxscuts a barrsp shif ipsratin and an ALU ipsratin if a singps cimppsx instructin in a singps cpick cycps.

o

Incpusiin if advancsd DSP instructins in ths ARM instructin sst fir ths muptppy and accumupats (MAC) unit rsppacss ths nssd if ssparats digitap signap pricsssir.

o

Imppsmsntatin if cipricsssir instructin sst with sxtsnsiin if ths prigramming midsp.

o

Ths Thumb instructin sst is 16-bit cimprssssd rsprsssntatin if ths ARM instructins that prividss high cids dsnsity.

ARM Instructins can bs catsgirizsd inti fippiwing briad cpassss:

1 .Data mivsmsnt instructins

2. Data Pricsssing Instructins

o

Arithmstc/pigic Instructins

o

Barrsp shifing instructins

o

Cimparisin Instructins

o

Muptppy Instructins

3. Branch Instructins

4. Liad and stirs Instructins

o

Liad and Stirs rsgistsr instructin

o

Liad and Stirs muptpps rsgistsr instructins

o

Stack instructins

o

Swap rsgistsr and msmiry cintsnt

5. Prigram Status rsgistsr Instructins

o Sst ths vapuss if ths cinditinap cids fag

o

Sst ths vapuss if ths intsrrupt snabps bit

o

Sst ths pricsssir mids

6. Excsptin gsnsratng Instructins

o

Sifwars Intsrrupt Instructin

o

Sifwars Brsak Piint instructin

UNIT-III Overview of Microcontroller and Embedded Systems

3.1 Embedded hardware and various building blocks:-

Systems 3.1 Embedded hardware and various building blocks:- Fig. 1 Components of Embedded system hardware Fig.

Fig. 1 Components of Embedded system hardware

building blocks:- Fig. 1 Components of Embedded system hardware Fig. 2 Various Building blocks of embedded

Fig. 2 Various Building blocks of embedded system

building blocks:- Fig. 1 Components of Embedded system hardware Fig. 2 Various Building blocks of embedded
3.2 Processor Selection for an Embedded System:-

3.2 Processor Selection for an Embedded System:-

3.2 Processor Selection for an Embedded System:-
3.2.1. Microcontroller Selection:

3.2.1. Microcontroller Selection:

3.2.1. Microcontroller Selection:
3.3 Interfacing Processor, Memories and I/O Devices:-

3.3 Interfacing Processor, Memories and I/O Devices:-

3.3 Interfacing Processor, Memories and I/O Devices:-
Features:
Features:
Features:

Features:

Features:
3.4. Timer & Counting Devices:- Most embedded systems needs a timing device. Timing Device: Counting

3.4. Timer & Counting Devices:-

Most embedded systems needs a timing device. Timing Device:

3.4. Timer & Counting Devices:- Most embedded systems needs a timing device. Timing Device: Counting Device:

Counting Device:

3.4. Timer & Counting Devices:- Most embedded systems needs a timing device. Timing Device: Counting Device:
Timer cum Counting Device: Uses of Timer Devices:

Timer cum Counting Device:

Timer cum Counting Device: Uses of Timer Devices:

Uses of Timer Devices:

Timer cum Counting Device: Uses of Timer Devices:
States in a Timer:

States in a Timer:

States in a Timer:
States in a Timer:

Ten Forms of a Timer:

Ten Forms of a Timer: Variables for control bits and status in a software timer: 3.5.

Variables for control bits and status in a software timer:

Variables for control bits and status in a software timer: 3.5. Serial Communication and advanced I/O:-

3.5. Serial Communication and advanced I/O:- I/O Types & Examples:

for control bits and status in a software timer: 3.5. Serial Communication and advanced I/O:- I/O

Serial Bus Communication Protocols:-

Serial Bus Communication Protocols:-
Serial Bus Communication Protocols:-
3.6 Buses between the Networked multiple Devices:-

3.6 Buses between the Networked multiple Devices:-

3.7 Embedded System Design and Co-Design Issues in System Development Process:-

3.7 Embedded System Design and Co-Design Issues in System Development Process:-

3.7 Embedded System Design and Co-Design Issues in System Development Process:-
3.8 Design Cycle in the Development Phase for an Embedded System:-

3.8 Design Cycle in the Development Phase for an Embedded System:-

3.8 Design Cycle in the Development Phase for an Embedded System:-

3.9. Uses of Target System or its Emulator and In-Circuit Emulator:-

3.9. Uses of Target System or its Emulator and In-Circuit Emulator:-
3.10 Use of software tools for Development of an Embedded System:-

3.10 Use of software tools for Development of an Embedded System:-

3.10 Use of software tools for Development of an Embedded System:-
2 3.11 Design Metrics of Embedded Systems:-

2

2 3.11 Design Metrics of Embedded Systems:-
2 3.11 Design Metrics of Embedded Systems:-

3.11 Design Metrics of Embedded Systems:-

2 3.11 Design Metrics of Embedded Systems:-

UNIT-4

MICROCONTROLLER FUNDAMENTALS FOR BASIC PROGRAMMING

The I/O pin configurations for the TM4C123 microcontrollers. The regular function of a pin is to perform parallel I/O. Most of the pins have an alternative function. Joint Test Action Group (JTAG) is a standard test access port used to program and debug the microcontroller board. Each microcontroller uses five port pins for the JTAG interface.

I/O pins on Tiva microcontrollers have a wide range of alternative functions:

UART

SSI

I 2 C

Timer

PWM

ADC

Analog Comparator

QEI

USB

Ethernet

CAN

Universal asynchronous receiver/transmitter

Synchronous serial interface

Inter-integrated circuit

Periodic interrupts, input capture, and output compare

Pulse width modulation

Analog to digital converter, measure analog signals

Compare two analog signals

Quadrature encoder interface

Universal serial bus

High-speed network

Controller area network

The UART can be used for serial communication between computers. It is asynchronous and allows for simultaneous communication in both directions. The SSI is alternately called serial peripheral interface (SPI). It is used to interface medium-speed I/O devices. I 2 C is a simple I/O bus that we will use to interface low speed peripheral devices. Input capture and output compare will be used to create periodic interrupts and measure period, pulse width, phase, and frequency. PWM outputs will be used to apply variable power to motor interfaces. In a typical motor controller, input capture measures rotational speed, and PWM controls power. A PWM output can also be used to create a DAC. The ADC will be used to measure the amplitude of analog signals and will be important in data acquisition systems. The analog comparator takes two analog inputs and produces a digital output depending on which analog input is greater. The QEI can be used to interface a brushless DC motor. USB is a high-speed serial communication channel. The Ethernet port can be used to bridge the microcontroller to the Internet or a local area network. The CAN creates a high-speed communication channel between microcontrollers and is commonly found in automotive and other distributed control applications.

4.1 Tiva TM4C123 LaunchPad I/O pins

Pins on the TM4C family can be assigned to as many as eight different I/O functions. Pins can be configured for digital I/O, analog input, timer I/O, or serial I/O. For example PA0 can be digital I/O or serial input. There are two buses used for I/O. The digital I/O ports are connected to both the advanced peripheral bus and the advanced high-performance bus. Because of the multiple buses, the microcontroller can perform I/O bus cycles simultaneous with instruction fetches from flash ROM. The TM4C123GH6PM adds up to 16 PWM outputs. There are 43 I/O lines. There are twelve ADC inputs; each ADC can convert up to 1M samples per second. Table 6.1 lists the regular and alternate names of the port pins.

Figure : I/O port pins for the TM4C123GH6PM microcontrollers. Each pin has one configuration bit

Figure : I/O port pins for the TM4C123GH6PM microcontrollers.

Each pin has one configuration bit in the GPIOAMSEL register. We set this bit to connect the port pin to the ADC or analog comparator. For digital functions, each pin also has four bits in the GPIOPCTL register, which we set to specify the alternative function for that pin (0 means regular I/O port). Not every pin can be connected to every alternative function.

Pins PC3 PC0 were left off Table 4.1 because these four pins are reserved for the JTAG debugger and should not be used for regular I/O. Notice, most alternate function modules (e.g., U0Rx) only exist on one pin (PA0). While other functions could be mapped to two or three pins (e.g., CAN0Rx could be mapped to one of the following: PB4, PE4, or PF0.)

The microcontroller board provides an integrated In-Circuit Debug Interface (ICDI), which allows programming and debugging of the onboard TM4C123 microcontroller. One USB cable is used by the debugger (ICDI), and the other USB allows the user to develop USB applications (device). The user can select board power to come from either the debugger (ICDI) or the USB device (device) by setting the Power selection switch.

Pins PA1 PA0 create a serial port, which is linked through the debugger cable to the PC. The serial link is a physical UART as seen by the TM4C and mapped to a virtual COM port on the PC. The USB device interface uses PD4 and PD5. The JTAG debugger requires pins PC3 PC0. The LaunchPad connects PB6 to PD0, and PB7 to PD1. If you wish to use both PB6 and PD0 you will need to remove the R9 resistor. Similarly, to use both PB7 and PD1 remove the R10 resistor.

Figure: Tiva LaunchPad based on the TM4C123GH6PM. The Tiva LaunchPad evaluation board has two switches

Figure: Tiva LaunchPad based on the TM4C123GH6PM.

The Tiva LaunchPad evaluation board has two switches and one 3-color LED. See Figure 4.3. The switches are negative logic and will require activation of the internal pull-up resistors. In particular, you will set bits 0 and 4 in GPIO_PORTF_PUR_R register. The LED interfaces on PF3 PF1 are positive logic. To use the LED, make the PF3 PF1 pins an output. To activate the red color, output a one to PF1. The blue color is on PF2, and the green color is controlled by PF3. The 0-Ω resistors (R1, R2, R11, R12, R13, R25, and R29) can be removed to disconnect the corresponding pin from the external hardware.

The LaunchPad has four 10-pin connectors, labeled as J1 J2 J3 J4 in Figures 4.2 and 4.4, to which you can attach your external signals. The top side of these connectors has male pins, and the bottom side has female sockets.

has male pins, and the bottom side has female sockets. Figure 4.3. Switch and LED interfaces

Figure 4.3. Switch and LED interfaces on the Tiva LaunchPad Evaluation Board. The zero ohm resistors can be removed so the corresponding pin can be used for its regular purpose.

4.2 GPIO

GPIO stand for General Purpose Input/Outputs, meaning that it's a module capable of receiving and transmitting signals. They work with digital signals but can be mixed to use the pins with other peripheral functions (ADC, SSI, UART, etc).

Tiva GPIOs

The tm4c123gh6pm has 6 GPIO blocks, each with his own GPIO port (portA, port B, port C, port D , port E , port F).

Up to 43 GPIOs, depending on configuration

Highly flexible pin muxing allows use as GPIO or one of several peripheral functions

5-V-tolerant in input configuration

Ports A-G accessed through the Advanced Peripheral Bus (APB)

Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for ports on APB

Programmable control for GPIO interrupt

Interrupt generation masking

Edge-triggered on rising, falling, or both

Level-sensitive on High or Low values

Bit masking in both read and write operations through address lines

Can be used to initiate an ADC sample sequence or a μDMA transfer

Pin state can be retained during Hibernation mode

Pins configured as digital inputs are Schmitt-triggered

Programmable control for GPIO pad configuration

Weak pull-up or pull-down resistors

2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA for high-current applications

Slew rate control for 8-mA pad drive

Open drain enables

Digital input enables

Note that PD4, PD5, PB0 and PB1 aren't 5V tolerant and are maxed at a 3.6V input.

Each GPIO has 8 pins which should make a total of 48 pins but some of those are internal and can't be used so the maximum is 43. The launchpads usually have less since some are not physically available. The TM4C123 launchpad has just 37 GPIO pins.

Alternate functions

The GPIO allows digital inputs or outputs and also allows alternate functions. The alternate functions can be analog readings by muxing the ADC to a pin, or UART communication by making the right muxing.

Very Important GPIO Pins With Special Considerations Some pins are locked to a certain configuration

Very Important GPIO Pins With Special Considerations

Some pins are locked to a certain configuration and can only be used if you unlock them. You need to do that in the GPIOLOCK register and uncommitted it by setting the GPIOCR register. If you use TivaWare this should work, just chose the right base:

HWREG(GPIO_PORTx_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY; HWREG(GPIO_PORTx_BASE + GPIO_O_CR) |= 0x80;

= GPIO_LOCK_KEY; HWREG(GPIO_PORTx_BASE + GPIO_O_CR) |= 0x80; TM4C123 GPIO Programming The TI LaunchPad uses the

TM4C123 GPIO Programming

The TI LaunchPad uses the TM4C123GH6PM microcontroller, which has 256K bytes (256KB) of on- chip Flash memory for code, 32KB of on-chip SRAM for data, and a large number of on-chip peripherals.

The ARM Cortex-M4 has 4GB (Giga bytes) of memory space. It uses memory mapped I/O, which means that the I/O peripheral ports are mapped into the 4GB memory space.

Allocated size Allocated address

Allocated size

Allocated address

Flash

256 KB

0x0000.0000 To 0x0003.FFFF

Flash 256 KB 0x0000.0000 To 0x0003.FFFF 32 KB 0x2000.0000 To 0x2000.7FFF SRAM I/O All the

32 KB

0x2000.0000 To 0x2000.7FFF

SRAM

I/O

All the peripherals

0x4000.0000 to 0x400F.FFFF

The General Purpose I/O ports (GPIO) on TM4C123GXL LaunchPad are designated to port A to port F. The address range assigned to each GPIO port is shown as follows:

Port A: 0x4000.4000 to 0x4000.4FFF

Port B: 0x4000.5000 to 0x4000.5FFF

Port C: 0x4000.6000 to 0x4000.6FFF

Port D: 0x4000.7000 to 0x4000.7FFF

Port E: 0x4002.4000 to 0x4002.4FFF

Port F: 0x4002.5000 to 0x4002.5FFF

The 4K bytes of memory space is assigned to each of the GPIO. The reason is that each GPIO has a large number of special function registers associated with it, and furthermore GPIO Data Register supports bit-specific addressing, which allows collective access to 1 to 8 bits in a data port.

To initialize an I/O port for general use seven steps need to be performed.

2. Unlock the port (LOCK = 0x4C4F434B). This step is only needed for pins PC0- 3, PD7 and PF0 on TM4C123GXL LaunchPad.

3. Disable the analog function of the pin in the Analog Mode Select register (AMSEL), because we want to use the pin for digital I/O. If this pin is connected to the ADC or analog comparator, its corresponding bit in AMSELmust be set as 1. In our case, this pin is used as digital I/O, so its corresponding bit must be set as 0.

4. Clear bits in the port control register (PCTL) to select regular digital function. Each GPIO pin needs four bits in its corresponding PCTL register. Not every pin can be configured to every alternative function. Figure 2.2 shows which pin can be used as what kind of alternate functions.

5. Set its direction register (DIR). A DIR bit of 0 means input, and 1 means output.

6. Clear bits in the alternate Function Select register (AFSEL).

7. Enable digital port in the Digital Enable register (DEN).

We need to add a short delay between activating the clock and setting the port registers.

Figure: registers used to configure GPIO
Figure: registers used to configure GPIO

Figure: registers used to configure GPIO

Figure: – PMCx bits in the GPIOPCTL register on the TM4C specify alternate functions. PD4

Figure: PMCx bits in the GPIOPCTL register on the TM4C specify alternate functions. PD4 and PD5 are hardwired to the USB device. PA0 and PA1 are hardwired to the serial port

The GPIO Data Register is located at the offset address of 0x000 from the base address of its port. As we mentioned before, the data register supports bit-specific addressing. In order to write to this register, the corresponding bits in the mask, resulting from the address bus bits[9:2], must be set. Otherwise, the bit values remain unchanged by the write.

For example, writing to address 0x40004038 means that bits 1, 2 and 3 of port A must be changed, since the base address of port A is 0x40004000. The explanation is shown in below.

of port A is 0x40004000. The explanation is shown in below . The following table help

The following table help you calculate offset address for the bits of a port, to which you want to access.

If we want to access bit

Offset Constanct

7

6

5

4

3

2

1

0

0x200

0x100

0x080

0x040

0x020

0x010

0x008

0x004

bit Offset Constanct 7 6 5 4 3 2 1 0 0x200 0x100 0x080 0x040 0x020

If we want to read and write all 8 bits of a port, it means that we need to sum all these 8 offset constants,

which makes the offset address of 0x3FC (001111111100 in binary).

4.3 Peripheral and Memory Address

A 32-bit processor can have 4 GB (=232) of address spaces. It depends on the architecture of the CPU

how these address spaces are segregated, among the memory and peripherals.

Peripheral Addressing

There are two complementary methods of addressing I/O devices for input and output between CPU and peripheral. These are known as memory mapped I/O (MMIO) and port mapped I/O (PMIO). www.ti.com Peripheral and Memory Address

In MMIO, same address bus is used to address both memory and peripheral devices. The address bus of

the CPU is shared between the peripheral devices and memory devices attached to the CPU. Thus, any

address accessed by the CPU may denote an address in the memory or a register of attached peripheral.

In these architectures, same CPU instructions used for memory access can also be used for I/O access.

In PMIO, peripheral devices possess a separate address bus from general memory devices. This is accomplished in most architectures by providing a separate address bus dedicated to the peripheral devices attached to the CPU. In these CPUs, the instruction set includes separate instructions to perform I/O access.

A TM4C123GH6PM chip employs MMIO which implies that the peripherals are mapped into the 32-bit

address bus.

4.4 Memory Mapped Peripherals

A TM4C123GH6PM chip consists of a 256 KB of Flash memory and 32 KB of SRAM. Table 5 shows

the memory map of a TM4C123GH6PM chip with addresses.

Flash Memory

Flash memory is structured into multiple blocks of single KB size which can be individually written to and erased. Flash memory is used for store program code. Constant data used in a program can also be stored in this memory. Lookup tables are used in many designs for performance improvement. These lookup tables are stored in this memory.

improvement. These lookup tables are stored in this memory. Table: Memory Mapping in TM4C123GH6PM Chip SRAM

Table: Memory Mapping in TM4C123GH6PM Chip

SRAM

The on-chip SRAM starts at address 0x2000.0000 of the device memory map. ARM provides a technology to reduce occurrences of read-modify-write (RMW) operations called bit-banding. This technology allows address aliasing of SRAM and peripheral to allow access of individual bits of the same memory in single atomic operation. For SRAM, the bit-band base is located at address 0x2200.0000. Bit band alias are computed according to following formula.

bitband alias= bitband base + byte offset *32 + bit number *4 (2.1)

Note: Bit banding is the technique to access and modifying content of bits in a register. It is helpful to finish the read-modify operation in single machine cycle.

The region of the memory which device consider for modification is known as bit band region and the region of memory to which device maps the selected memory is known as bit band alias.

The SRAM is implemented using two 32-bit wide SRAM banks (separate SRAM arrays). The banks are partitioned in a way that one bank contains all, even words (the even bank) and the other contains all odd words (the odd bank). A write access that is followed immediately by a read access to the same bank. This incurs a stall of a single clock cycle.

Internal ROM

The internal ROM of the TM4C123GH6PM device is located at address 0x0100.0000 of the device memory map. The ROM contains:

0x0100.0000 of the device memory map. The ROM contains: -specific peripherals and interfaces functionality The boot
0x0100.0000 of the device memory map. The ROM contains: -specific peripherals and interfaces functionality The boot

-specific peripherals and

interfaces

map. The ROM contains: -specific peripherals and interfaces functionality The boot loader is used as an
map. The ROM contains: -specific peripherals and interfaces functionality The boot loader is used as an

functionality

The boot loader is used as an initial program loader (when the Flash memory is empty) as well as an application-initiated firmware upgrade mechanism (by calling back to the boot loader). The Peripheral

Driver Library, APIs in ROM can be called by applications, reducing flash memory requirements and freeing the Flash memory to be used for other purposes (such as additional features in the application). Advance Encryption Standard (AES) is a publicly defined encryption standard used by the U.S. Government and Cyclic Redundancy Check (CRC) is a technique to validate if a block of data has the same contents as when previously checked.

Peripheral

All Peripheral devices, timers, and ADCs are mapped as MMIO in address space 0x40000000 to 0x400FFFFF. Since the number of supported peripherals is different among ICs of ARM families, the upper limit of 0x400FFFFF is variant.

Memory Layout in TIVATM Launchpad

To observe the memory layout of TM4C123GH6PM, users can run an experiment on the board with a simple code provided below. This is a simple code that results in the glow of the GREEN LED.

Example:

code that results in the glow of the GREEN LED. Example: Fig : Flowchart to glow

Fig : Flowchart to glow onboard LED

Pseudo code:

Start: Set clock (division| PLL| 16 Mhz| main OSC) Configure the pins (Pin 1, 2, 3) Output: Toggle the led (Pin1, 2, 3) Delay generation (in nanoseconds) Run infinite Once this code is compiled, under workspace, if we expand <the project>/Debug, we can see the memory map file.

4.5 Watchdog Timer

Every CPU has a system clock which drives the program counter. In every cycle, the program counter executes instructions stored in the flash memory of a microcontroller. These instructions are executed sequentially. There exist possibilities where a remotely installed system may freeze or run into an unplanned situation which may trigger an infinite loop. On encountering such situations, system reset or execution of the interrupt subroutine remains the only option. Watchdog timer provides a solution to this.

A watchdog timer counter enters a counter lapse or timeout after it reaches certain count. Under normal

operation, the program running the system continuously resets the watchdog timer. When the system enters an infinite loop or stops responding, it fails to reset the watchdog timer. In due time, the watchdog timer enters counter lapse. This timeout will trigger a reset signal to the system or call for an interrupt service routine (ISR).

the system or call for an interrupt service routine (ISR). Fig : Operation of Watchdog Timer

Fig : Operation of Watchdog Timer

TM4C123GH6PM microcontroller has two Watchdog Timer modules, one module is clocked by the system clock (Watchdog Timer 0) and the other (Watchdog Timer 1) is clocked by the PIOSC therefore it requires synchronizers.

Features of Watchdog Timer in TM4C123GH6PM controller:

Features of Watchdog Timer in TM4C123GH6PM controller: -bit down counter with a programmable load register

-bit down counter with a programmable load register

-bit down counter with a programmable load register protection from runaway software -enabled stalling when the
-bit down counter with a programmable load register protection from runaway software -enabled stalling when the

protection from runaway software-bit down counter with a programmable load register -enabled stalling when the microcontroller asserts the CPU

programmable load register protection from runaway software -enabled stalling when the microcontroller asserts the CPU