1328 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 51, NO.

6, DECEMBER 2002

System Analysis of a Fully-Integrated Capacitive

Angular Sensor
Thilo Sauter, Member, IEEE, and Nikolaus Kerö, Member, IEEE,

Abstract—Contact-less angle measurement principles are far

superior to standard potentiometers in terms of service life and
reliability. Still, their usage is limited due to sophisticated analog
and digital signal processing mandatory to fully exploit their fea-
tures. This article presents the design of a fully-integrated angular
speed sensor system based on a capacitive carrier frequency mea-
surement principle. To optimize the performance, we combined
a synchronous demodulation strategy with an external resonance
filter serving both as clock reference and noise protection. This
filter was extended by an additional low-pass easing implementa-
tion of the demodulator and compensating for internal signal de-
lays. For system simulation, a simple analytical model based on
Fourier synthesis was found to be superior to a conventional SPICE
simulation. This efficient, time-domain-based verification method
allowed performing an exhaustive analysis and optimization of the
complete sensor system. Fig. 1. Configuration of a capacitive angular sensor.

Index Terms—Angular sensor, automotive application, carrier

frequency system, smart sensor, synchronous demodulator, system the signal cannot be used for a reliable computation of the
simulation. angle. Instead, a ratiometric algorithm [4] exploits the relative
differences between the signals measured at the individual
I. INTRODUCTION segments and is compulsory for a measurement to achieve an
overall accuracy of better than 1 .

S ENSORS based on capacitive and inductive principles are

known to be far more reliable than conventional sensors
based on potentiometers. Particularly, in automotive applica-
tions, where both robustness and extended operating conditions
are key issues, contact-less measurement techniques gain more
and more importance. Unfortunately, they also require far more
complicated and sophisticated analog and digital signal analysis
methods than their conventional counterparts.
Fig. 1 shows the principal configuration of a segmented
capacitive angular sensor [1]–[3]. It consists of a number of
“sending” segments, a butterfly shaped rotor, and a “receiving”
electrode. For such sensors, and the small values of the capaci-
tances (typically some 10 fF in practical realization), a carrier
frequency measurement is the most suitable strategy, where a
square wave signal is fed to each segment in turn for a given
period of time. Depending on the rotor position, the capacitance
between the sending and receiving electrodes changes, which
in turn yields an amplitude modulation of the carrier. Based
on the known geometry of the sensor, this variation of the
carrier amplitude is used to determine the angle. As the signal
amplitude can vary significantly due to mechanical tolerances
and changes of the dielectric characteristics of the medium
between the electrodes of the sensor, the absolute value of
Manuscript received May 29, 2001; revised September 5, 2002.
T. Sauter is with the Vienna University of Technology, Institute of Computer
Technology, Wien, Austria (e-mail: sauter@ict.tuwien.ac.at).
N. Kerö is with the Vienna University of Technology, Institute of Industrial
Electronics and Material Science, Wien, Austria (e-mail: keroe@tuwien.ac.at).
Digital Object Identifier 10.1109/TIM.2002.808040
0018-9456/02$17.00 © 2002 IEEE
This paper describes the boundary conditions that need to
be taken into account for the design of an integrated capacitive
sensor system. It outlines the interplay between the various re-
quirements and is structured as follows: Sections II and III will
describe the basic requirements imposed on sensors in the auto-
motive area and the consequences for the general system design,
respectively. Section IV discusses the demodulation strategy,
which is a key design element. In Section V, we present an im-
proved front-end that minimizes the external components while
at the same time supporting extended EMC requirements. Sec-
tion VI finally shows how the proposed approach can be verified
by an efficient system simulation based on Fourier synthesis.
II. REQUIREMENTS IMPOSED BY THE APPLICATION
The requirements of automotive applications impose some
severe restrictions on the design. First and foremost, the pro-
duction costs have to be minimized while obtaining a high level
of reliability. Furthermore, the sensor system has to operate in a
wide temperature range of -40 C to 150 C. As the number of
electronic components even in middle-class cars is constantly
growing, the power consumption has to be strictly limited as
well. Another important boundary condition of the system de-
sign is that the stimulus signal has to be slew-rate limited to im-
prove the EMC properties of the sensor system. To minimize in-
terference of any electronic unit operating in a car with wireless
communication systems like cell phones or radio receivers, sev-
eral large car manufacturers have defined a number of narrow
stop bands. The range of 30 to 300 MHz is of special interest
SAUTER AND KERÖ: SYSTEM ANALYSIS OF A FULLY-INTEGRATED CAPACITIVE ANGULAR SENSOR
Fig. 2. Integrated angular sensor system.
concerning the impact of higher order harmonics of a carrier fre-
quency system, and the forbidden bands in this range limit the
choice of the carrier frequency. Finally, field replaceable units
like angle sensors have to cope with extended mechanical toler-
ances.
Only a fully-integrated sensor system with as few external
components as possible can comply with all of the above-men-
tioned constraints. Consequently, any type of external oscillator
is not admissible both for cost and reliability reasons. Again to
keep production costs low, only standard CMOS fabrication pro-
cesses were considered, although BICMOS technologies are in
principle beneficial when designing high-speed and low-noise
analog circuitry.
III. BASIC SYSTEM DESIGN
The applicability of this sensor configuration was already
demonstrated with a prototype based on a standard micro-con-
troller [1]. For mass production, however, this solution is too
expensive. Consequently, we sought an improved implementa-
tion with utmost integration and as few external components as
possible. Fig. 2 shows the resulting structure of the entire sensor
system. A dedicated microcontroller controls the measurement
and provides stimulation of the sensor segments. The external
front-end consists just of passive components and performs fil-
tering in that it suppresses noise outside the carrier range [1]. All
further signal processing is again integrated. A demodulator ex-
tracts the baseband signal from the modulated carrier, and after
analog/digital conversion the signal is further processed fully
digitally.
The stringent EMC rules in the automotive industry are
satisfied by a carrier frequency range of 15 to 20 MHz. To
cope with the constraint of a forbidden external oscillator, a
numerically controlled oscillator is integrated into the analog
part of the controller. Unfortunately, the frequency of the NCO
exhibits considerable production- and temperature-dependent
variability. This lack of accuracy prevents the use of the NCO
in a straightforward, open-loop manner. However, the external
passive resonance filter also shown in Fig. 2 is set to the
nominal carrier frequency the system should operate at. In the
practical implementation, it is an inexpensive LC-filter con-
sisting of a printed coil (approximately 1.5 H) together with a
lumped capacitance of some 20 pF (in addition to the intrinsic
capacitance of the printed circuit board). The tolerance range
and temperature drift of the filter are one order of magnitude
1329
better than those of the internal NCO; therefore it can serve as
a reference to adjust the clock frequency. To that end, the actual
carrier frequency is regularly adjusted during normal operation
so as to obtain the maximum amplitude of the demodulated
signal [5]. By this closed-loop frequency tracking strategy,
we can ensure that the sensor stays in an optimum operating
point. Note that the additional low-pass filter is not an a-priori
requirement. Its significance will be shown later.
IV. DEMODULATION STRATEGY
While the amplitude modulation principle and the application
of a small-band resonance filter are reasonable and necessary to
obtain reliable measurement results, the design of the integrated
controller itself as well as of the rest of the external front-end
opens several degrees of freedom and possibilities for optimiza-
tion. A key component of the signal path is the demodulator.
Essentially, there are three alternatives to extract the baseband
signal from the carrier.
• Peak rectification was employed for a discrete prototype
realization and yielded satisfactory results [1]. However,
in view of the system requirements set up in Section II,
this is only a poor and inappropriate solution. First, it re-
quires an additional broadband (unity gain bandwidth of
more than 100 MHz) pre-amplifier to cope with the small
input signal levels of less than 50 mV. For an integrated
solution, this amplifier ought to be included in the input
stage of the controller, which is hard to achieve in a stan-
dard CMOS process given the extended temperature range
of an automotive sensor located in the engine compart-
ment. Furthermore, such an amplifier is highly susceptible
to input noise and requires a fairly high amount of supply
current. Finally, peak rectification inherently has a large
bandwidth, which renders the noise suppression by pas-
sive external filters inefficient.
• An alternative is to sample the AM signal around the max-
imum of the carrier oscillation. This technique requires
fast but very low impedance switches, which are not avail-
able in CMOS technology. Thus, a short aperture time
would most likely not be sufficient to charge the sampling
capacitance, which itself has to be substantially large to
offer sufficient noise immunity and to cope with leakage
currents. The use of an input pre-amplifier as impedance
converter could remedy the situation, but we would face
the same problems as with peak rectification.
1330 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 51, NO. 6, DECEMBER 2002

• A synchronous demodulator integrates the signal over a

half-period. In this case, high-impedance switches are suf-
ficient, which is beneficial for a compact implementation.
Together with the integration capacitors, the switches form
an additional low-pass filter suppressing high-frequency
noise even further. Consequently, this approach fits the
properties of the sensor best, and therefore is the method
of choice.
Owing to the inherent closed-loop measurement approach, we
have no troubles achieving synchrony between the stimulus and Fig. 3. Circuit diagram of the improved sensor front-end.
the demodulator control signals. The main problem with the de-
modulator is its sensitivity to a phase shift between the input
The signal voltage at the resonance filter is
AM signal and the clock controlling the switches. We get an
optimum output only if we integrate between successive zeros
of the input signal. This sensitivity could be alleviated with a (1)
four-quadrant demodulation technique. This solution, however,
requires a substantially higher implementation effort. Above all,
it needs two complete demodulators controlled by two clocks with the abbreviation /( , where
with a phase shift of precisely 90 . The two input signals should
be buffered and the demodulator outputs combined to obtain the
final result. This approach is useful when we have to deal with an (2)
a priori unknown amount of phase shift introduced in the signal
path. In the application considered here, we have well-defined is the output voltage of the original front-end and
and highly invariant conditions, and therefore a four-quadrant
method is too expensive in terms of silicon area. In addition, the
higher system frequency needed to generate the two clocks with (3)
precise phase offset of 90 leads to excessive power consump-
tion. Consequently, we have to get by with a simple demodu-
is the respective output impedance. The output signal at the
lator.
low-pass filter is found to be

V. IMPROVED FRONT-END
A basic property of the external front-end is that the reso-
nance filter in conjunction with the sensing capacitance shifts
the signal by 90 . Hence, the demodulator would produce no
output signal because of integrating the AM signal between suc-
cessive extrema. To shift the clock of the demodulator is not rea-
sonable for the same reasons as given above. A suitable way to
circumvent the problem is to add an external (passive) low-pass
filter providing an additional phase shift. Both system simula-
tion and measurement results showed that the insertion loss is
acceptable if limited to some 3 dB.
Slew-rate control is basically achieved via a limitation of the
current driving capabilities of the off-chip drivers generating the
stimuli. The main effect of the slew-rate limitation is a phase
shift in the signal path, i.e., the stimuli are delayed with respect
to the system (and demodulator) clock. In addition, we can ex-
pect an internal combinatorial delay between the clock and the
ideal stimulus signal. These effects allow for the use of a simple
first-order low-pass filter in the front-end. Fig. 3 shows the re-
spective circuit diagram. The variable capacitor designates the
capacitance of one sensor segment. The inductance is printed
on the PCB. The resistance sums up all losses in the resonance
circuit and is chosen so as to correctly model the quality factor
, which is about 16 in the concrete imple-
mentation. The capacitor decouples the different dc levels at
the resonance circuit and the demodulator input and is chosen
several orders of magnitude larger than . the relatively complex circuit and the rather long time constants
(4)
In contrast to a second-order filter that has to be used in case of
stimuli with unlimited slew-rate [6], the circuit shown in Fig. 3
causes lower additional attenuation. Still, the added benefit of
a low-pass filter, i.e., the suppression of high-frequency noise,
is retained. The inherent band-pass characteristic of the entire
front-end also at high frequencies is a major improvement of
the original circuit presented in [1], which consisted only of the
sensor capacitance and the resonance filter. As can be seen from
the transfer function (2), this configuration is tantamount to a ca-
pacitive divider without significant noise-shaping capabilities.
Fig. 4 shows the frequency response of the entire front-end with
the component values
H pF fF
nF pF (5)
The result clearly displays the difference between the original
and the improved version.
VI. SYSTEM SIMULATION
A straightforward analog simulation of both front-end and
demodulator requires excessively long computing times due to
SAUTER AND KERÖ: SYSTEM ANALYSIS OF A FULLY-INTEGRATED CAPACITIVE ANGULAR SENSOR 1331

Fig. 4. Frequency response of the external front-end up to the resonance filter (upper curve) and for the entire filter (lower curve). The sensor itself and the
resonance filter form a capacitive voltage divider; therefore, high frequencies are not attenuated in the upper curve.

of the filters. Being interested primarily in the steady-state be-

havior of the circuit, we prefer to investigate a semi-analytical
model instead. To that end, we describe the stimulus applied to
the sensor and the signals returned by the front-end by means of
a simple Fourier synthesis. The stimulus is modeled as a simple
square wave function applied to a first-order low-pass filter

(6)

where is the filter’s time constant. In the actual implementa-

tion, ns. This filter mimics the slew-rate limitation of the
output driver and especially the phase shift introduced by this
behavior. We thus have in general for any signal

(7)

with as spectrum of the respective signal and as car-

rier frequency. Fig. 5 shows the input and output signals ob-
tained. Thanks to the band-pass nature of the front-end, a few
harmonics already yield satisfactory results. The output signal
in principle coincides with the clock used to control the de-
modulator. In our model, the demodulator integrates the signal
starting at for half a period. It is evident that the result of
the integration is optimal when the signal is integrated between
successive zeros, i.e., when the signal has a zero at . In the
actual implementation, however, there will be a delay between
the demodulator clock and the stimulus generator. Most likely,
this delay will be negative, which means that the stimulus will
be retarded with respect to the clock. Consequently, the integra-
tion will start even earlier than shown in Fig. 5.
To evaluate the sensitivity of the demodulator to frequency
variations and internal delays, we model the operation of the
Fig. 5. Input signal (upper graph) and output signals (lower graph) obtained
from the analytical model of the sensor system. The low-pass behavior of the
stimulus models the slew-rate limitation. The lower graph shows the signal after
the resonance filter (with larger amplitude) and after the additional first-order,
low-pass filter. In an actual implementation, the system clock will be slightly
ahead of the stimulus.
demodulator by integrating the output signal shown in Fig. 5
over a half-period. Frequency variations will affect the signal
because of the filter characteristic. Not only will the amplitude
change, a change in the phase shift will have an even stronger
impact on the integration result. As described in the previous
section, internal delays (that may vary by a factor of 2) also in-
fluence the output of the demodulator. While the internal delay
cannot be compensated for dynamically, the controller adjusts
the carrier frequency so as to obtain the maximum signal at
1332 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 51, NO. 6, DECEMBER 2002
Fig. 6. Demodulator output depending on the carrier frequency and the delay
between stimulus generator and demodulator clock. Negative delays reflect the
situation in the actual integrated solution. The optimum performance is reached
0
at a delay of roughly 6 ns.
the demodulator output. With two independent parameters af-
fecting the output signal, the question arises whether an op-
timum can always be found to ensure a stable operation of the
frequency-tracking algorithm. A simple model of the demodu-
lator
(8)
includes the phase shift due to internal delays. The signal to
be integrated is inserted from (7) and (4) and has the form shown
in Fig. 5. This model will certainly not return accurate absolute
values, but suffices to judge the overall behavior. Fig. 6 shows
a typical result. We see that there is indeed a pronounced max-
imum, so the adjustment of the frequency will work. A series of
simulations also showed that the position of the maximum can
be shifted over a large range, depending on the filter parame-
ters. Note that the ideally symmetric shape of the demodulator
output with respect to frequency variations becomes more and
more asymmetric as we deviate from the peak due to changes
in the internal delay. It is, therefore, desirable to estimate the
delay (via simulations based on the controller layout) and select
the filter parameters accordingly.
Along with the tolerance analysis the simulation also pro-
vided valuable information on the maximum allowable step size
of the NCO. The total number of the steps should be as small
as possible to keep the implementation simple. Still, the NCO
has to cover the frequency range defined by the production tol-
erances of the external filter components on one side as well as
by the temperature drift of the NCO itself on the other side. A
worst-case analysis showed that 32 steps with an average step
size of around 150 to 200 kHz suffice to produce a reasonably
fine grid.
In the actual implementation, the inductance ( in Fig. 3) was
realized as a printed coil and the filter capacitor solely by the
parasitic input capacitance of the demodulator input pad. Hence
only the filter capacitor , the coupling capacitor and the
series resistor were needed as additional components. This
resulted in a sufficiently high quality factor of at least 15 for the
whole circuit. The controller shown in Fig. 2 was integrated in a
single ASIC. The actual controller core has a Harvard architec-
ture optimized according to the operations needed for the mea-
surement algorithm [4]. Therefore, the whole ASIC requires a
silicon area of only about 2.5 mm .
VII. CONCLUSION
We have shown how to optimize the design of an integrated
capacitive sensor system with respect to implementation
efficiency and, equally important, to robustness. The system
analysis and simulation were done using simple but efficient
analytical time domain models. Compared to a conventional
SPICE simulation, this approach needed slightly more prepara-
tion time. The simulation itself, however, was some two orders
of magnitude faster, because it focused on the steady-state
behavior and did not require the inclusion of long initialization
and settling times. The short simulation times allowed for a
thorough parametric analysis of all system configurations in
question.
Particular emphasis was given to the combination of the de-
modulation strategy and external filtering. The analysis of the
front-end together with the proposed demodulator confirmed the
usefulness of the system design and yielded remarkable results.
First, a synchronous demodulator complements ideally the high
impedance of the capacitive sensor. In addition, the inherent in-
tegration performed by the demodulator helps to suppress noise.
Further noise shaping is provided by an external resonance filter
that also serves as an inexpensive reference for the system clock.
Finally, a simple low-pass filter optimizes the performance of
the demodulator, avoiding the need for complicated integrated
clock shifters. This additional filter constitutes a considerable
improvement of the original front-end structure that used only
the resonance filter. This approach is sufficiently robust and
works also if the comparatively large tolerances due to process
variations are taken into account. Likewise, the quality of the
demodulated base band signal will not be affected by delay vari-
ations. The simulation results were also confirmed by an imple-
mentation of the controller now used in series production.
REFERENCES
[1] G. Brasseur, “Modeling of the front end of a new capacitive finger-type
angular position sensor,” IEEE Trans. Instrum. Meas., vol. 50, pp.
111–116, Feb. 2001.
[2] T. Fabian and G. Brasseur, “A robust capacitive angular speed sensor,”
IEEE Trans. Instrum. Meas., vol. 47, pp. 280–284, Feb. 1998.
[3] N. Kerö and T. Sauter, “Design of an integrated angular sensor system,”
in IEEE Instrum. Meas. Technol. Conf. (IMTC), Budapest, Hungary,
May 21–23, 2001, pp. 433–436.
[4] N. Kerö, H. Nachtnebel, and T. Sauter, “Optimized architecture for a ca-
pacitive angular sensor system,” in 27th Annu. Conf. IEEE Ind. Electron.
Soc. (IECON), Denver, CO, Nov. 29–Dec. 2, 2001, pp. 518–523.
[5] N. Kerö, H. Nachtnebel, H. Pommer, and T. Sauter, “Fault tolerant car-
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SAUTER AND KERÖ: SYSTEM ANALYSIS OF A FULLY-INTEGRATED CAPACITIVE ANGULAR SENSOR
Thilo Sauter (M’93) was born in Biberach,
Germany, in 1967. He received the Dipl.-Ing. and
doctorate degrees in electrical engineering from the
Vienna University of Technology, Vienna, Austria,
in 1992 and 1999, respectively.
From 1992 to 1996, he was a Research Assistant
at the Institute of General Electrical Engineering,
Vienna University of Technology, working in the
area of programmable logic and analog ASIC
design. Since 1996, he has been with the Institute
of Computer Technology, Vienna University of
Technology, where he is Head of the Center of Excellence for fieldbus systems
and leading the Factory Communications Group. His current research interests
are communication networks in automation and integrated sensor systems. His
present teaching activities include fieldbus systems, fault tolerant systems, and
the design of analog integrated circuits.
1333
Nikolaus Kerö (97) was born in Vienna, Austria,
in 1961. He received the Dipl.-Ing. degree in
electrical engineering from the Vienna University of
Technology, Vienna, in 1984.
He was a Research Assistant with the Institute of
General Electrical Engineering ,Vienna University
of Technology, and later on with the Institute of
Industrial Electronics and Material Science, Vienna
University of Technology, where he has been leading
the ASIC design activities since 1995. His current
research interests are design of analog and digital
integrated circuit and systems and hard- and software design for embedded
systems.