Beruflich Dokumente
Kultur Dokumente
Signal Chain
Prepared by
Matthew Hann,
Texas Instruments
Precision Analog Applications Manager
Presented by
Jose Duenas,
Precision Analog Product Marketing Engineer 1
Objectives
41
What is a Biopotential
An electric potential measured between living cells
5
What is a Biopotential
Every cell is like a little battery
Cell membrane
(lipids)
Intracellular medium/
Cytoplasmic fluid
Cell membrane
(lipids)
K+ is 30 to 50x
higher @ rest
Electrostatic
Force
9
What is ECG?
101
What is ECG?
A measure of the electrical activity of the heart
11
What is ECG?
ECG and blood pressure waves
12
What is ECG?
Actual ECG-normal
13
What is ECG?
ECG irregular tracings due to external artifacts
14
What is ECG?
Modeling the electrode interface
161
Analog Lead Derivation
ECG Einthoven Triangle, 1907
3 Body Electrodes,
3 Derived Leads = I, II, III
Einthoven’s Law
Assuming:
Then:
WCT RA LA LL
3
RRA RRA
18
RRA
RLA
VOUT = V(1-6) - VWCT
20
Analog Lead Derivation
Augmented Leads Derived via WCT to Provide
Enhanced Vector Information
21
Analog Lead Derivation
IEC60601-2-51—Diagnostic
Standards Electrodes Needed
1 Lead LA, RA
3 Lead LA, RA, LL
6 Leads LA, RA, LL
12 Leads LA, RA, LL, V1-6
22
Analog Lead Derivation
Different Lead Combinations Reveal Axis Deviation
and
I I
D e
R em
LA
tr
AVF AVF
Ex
A
D
al
I
R
m
I
A
or
D
AVF N
AVF
24
ECG Input Filtering, Defibrillation
Protection, and Isolation
251
ECG Input Filtering and Protection
Example: LEAD I Protection with Input Filtering
+Vs
-Vs
Patient
Protection 10 Ne2H Lamps/TVS Protect Cdiff = 10 x Ccm
-20k ohms Against Defibrillation
Voltages
26
System Block Diagram
271
System Block Diagram
Wilson INA MUX
I QRS and PACE
II dV/dt Detect
RA
III
LA
aVR
LL aVL
aVF
V4
V5
V6 28
The INA Front End
291
The INA Front End
Key Features of the INA Front End
30
The INA Front End
Ideal Simulation Circuit with Current and Voltage Noise
Sources
nV
V4 0 V n12 Vnoise
R21 1k R1 63.4k R3 63.4k
C20 330p
ECGp + +
INA 1
C9 47n - -
Vref C8 100p
Vref
R23 1k V5 0 R4 63.4k R5 63.4k
R24 1k
R25 1k R22 100k fA
In12 In_fA
31
The INA Front End
Simulation Showing Output-Referred Total RMS Noise
vs. Bandwidth (G = 1-10)
-Vdif Vin-
2+
Va1
+ Noise may NOT necessarily
- 150k 150k
A1
increase linearly with gain
50k
(INA or PGA topology
VCM
Rg 1k
- A3 Vout
+ +
dependent)
50k
- 150k 150k
T 32.00u
+ A2
+
Vdif Va2
Vin+ 28.00u
2
24.00u
16.00u
12.00u
8.00u
4.00u
0.00
1.00 10.00 100.00 1.00k
Frequency (Hz)
32
The INA Front End
TINA Simulations Showing Output-Referred ECG Signal
(G = 1-10)
Snapshot of R
Wave from
ECG Waveform
T 2.51
Voltage (V)
2.50
(1) (2)
ECGp 52k + +
33p
33p
100k
- - Vref
330p
Vref
33p
+
47n
ECGn
33p
100n
+
-
-150m
VCC
+
63.4k 63.4k
1k OPA333
52k
Vout[G = 1]
2.50
2.50
Vout[G = 3]
Vout[G = 6]
Integrator Saturates from
Increased Gain, Vout of the
2.50
2.50 INA pulls away from Vref
Vout[G = 8]
2.49
2.71
Vout[G=9]
2.70
3.01
Vout[G=10]
3.00
VCM + ECGp +
VOSelectrode1
(ECGp –ECGn)*Gain
VCM + ECGn +
VOSelectrode2
ECGn
C5 33p
C6 33p
+
INA 1
Vref ECGp + + +
C9 330p
Vout
C8 33p
- - -
+
C4 47n
C7 33p
ECGn
V4 0
R10 63.4k R11 63.4k CCn 1u Vref
R7 52k
Vref
R13 10M
38
The INA Front End
INA Gain = 1-1000 with VREF = 2.5V AC Coupled
3.06
2.79
2.52
Voltage (V)
2.25
1.98
1.71
ECGp
V CM V CM Gain
CMRR 20log 10 20
V OS V out
V CM
Vout ECGp ECGn VOSelectrode VOSOPA Gain
CMRR
20
10 40
The INA Front End
What is CMRR? Why is it Important in ECG?
RP1
ECGp CC1
The INA includes the
R and C and must be
Amp considered in the
overall CMRR Analysis
VCM
ECGn CC2
RP2
•Mismatch in Rp and Cc
causes a differential
signal error
2 2
•Even a 1% tolerance
Rp1 Rp2 on Cc cause a 20dB
Vdiff_actual Vinp Vinn
2 2 attenuation in CMRR
Rp1
j
Rp2
2 2 j
Cc1 Cc2
41
The INA Front End
50/60Hz Common Mode Simulation Circuit with 1µF
Coupling Capacitors Mismatched
C5 33p
V+
RG
C9 330p Vout
R1 20k
Ref
Out
C8 33p
C4 47n RG
+
V-
C7 33p
VCM V4 0
C12 1u
- U1 INA333_C
R10 63.4k R11 63.4k
R7 52k
Vref
R13 10M
42
The INA Front End
Plot of CMRR vs. Frequency for .01 - .5% Coupling
Capacitor Mismatch
T -40.00
.5% Mismatch
-60.00
Voltage (V)
-80.00
0% Mismatch
-100.00
100.00m 1.00 10.00 100.00
Frequency (Hz)
43
The INA Front End
Plot of ECG Response to 5Hz CM Input Signal (0%-
.5%) CC Mismatch
T 2.51
Lower Frequency
Signals Couple
Directly Into the ECG
Signal to the Output
Voltage (V)
2.50
0.00 400.00m 800.00m
Time (s) 44
The INA Front End
Plot of ECG Response to 50/60 Hz CM Input Signal
2.50
0.00 400.00m 800.00m
Time (s)
45
The Right Leg Drive Amplifier
461
The RL Drive Amplifier
The RL Drive Amplifier Serves 2 Purposes: (1)
Common Mode Bias (2) Noise Cancellation
ECGp
CMnoise
CMnoise
ECGn
Average VCM is
*Tapping off center of split gain
Inverted and Fed resistor feeds the following
Back to RL; voltage to the RL Drive Circuit
Cancels 50/60Hz [(Vcm+ ECGP )+ (Vcm+ ECGn )]/ 2
noise = Vcm + (ECGp + ECGn )/2
47
The RL Drive Amplifier
Simulation Circuit for Response to 50/60 Hz CM Noise
Injection Source
VCC
NS3 2.5
NS
Vref
R1 1k C2 47n +
+
U1 OPA333
R15 1M -
R4 1k VCC
R8 63.4k R9 63.4k
C10 1u
+
R12 1M
C5 33p
C6 33p
ECGp +
V+
RG
C9 330p
RG1 10k Ref Vout
Out
+
C8 33p
ECGn
+
RG
Noise
V-
C7 33p
RG2 10k - NS
U3 INA333
R10 63.4k R11 63.4k
NS2 2.5
C4 47n
R2 1k R7 1k
Vref
R5 1M = Included for
NS1 2.5
NS TINA spice
R6 1k R3 10k
- - Convergence
U2 OPA333 U4 OPA333
+ +
+ Vref +
R14 1M
R13 1M
R16 1M
VCC VCC
48
The RL Drive Amplifier TINA
Simulation with NO RL Drive; CM Noise is Coupled to
Output
T 750.00u
ECGn
-150.00u
750.00u
ECGp
-150.00u
1.00
Noise
-1.00
2.51
Vout
2.50
0.00 665.73m 1.33
Time (s) 49
The RL Drive Amplifier
TINA Simulation with RL Drive; Output Noise is
Reduced
T 750.00u
ECGn
-150.00u
750.00u
ECGp
-150.00u
1.00
Noise
-1.00
2.51
Vout
2.50
5.46m 282.16m 558.86m
50
Time (s)
The RL Drive Amplifier
Analyzing the RLD Amplifier Loop
RG/2
•More Gain = Better CMRR RA
VCC
Sweep Feedback
Vref
Resistor Gain to
show Effects of +
+
R12 1M
V3 0
C5 33p
C6 33p
+
V+
RG
C9 330p
Vout
+
C8 33p
R17 1M
RG
V-
C7 33p
RG2 25k - U3 INA333
R7 52k
R_RLD 52k
VCC
NS1 2.5
R2 100k NS
RF 10k Vref V1 2.5
-
U4 OPA333
R3 10k +
+
R14 100k
-
V2 2.5
R16 10M
+
VCC
+
R13 100k
Vref
VCC
U2 OPA333
52
The RL Drive Amplifier
CMRR Plots vs. Gain in RLD Loop
T -80.00
RF = 10k
CMRR (dB)
RF = 100k
-100.00
RF = 1M
RF = 10M
-120.00
10.00 100.00
Frequency (Hz)
53
The RL Drive Amplifier
VCC
RL Drive Stability Simulation Circuit
Vref
Electrode +
+
R12 1M
Stability
C5 33p
C6 33p
+
V+
RG
C9 330p
RG1 25k Ref
C4 47n Out
C8 33p
V4 0
R17 1M
RG
V-
C7 33p
RG2 25k - U3 INA333
R7 52k
R_RLD 52k
VCC
R5 10M
Vref V1 2.5
R2 100k
L1 1G R3 10k -
U4 OPA333
- +
+
R14 100k
+
+ Vloop V2 2.5
Local RLD Loop is VoA VCC
Vref
Broken to Ensure
C1 1G
VCC
U2 OPA333
Proper Phase Margin
+
Electrode Resistance
54
The RL Drive Amplifier
RL Drive Simulation Showing Instability in the RLD
Feedback Loop
T 120.00
100.00
> 20dB/dec ROC (Rate of
80.00 Closure) = INSTABILITY
AOL
Gain (dB)
60.00
40.00
1/Beta
20.00
0.00
-20.00
1.00 10.00 100.00 1.00k 10.00k 100.00k 1.00M 10.00M
Frequency (Hz)
55
The RL Drive Amplifier
Using RLD Simulation to Compensate for 1/Beta
Variation With Electrode Resistance
T 120.00
100.00
Intersection
80.00 of 1/ß and
AOL curve > -
40dB/dec
Gain (dB)
60.00
40.00
Feedback Comp
Placed vs. Worst
20.00
Case Electrode
Resistance and
0.00 RLD AOL
-20.00
1.00 10.00 100.00 1.00k 10.00k 100.00k 1.00M 10.00M
Frequency (Hz)
56
The RL Drive Amplifier
RL Drive Stability Simulation Circuit of Feedback #1
VCC
Vref
+
+
U1 OPA333
R18 10M
R15 1M -
C2 47n
VCC
R8 63.4k R9 63.4k
R4 52k C10 1u
R12 1M
V3 0
C5 33p
C6 33p
+
V+
RG
C9 330p
RG1 25k Ref
V4 0C4 47n Out
C8 33p
R17 1M
RG
V-
C7 33p
RG2 25k - U3 INA333
R7 52k
R_RLD 52k
R2 100k -
Vref V1 2.5
Vloop -
+
+
U4 OPA333
VoA
R13 100k
+
Vref +
R14 100k
C1 1G
VCC
U2 OPA333 V2 2.5
R16 10M
VCC
+
Vin
57
The RL Drive Amplifier
RL Drive Stability Simulation Circuit of Feedback #2
VCC
Vref
+
+
U1 OPA333
R15 1M -
C2 47n
VCC
R8 63.4k R9 63.4k
V3 0 R4 52k C10 1u
R12 1M
C5 33p
C6 33p
+
V+
RG
C9 330p
RG1 25k Ref
C4 47n Out
C8 33p
V4 0
R17 1M
RG
V-
C7 33p
RG2 25k - U3 INA333
R7 52k
R_RLD 52k
R1 10M VCC
Vref
L1 1G R3 10k
R2 100k -
Vref V1 2.5
-
Vloop
+
+ U4 OPA333
VoA +
R13 100k
+
Vref R14 100k
C1 1G
VCC V2 2.5
R16 10M
U2 OPA333 VCC
+
Vin
58
The RL Drive Amplifier
RLD Stability Circuit with Compensated Amplifier
VCC
Vref
+
+
U1 OPA333
R15 1M -
C2 47n
VCC
R8 63.4k R9 63.4k
R4 52k C10 1u
R12 1M
V3 0
C5 33p
C6 33p
+
V+
RG
C9 330p
Vout
+
C8 33p
R17 1M
RG
V-
C7 33p
RG2 25k - U3 INA333
R7 52k
R_RLD 52k
VCC
R5 10M
NS1 2.5
R2 100k C3 3.3n NS
R1 10k Vref V1 2.5
-
U4 OPA333
R3 10k +
+
R14 100k
-
V2 2.5
R16 10M
+
VCC
+
R13 100k
Vref
VCC
U2 OPA333
59
The RL Drive Amplifier
RL Drive Stability Simulation of Separate Feedback
Paths
T 120.00
60.00
40.00
-20.00
1.00 10.00 100.00 1.00k 10.00k 100.00k 1.00M 10.00M
Frequency (Hz)
60
The RL Drive Amplifier
Compensated RLD Circuit Simulation of 1/Beta and
AOL Intersection
T 120.00
100.00
60.00
40.00
20.00
0.00
-20.00
1.00 3.16k 10.00M
Frequency (Hz)
61
The RL Drive Amplifier
Gain and Phase Margin Plots of Compensated RLD
Amplifier
T 120.00
100.00
80.00
Gain (dB)
60.00
Loop Gain Phase Margin
40.00 @ 0dB = 70 degrees
20.00
0.00
180.00
135.00
Phase [deg]
90.00
45.00
0.00
1.00 3.16k 10.00M
Frequency (Hz)
62
The RL Drive Amplifier
Step Response of RLD Amplifier and ECG Output
T 100.00m
Vin
-100.00m
2.55
VoA
2.45
2.80
Vout
2.20
0.00 5.00m 10.00m
Time (s)
63
The ECG Shield Drive
641
The ECG Shield Drive
Shield drive eliminates leakage to ECG Inputs
ECGP CP1
–
ECGN CP2
VCC/2
+ + + • Shield is driven to
– (VIN(+) — VIN(–)) /2
– – • Eliminates Leakage
from CP1 and CP2
VCC
NS3 2.5
NS
Vref
+
+
U1 OPA333
R15 1M -
VF2 VCC
R4 10k C2 47n R8 63.4k R9 63.4k
C10 1u
R12 1M
C5 33p
C6 33p
R5 1k +
V+
RG
C9 330p
Vref R1 10k Ref VF1
Out
C8 33p
C4 47n
RG
V-
C7 33p
R2 10k -
R7 1k U2 INA333
R3 10k R10 63.4k R11 63.4k
VF3
VCC
VinP
VinN
U3 OPA333
+
+
Effective -
L1 1T VF
C3 1T
Capacitance Vout
+
66
The ECG Shield Drive
AOL + 1/Beta Response of OPA333 Shield Drive and 1nF
Cable Capacitance
120.00
100.00
80.00
Gain (dB)
60.00
-40dB/decade Intersection
of AOL and 1/Beta =
40.00
UNSTABLE
20.00
0.00
-20.00
1.00 10.00 100.00 1.00k 10.00k 100.00k 1.00M
Frequency (Hz)
67
The ECG Shield Drive
TINA Simulation Circuit for Stabilized OPA333 Shield Driver
VCC
NS3 2.5
NS
Vref
+
+
U1 OPA333
R15 1M -
VF2 VCC
R4 10k C2 47n R8 63.4k R9 63.4k
C10 1u
R12 1M
C5 33p
C6 33p
R5 1k +
V+
RG
C9 330p
Vref R1 10k Ref VF1
Out
C4 47n C8 33p
RG
V-
C7 33p
R2 10k -
R7 1k U2 INA333
R3 10k R10 63.4k R11 63.4k
VF3
VCC
VinP
U3 OPA333 C3 1T
R6 2k +
+
L1 1T VF
-
VG1
+
C1 1n
Vout
Shield Drive C11 1n
Compensation
Network R13 10k
68
The ECG Shield Drive
TINA Simulation Shows > 45 Degrees Phase Margin for
OPA333 Shield Driver
120.00
100.00
80.00
Gain (dB)
60.00
40.00
20.00
0.00
0.00
-45.00
Phase [deg]
-90.00
-135.00
-180.00
1.00 1.00k 1.00M
Frequency (Hz)
69
Lead Off Detection
701
Lead Off Detection
Lead Off Differentiates a Bad Lead from an Arrythmia
Body-Electrode VTH
VCC
Model
VREF
VTH
Voltage-Controlled
R13 10M
VCC
Switches Simulate VR
VF3
U1 TLV3701
Disconnected Lead +
+
R14 13.5M
VS
VCC
R6 1M
- +
R15 10M
VM1
+
VF1
-
R1 1k C2 47n -
SW1 1
VCC Vref
R8 63.4k R9 63.4k
C5 33p
R4 52k
C6 33p
+
NS1 2.5 V+
RG
C9 330p
NS RG1 10k Ref Vout
Out
C8 33p
RG
V- VS
C7 33p
C4 47n
RG2 10k -
R12 1M
U3 INA333
R10 63.4k R11 63.4k
+
SW2 1
R3 10M
R7 52k VF2
R2 1k VG1
+
VS2 VCC
+
R5 1M
R17 1M +
+
+ VG2
R21 52k VM2
R18 100k -
R16 10k - VCC
U5 OPA348
- U4 OPA348
+
R19 1M
+
+
R20 1M
VCC
VCC Vref
72
Lead Off Detection
TINA Simulation Results for Lead Off Detect
T 2.00
Vswitch
0.00
4.99
VComparator
0.00
401.55u 559.69u 717.83u
Time (s)
73
Pace Detection
741
Pace Detect
Pace Maker Pulse Specifications
dp
ap
t0
ao
ap = Amplitude (2-700mV)
ao = Overshoot
dp = Pulse Width (.1-100us)
t0 = Overshoot Time Constant (4-100ms)
Rise Time = 100us 75
Pace Detect
Pace Detect Circuitry in Parallel with ECG Signal Path
VCC
C2 100p
R5 2M
Vpace Pos VCC
47n
VCC Vref
+ R4 100k
63.4k VECG_block +
TLV3701
+
+
ECGp
R6 2M
52k
+
33p
V+ Vout
- 10n R2 1k -
+
10k
RG
C9 330p
Ref +
Vpace1
Out + - -
+
OPA348
R1 100k
47n OPA348 VPDetect
ECGn RG
R17 1M
V- +
VCC +
10k
R3 1M
- VCC
33p
U5 INA333 -
Vpace Neg 63.4k
VCC
52k
100k
VCC Vpace2
R7 2M
+ +
+
Vref +
10n
- TLV3701
•AC Coupled Input Blocks ECG
R8 400k
R20 100k
+
+
PACER Signal Detected
R23 1M
+ U6 OPA348
VCC
VCC Vref •Separate PACER Processing
Circuitry
76
Pace Detect
PACE Signal Extracted From PACE + ECG Waveform
2.51
Vout
2.50
1.00m
Vpace Pos
0.00
153.93m 209.78m 265.62m
Time (s)
77
INA Post Gain and Filtering
781
INA Post Gain and Filtering
Choice of High Gain + SAR ADC OR Low Gain + 24 bit Delta
Sigma ADC
At
At HighGain
High Gain At
At At
At Lowgain
Low gain At
At
electrode
electrode withlow
with lownoise
noise ADC
ADC electrode
electrode ADC
ADC
amplifiers
amplifiers
x200 x5
Amplitude
Amplitude
Amplitude
Amplitude
Noisefree
Noise free
Dynamicrange
Dynamic range
Noise
Noisefree
free
Dynamic
Dynamicrange
range
ADC
ADC
Amp
Amp Noise
Noise
noise
noise
Signal
SignalChain
Chain Signal
SignalChain
Chain
a)
a)Using
Usingaalow
lowresolution
resolutionADC
ADC b)
b)Using
Usingaahigh
highresolution
resolutionADC
ADC
79
INA Post Gain and Filtering
INA + Post Gain Amp With Differential Noise Source
R21 2M
VCC
Noise NS5 2.5
+ NS
Vref
C1 10p
R1 1k C2 47n +
+
U1 OPA333
R22 1M -
R18 2M
R4 1k VCC
R15 2M
ECGp
C10 1u
C5 33p
R23 1M
C6 33p
+ VF1
-
NS4 2.5
V+ Vref
NS
RG U5 OPA333
C9 330p RG1 10k Ref Vout
+
Out +
+
C8 33p
ECGn RG
R20 2M
V-
C7 33p
R17 10M
RG2 10k - NS VCC
U3 INA333
R10 63.4k R11 63.4k
NS2 2.5
C4 47n
R12 1M
R2 1k R7 1k
R5 1M
NS1 2.5
NS
R6 1k R3 10k
- -
U2 OPA333 U4 OPA333
+ +
+ Vref +
R14 1M
R13 1M
R16 1M
VCC VCC
80
INA Post Gain and Filtering
Noise Coupled Differentially Translates to Output
1.00
50/60Hz
-1.00
4.33
2.16
0.00 187.93m 375.86m
Time (s)
81
INA Post Gain and Filtering
Use Filter Pro to Design a 50/60 Hz Notch
82
INA Post Gain and Filtering
ECG Circuit with Added 50/60Hz Notch + Post Gain
VCC
U3 OPA333
Vref
R21 2M
+
+
R1 1k C2 47n Noise
+ -
C1 10p Vref
R19 10k R18 1M
R4 52k VCC C11 1u
VCC
R15 2M
R8 63.4k R9 63.4k
+
ECGp
R30 1M
U4 OPA348 -
VF1
C5 33p
C6 33p
+ Vout + U7 OPA378
NS4 2.5
V+ +
NS
RG C12 330n +
+
C9 330p
C8 33p
R29 8.06k
R17 1M
ECGn RG R26 8.06k VCC
R20 2M
C7 33p
V- R24 64.9k
RG2 10k - U5 INA333_C
C3 330n
R22 1M
R10 63.4k R11 63.4k
R25 64.9k
C4 47n
R12 1M
NS1 2.5 -
R2 1k R7 52k C10 1n
NS U1 OPA348
R3 10k Vref NS
+
+
-
R27 8.06k
R5 1M
NS3 2.5
U6 OPA348
+ VCC
+
R14 1M
R6 1k
- R28 8.06k
R16 1M
VCC
R23 1M
U2 OPA348
+
+ Vref
R13 1M
VCC
83
INA Post Gain and Filtering
Plots of ECG Output with Gain and 60Hz Notch
968.42m
Noise
-1.00
3.40
Vout_Filter
2.37
2.51
Vout_PostGain
2.50
2.51
Vout_INA
2.50
370.88m
ECG (V)
247.25m
123.63m
0.00
400m 417m 433m 450m 467m 483m 500m 517m 533m 550m
Time (s)
Elec 8
100KSps
` •Reduced Hardware
•Filter Requirements Relaxed
INA
Elec 9
•Lower Power
RL
•Lower System Cost
x5
Using a high resolution ADC
100 Hz
•Electrode Offset Info
Elec 1 ADS1258 Retained
INA
Elec 2
Patient
Protection,
Simple RC filter DOUT
MUX
Lead
selection
ADC
24 bit,
Elec 8 INA 100KSps
`
Elec 9
RL
86
INA Post Gain and Filtering
Block Diagram of INA Gain, Simple RC Filter, and ADS1258
x5 x5 100 Hz 100 Hz
Elec 1 Elec 1 ADS1258 ADS1258
INA INA
lec 2 Elec 2
Patient Patient
Protection, Protection, DO
Simple RC filter
Simple RC filter MUX MUX DOUT
Lead Lead
selection selection
ADC ADC
24 bit, 24 bit,
lec 8 Elec 8 INA INA 100KSps
`
100KSps
`
Elec 9 Elec 9
RL RL
87
ADS1298 Introduction
881
The ADS129x
The All-In-One ECG Chip
89
ADS129x
Input Amplifier Specifications for Single Channel AFE
CH1P
+
PGA +
- BUF
-
RLD 24-bit
Delta-Sigma
ADC
+
+
BUF
-
PGA
CH1M -
CH1P AFE
CH1M +
ADC
91
ADS129x
Programmable Data Rates for Low Power and High
Resolution Modes
92
ADS129x
MUX Selects Inputs to Front End PGA
• Normal Electrode
• Input Shorted
• RLD Input
• VDD
• TMP Sensor
• Input Test Signal
93
ADS129x
Wilson Central Terminal
Wilson Central
Voltage
0.333(RA+LA+LL)
Augmented Lead
Voltages
0.5(RA+LA)
0.5(LA+LL)
0.5(RA+LL)
VCM1 = AVDD/2
+/-VCM2 + VS AVDD
+ VO2
RS
-
R1 R2
50K 20K
+ 220K
+
RLDM3 50K
CH3N
- 220K
-
R1
RLDM4
CH4N
CH5P + 220K
RLD_REF
RLDP5 /RLDREF_INT
- 50K 220K + CH6P
RLDP6
20K
50K - R2
50K 20K
+ 220K +
RLDM5 50K
CH5N
- 220K
-
RLDM6 CH6N
CH7P + 220K
RLDP7
- 50K 220K + CH8P
RLDP8
20K
50K - All switches can be controlled
50K 20K
+ 220K
+ by register settings
RLDM7 50K
CH7N
- 220K
-
RLDINV RLDM8
CH8N
Cext
Rext
10M
- *Multiple PGA Outputs Can Be Switched to
264pF RLDREF_INT
RLD
RLDOUT
AMP
+
AVDD - AVSS
Derive Inverting RLD
RLDREF_INT WCT_TO_RLD 2
RLDREF WCT
96
ADS129x
RLD with Multiple Devices
To Input Mux
To Input Mux
Device 1 Device 2 Device 1
To Input Mux
Power Down
- - -
RLD RLD RLD RLD RLD RLD RLD RLD RLD RLD RLD RLD
IN REF OUT INV IN REF OUT INV IN REF OUT INV
To Input Mux
To Input Mux
Power Down Power Down
- - -
RLD RLD RLD RLD RLD RLD RLD RLD RLD RLD RLD RLD
IN REF OUT INV IN REF OUT INV IN REF OUT INV
- 50K
01xx
500K + From CH4P<
xx01
20K 50K -
50K 20K
+ 500K + PACE_OUT1 VREFCM ADS129x
01xx 50K
>From CH3N
- 500K
-
100K
xx01 250K
From CH4N<
>From CH5P + 500K CH1P
PDB_PACE_ODD
- 50K
10xx
500K + From CH6P< + 250K
xx10 CH7P
20K
50K - PACE
AMP - 250K
PACE_ODD[0:1]
50K 20K
+ 500K +
CH1M
10xx 50K
>From CH5N
- 500K
-
100K 250K
CH7M
xx10 From CH6N<
>From CH7P + 500K
PACE_OUT2 VREFCM
11xx
- 50K 500K + From CH8P<
100K
xx11
20K
50K - 250K
CH2P
50K 20K PDB_PACE_EVEN
+ 500K + + 250K
50K
>From CH7N
- 11xx
VREFCM
500K
- PACE
CH8P
PACE_EVEN[0:1]
xx11 AMP - 250K
From CH8N<
100K
CH2M
PDB_PACE + x x 0 0 Channel #1
0 0 x x Channel #2
TESTP_PACE_OUT1 PACE -
AMP x x 0 1 Channel #3
0 1 x x Channel #4
200K
x x 1 0 Channel #5
1 0 x x Channel #6
x x 1 1 Channel #7
1 1 x x Channel #8
98
ADS129x
Lead Off Detection
AVDD AVSS
LOFF_FLIP
FLEAD_OFF[0:1]
FREQ = DC, FDR/2 or FDR/4
FLEAD_OFF[[1:0] VX
Patient Skin – Electrode Patient
Contact Model Protection Anti-Aliasing Filter
>
Resistor <512KHz
< R1 ~ 10M
Z1
LOFF_STATP
LOFF_SENSP LOFF_SENSM
47nF
& VLEAD_OFF_EN & VLEAD_OFF_EN
R2 VINP
51K
+
100K
EMI
Filter
To ADC
51K R2 VINM
100K
-
47nF LOFF_SENSP LOFF_SENSM
Z2 & VLEAD_OFF_EN & VLEAD_OFF_EN LOFF_STATM
LOFF_FLIP
4-bit COMP_TH[2:0]
25, 17.275, 12.5, & DAC
6.25nA
Z3 AVSS
AVDD
ILEAD_OFF[0:1]
51K R3
RLD OUT
100K 99
ADS129x
Respiration Testing Measures the Change in Thoracic
Impedance with Inhalation of O2
ADS129x ADS129x
PATIENT’
PATIENT’ S CHEST
S CHEST RPROTEC RPROTEC
T E2 T
E4
100K 100K
RTHORAX
V
RPROTEC 64KHz
RPROTEC E1 T
T 100K
E3
100K
RTHORAX
RPROTEC
T
E1
100K
100
ADS129x
Respiration Functions
ADS129x
GPIO1
GPIO
GPIO2
RESPIRATION
RESP_OUT
RESP_MODE
Complex Impedance Phase Shifts
Between Modulator and
GPIO4/
RESP_PH_OUT Demodulator
RESP_PH [4:2]
101
ADS129x
Internal Voltage Reference
103
Questions?
1041
Acknowledgements
• Beraducci, Mark and Soundarapandian, Karthik. Sbaa160, Application Report: Analog
Front End Design of ECG Systems Using Delta-Sigma ADCs. March 2009.
• Brown, John --Burr Brown Strategic Marketer, general information
• Brown, John and Joseph Carr. Introduction to Biomedical Equipment Technology.
Prentice Hall Inc. New Jersey. 1981, 1993.
• Dubin, Dale. Rapid Interpretation of EKG’s. Cover Publishing Company. Fort Myers.
2000.
• Fraden, Jacob. Handbook of Modern Sensors—Physics, Designs, and Applications.
Advanced Monitors Corporation. San Diego. 2004.
• Franco, Sergio. Design with Operational Amplifiers. McGraw-Hill Inc. NY. 1988.
• Fredericksen, Thomas M. Intuitive Operational Amplifiers. McGraw-Hill Inc. 1988.
• Graeme, Toby, Huelsman. Operational Amplifiers—Design and Applications. McGraw-
Hill Publishing Company. New York. 1971.
• Gray, Paul R. and Meyer, Robert G. Analysis and Design of Analog Integrated Circuits.
John Wiley & Sons. New York. 1977
• Green, Timothy - Linear Applications Manager, general information
• Kuehl, Thomas--Linear Applications Engineer, general information
• Norton, Harry N. Sensor and Analyzer Handbook. Prentice Hall Inc. New Jersey. 1982.
• Soundarapandian, Karthik--Over sampling Manager, general information
105