phys. stat. sol. (a) 205, No. 4, 679–694 (2008) / DOI 10.1002/pssa.
200723528
Tunneling phenomena
in carbon nanotube
field-effect transistors
Joachim Knoch*, 1 and Joerg Appenzeller2
1
IBM Zurich Research Laboratory, Säumerstrasse 4, 8803 Rüschlikon, Switzerland
2
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
Received 29 October 2007, revised 7 January 2008, accepted 17 January 2008
Published online 19 March 2008
PACS 73.40.Gk, 73.63.Fg, 85.30.Tv, 85.35.Kt
*
Corresponding author: e-mail jkn@zurich.ibm.com, Phone: + 41 44 724 8992, Fax: + 41 44 724 8966
In the present article we will discuss the electronic trans-
port properties of carbon nanotube field-effect transistors
(CNFETs). Three different device concepts will be studied in
more detail: Schottky-barrier CNFETs with metallic source
and drain contacts, conventional-type CNFETs with doped
nanotube segments as source and drain electrodes and finally
a new concept, the tunneling CNFET. As it turns out, tunnel-
ing phenomena play a prominent role in all three CNFET de-
1 Introduction The enormous evolution of informa-
tion technology has been made possible to a large extend
by modern CMOS technology. In particular, the continued
down-scaling of the metal–oxide–semiconductor field-
effect transistors (MOSFET) has led to tremendous per-
formance improvements over the past three decades. The
very successful route of scaling, however, runs into severe
problems in the very near future. This is the reason why re-
searchers have been looking intensively at alternatives to
the conventional bulk silicon MOSFET by exploring new
materials as well as new device architectures as replace-
ments and/or add-ons to current CMOS technology. In re-
cent years, carbon nanotubes have attracted a great deal of
attention as building blocks of a future nanoelectronics ow-
ing to their unique electronic and structural properties ena-
bling in principle ultimately scaled FET devices [1–3].
Figure 1(a) shows an SEM of a typical research device
with metallic source–drain contacts and a large area back-
gate; representative output characteristics of such a carbon
nanotube field-effect transistor (CNFET) are shown in
Fig. 1(b). The device exhibits a linear increase of current
for small and current saturation for large drain–source bias.
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Feature Article
signs and determine their electrical behavior to a large extend.
In addition, the one-dimensionality of the electronic transport
makes them ideally suited for novel device architecture such
as the tunneling CNFET. Analytical as well as simulation re-
sults will be given and compared with each other and with
experimental data in order to explain the different influences
on the electronic transport in CNFETs and thus on the device
behavior.
© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Consequently the transport in CNFETs has been inter-
preted in terms of conventional MOSFETs. However, the
appearance of short channel-like effects in electrostatically
well-tempered devices [4] has stimulated further investiga-
tions of the electronic transport in CNFETs. Substantial
progress has been made recently in terms of understanding
the transport properties as well as the role of the contacts
on the behavior of CNFET devices [5–8]. Using charge
transfer doping together with a dual-gate structure, band-
to-band tunneling was investigated and new device con-
cepts such as tunneling CNFETs have been realized [9, 10].
Significant progress has also been made regarding the in-
tegration of tubes into electronic circuits [11, 12]. Recently,
a ring-oscillator fabricated on a single nanotube has been
demonstrated for the first time. The device exhibits a
strongly improved frequency response compared to previ-
ous realizations [13]. Despite this very impressive progress
it should be noted that a future nanoelectronics based on
nanotubes would require to fabricate billions of CNFETs at
certain positions with each tube having the same electronic
properties on a small chip. Present technology is not yet at
this stage. Independent of all technology related aspects it
© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
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680
Joachim Knoch studied phys-
ics at Aachen University of
Technology, Germany, and
Queen Mary, University of
London, UK. He received the
M.S. and Ph.D. degrees from
Aachen University of Tech-
nology in 1998 and 2001, re-
spectively. From 2001 to
2002 he was with the Micro-
systems Technology Labora-
tory, Massachusetts Institute of Technology, USA,
where he was engaged in research on InP HEMT de-
vices. From 2003 through 2006 he was a Research Sci-
entist at the Research Center Juelich, Germany, where
he investigated electronic transport in alternative field-
effect transistors such as carbon nanotube FETs, ultra-
thin-body Schottky-barrier devices and MOSFETs
based upon strained silicon. Since December 2006 he
has been with the IBM Zurich Research Laboratory,
Switzerland, as a Research Staff Member. His current
interests include electronic transport in nanowire/tube
transistors as well as their potential for future device
applications.
Joerg Appenzeller received
the M.S. and Ph.D. degrees
in physics from the Techni-
cal University of Aachen,
Germany, in 1991 and 1995.
His Ph.D. dissertation inves-
tigated quantum transport in
low dimensional systems
based on III/V heterostruc-
tures. He worked for one year
as a Research Scientist in the
Research Center in Juelich, Germany, before he became
an Assistant Professor with the Technical University of
Aachen in 1996 working on electronic transport in car-
bon nanotubes and superconductor–semiconductor-
hybrids. From 1998 to 1999, he was with the Massachu-
setts Institute of Technology, Cambridge, as a Visiting
Scientist, exploring the scaling limits of Si-MOSFETs.
From 2001 until 2007, he had been with the IBM T.J.
Watson Research Center, Yorktown, NY, as a Research
Staff Member mainly involved in the investigation of
carbon nanotubes and silicon nanowires for a future
nanoelectronics. Since 2007 he has been Professor of
Electrical and Computer Engineering at Purdue Univer-
sity and Scientific Director of Nanoelectronics in the
Birck Nanotechnology Center. His current interests in-
clude novel devices based on nano-materials such as
nanowires, nanotubes and graphene.
© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
J. Knoch and J. Appenzeller: Tunneling phenomena in CNFETs
is fair to say however, that owing to their geometrical
smallness and their exceptional transport properties carbon
nanotubes are an ideal work-horse to study and explore
possible advantages of one-dimensional systems as active
channel material for ultimately scaled transistor devices.
The aim of this article is to investigate the electronic
transport in field-effect transistors based on carbon nano-
tubes and to discuss three different device architectures
with respect to their applicability. In particular we will
study tunneling phenomena appearing in these devices and
their impact on the electronic transport and device func-
tionality. To be specific, we will discuss electronic trans-
port in Schottky-barrier CNFETs (SB-CNFETs) with
metallic source and drain electrodes, conventional-type
CNFETs (C-CNFETs) with doped source and drain exten-
sion and tunneling CNFETs (T-CNFETs) where the modu-
lation of band-to-band tunneling is used for switching of
the device.
2 Modeling and simulation approach In this sec-
tion a general framework of a model for CNFETs and the
quantum mechanical simulations of their electrical behav-
ior will be introduced. Our model is rather general and ap-
plies to a variety of one-dimensional FET structures. Nano-
tube-specific properties are accounted for by material char-
acteristics such as the effective masses, the energy gap and
diameter. The simulations are based on a self-consistent
solution of the Schrödinger equation using the non-
equilibrium Green’s function formalism (NEGF) and the
Poisson equation as will be outlined in more detail below.
2.1 Device geometry and electrostatics We con-
sider in the following two different device geometries con-
sisting of a nanotube with diameter d nt and a gate oxide
thickness of dox as shown in Fig. 2: (a) displays a wrap-
gate architecture and (b) a back-gated, lateral device design.
In addition, devices with two different contact schemes are
investigated. First, doped nanotube portions that act as
source and drain contacts and second metallic contacts that
are deposited on top of a nanotube portion – called “side-
contacts” in the following (illustrated in Fig. 2(b)) – will
be studied. The use of side-contacts in the simulations re-
flects the experimental situation and it will become clear
below that a number of experimental observations can only
be explained with the assumption of side-contacts as
source and drain electrodes.
Although small, a real CNFET is nevertheless a three-
dimensional object and a three-dimensional calculation
should be employed in order to simulate its electrical char-
acteristics accurately which represents an enormous com-
putational burden. However, it is possible to describe the
electrostatics of ultrathin-body devices such as CNFETs by
a surface potential method which captures all relevant as-
pects related to the scaling of the gate oxide thickness d ox ,
the body (i.e. channel) thickness d nt and of course the ap-
pearance of short channel effects in laterally scaled devices.
The approach leads to a one-dimensional Poisson equation
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phys. stat. sol. (a) 205, No. 4 (2008)
1.5
(a)
1.0
| I d (mA) |
0.5
0.0
-1.0 -0.8
for the potential at the channel–dielectric interface Φ f ( x)
[14, 15] given by
d 2Φ f ( x) Φ f ( x) - Φ g - Φ bi e( ρ ± N )
- =- . (1)
dx 2 λ2 ε 0ε nt
Here, Φg and Φ bi are the gate and the built-in potential, re-
spectively. Furthermore, ρ is the density of mobile carriers,
and N is a constant charge background due to a doping of
the nanotube with either donors (‘+’-sign) or acceptors
(‘–’-sign). For constant charge density, Eq. (1) can be
solved analytically leading to a solution of the form
Φ f ( x) µ exp ( - x/λ ) showing that λ is the relevant length
scale for potential variations. This screening length λ is
a function of d nt as well as dox and reflects the device
geometry under consideration. For a wrap-gate device
structure as displayed in Fig. 2(a) it is given by
λ = ε nt d nt2 ln (1 + (2d ox /d nt ))/8ε ox [14] where ε nt ,ox are
the relative dielectric constants of the nanotube and the
gate oxide 1 . In the case of a planar gate as shown in
Fig. 2(b) we consistently found by comparison with ex-
periment that the screening length is rather of the form
λ = (ε nt /ε ox ) d nt d ox , which was originally derived for a
planar-gate, planar-channel geometry such as a single-
gated MOSFET on SOI [15]. The present approach based
on Eq. (1) has been successfully applied to a variety of
fully-depleted FETs such as silicon-on-insulator MOS-
FETs, nanowire as well as nanotube transistors [5, 16].
Since nanotubes are inherently small, cylindrical objects, a
wrap-gate device architecture based upon nanotubes as
active channel material yields very small λ without the in-
1 At the same time, Qtot is determined by the terminal volt-
Note that the difference between the expression for λ used here and in
Ref. [14], is due to the fact that in the present case Eq. (1) is derived for
the surface potential at the gate insulator – nanotube interface whereas in
[14] the potential in the center of the circular channel is calculated.
(a) (b)
gate oxide
gate
gate drain
dox
source
L silicon
dnt
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681
(b)
Vgs: 0V to -1.2V
step: -0.3V
Figure 1 (a) Electron micrograph of a CNFET.
(b) shows typical output characteristics.
-0.6 -0.4 -0.2 0.0
troduction of dopants. Hence, nanotubes seem to be ideally
suited for the realization of ultimately scaled devices from
the electrostatics point of view.
It has been noted that the electrical behavior of MOS-
FETs is determined by the potential maximum in the chan-
nel – called Φf0 in the following – that mediates the in-
jection of carriers from the source into the channel [17]
(see Fig. 3(a)). Solving Eq. (1) an expression for Φf0 can
be obtained by differentiation of the solution. For in-
stance, in the device’s off-state, an analytical expression
can be found if the channel length L is larger than λ
yielding Φ f0 ª 2 -(Φ bi + Φ g ) (Φ d - (Φ bi + Φg )) exp ( - L/ 2λ )
+ Φ g - Φ bi where Φ d = -eVds [15]. For ideal MOSFET (off-
state) performance Φf0 should not depend on Φd which is
attained if L
λ since then the first term can be neglected.
In this case, Φ f0 = Φ g + Φ bi implying that δΦf0 = δΦ g or
∂Φ f0 /∂Φg ª 1. As a result, the surface potential maximum
that determines the injection of carriers can be moved
one-to-one by the gate voltage yielding ideal turn-off char-
acteristics with an inverse subthreshold slope of
S = ln (10) ((∂I d /∂Vgs ) (1/I d )) -1 = kBT /q ◊ ln (10) ª 60 mV/dec,
where q is the electron charge. Furthermore, in the case
L
λ , ∂Φ f0 /∂Φ d ª 0, i.e. drain-induced-barrier-lowering
(DIBL) is efficiently suppressed. On the other hand, if
L ª λ so-called short channel effects (SCEs) appear with
∂Φf0 /∂Φg < 1 and ∂Φ f0 /∂Φ d > 0 giving rise to an S signifi-
cantly larger than 60 mV/dec and the appearance of DIBL.
A MOSFET can also be regarded as a combination
of different capacitors as illustrated in the upper part of
Fig. 3(a). The total charge Qtot in the channel is
-Φ f0 /q ◊ (Cox + Cs + Cd ) where Cs ,d are the source–drain
capacitances and Cox is the geometrical oxide capacitance.
ages, i.e. Qtot = CoxVgs + CsVs + CdVd + Qch where Qch is the
mobile charge injected by the contacts into the channel.
Then differentiating Φf0 with respect to Φg and Φd and not-
Figure 2 Device geometries consid-
dnt
ered in the following: (a) wrap-gate ar-
drain
drain
i dox chitecture with doped source – drain
electrodes and (b) back-gated, lateral
device design with metallic side-
back-gate
contacts.
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682 J. Knoch and J. Appenzeller: Tunneling phenomena in CNFETs

(a) Vgs (b)

Cox

E (eV)
Cs Cd
Vs
Vd Ef
Q ch
Ef D(E)

Vgs Figure 3 (a) Conduction band profile along the

D(E)
current transport direction displaying the poten-
F0f (Vgs ) tial maximum Φf0 . The top part shows the rele-
vant capacitances in a MOSFET. (b) Conduc-
tion band profile for two different Vgs with 1D
source channel drain density of states.

ing that q ∂Qch /∂Φ f0 = Cq one obtains (in the following we
neglect Cs for simplicity)
Cox Cd
δΦ f0 = δΦ g + δΦ d ,
Cox + Cd + Cq Cox + Cd + Cq
where Cq is the so-called inversion layer or quantum capaci-
tance (see next section for more details) [18]. In order to
suppress SCEs we required ∂Φ f0 /∂Φ g ª 1 and ∂Φ f0 /∂Φ d ª 0 .
From Eq. (2) it is then obvious that this is fulfilled if, both,
Cox
Cd and Cox
Cq in the device’s off-state. In a device
with L
λ , indeed Cox
Cd is the case. The second re-
quirement, however, needs more consideration.
2.2 The quantum capacitance In an electrostati-
cally well-behaved, fully depleted device the total gate ca-
pacitance is given by Cg = Cox Cq /(Cox + Cq ) where Cq is
again the quantum capacitance introduced above. On the
other hand Cg = ∂Qch /∂Vgs = q ◊ ∂Qch /∂Φ f0 ◊ ∂Φ f0 /∂Φ g . The
second term of this expression can be identified by com-
parison with Eq. (2) to be Cox /(Cox + Cq ). This means that
q ∂Qch /∂Φ f0 = Cq , i.e. the quantum capacitance is the
change of the channel charge with changing surface poten-
tial. In equilibrium (i.e. in an MOS capacitor) the channel
charge is given by the density of states, D( E ) , and the-
Fermi function and one obtains for Cq 2
∂Qch ∂f s ( E - Efs )
Ú tion of the electronic transport in CNFETs. To numerically
2
Cq = q µ - q d E D ( E )
∂Φ f0 ∂E
2
Note, that all capacitances are meant as per area in two-dimensions and
per length in 1D.
where Efs is the source Fermi level. This integral vanishes
in the device’s off-state and hence Cox
Cq as required
above. However, in the on-state of the transistor one ob-
(2) tains from Eq. (3) Cq ª q 2 D( Efs - Φ f0 ) meaning that the
quantum capacitance is proportional to the density of states
(DOS) within the channel. In a conventional bulk-silicon
MOSFET the DOS approaches the three-dimensional limit.
As a result, the DOS and hence Cq increase with increasing
Vgs . Hence, Cox < Cq and consequently the movement of Φf0
with changing Vgs tends to zero, i.e. ∂Φ f0 /∂Φ g → 0 , as is
well-known from a conventional MOSFET [19].
This situation can be very different in a one-
dimensional systems such as carbon nanotubes. In 1D, the
DOS is proportional to 1/ Ef - Φ f0 such that the so-called
quantum capacitance limit (QCL) can be achieved where
Cq1D < Cox (illustrated in Fig. 3(b)). In this case, the gate ca-
pacitance is dominated by Cq and consequently, ∂Φf0 /∂Φg
approaches unity even in the device’s on-state. As will be-
come clear below this has important consequences for the
functionality of CNFETs.
2.3 Electronic transport For the calculation of the
charge in and current through the nanotube we employ the
non-equilibrium Green’s function formalism. Together
with Eq. (1), our model allows the self-consistent calcula-
, (3)
compute the Green’s function we make use of Datta’s ap-
proach [20]. We consider a one-dimensional finite differ-
ence scheme with lattice constant a and nearest neighbor
hopping as illustrated in Fig. 4(a). A quadratic dispersion

Figure 4 (a) Conduction and valence band

of a p – i – p FET. Büttiker probes are at-
tached to a finite difference grid with lattice
spacing a. An effective mass approximation
is used; the complex band structure in the
gap is described with an energy-dependent
effective mass. (b) shows a gray-scale plot
of the local DOS.

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phys. stat. sol. (a) 205, No. 4 (2008) 683

relation in the conduction and valence band (see Fig. 4(a)) is deposited over a larger portion of the nanotube, the
is used with effective masses being m*con and m*val , respec- metal-nanotube contact is a side-contact as already men-
tively. In order to describe the complex band structure in tioned above. In order to explain a number of experimental
the band gap we make use of Flietner’s dispersion relation observations, in particular the trend of the rather large de-
[21]; for more details see Ref. [22]. pendence of the inverse subthreshold slope S and the on-
Scattering in the nanotube channel is accounted for by current on dox in devices with the same metal as electrode
attaching Büttiker probes via appropriate self-energy func- material, it is sufficient to describe the side-contact as a
tions to each site of the finite difference grid [23] which is simple metal semiconductor contact with a certain Schot-
also shown in Fig. 4(a). The Büttiker probes are attached tky-barrier (SB) height given by the work-function differ-
with a certain coupling strength γ = 0 . . .1 which is related ence between metal and tube. However, as will become
to the mean free path for scattering lscat via γ = 2a/lscat [23]. clear below, the strong dependence of the on-current on the
Furthermore, each probe has its own Fermi level Efj such specific contact metal and the rather asymmetric ambipolar
that the dotted line in Fig. 4(a) represents the position de- behavior cannot be explained with such a simple contact
pendent quasi-Fermi level in the channel. Since each Efj model. In this case, a side-contact geometry has to be taken
individually floats to a value such that the total current into account.
flowing into and out of a Büttiker probe sums up to zero
the probes describe inelastic scattering within the channel.
3.1 Carrier injection – impact of the device ge-
Figure 4(b) shows a gray-scale plot of the local density of
ometry Figure 5(a) and (b) show representative transfer
states in a conventional p–i–p transistor. Dark areas refer
characteristics for various drain–source voltages of a
to a low and bright areas to a large DOS. In the contacts
Schottky-barrier-CNFET (SB-CNFETs). The device exhib-
the DOS is low within the band gap whereas in the channel
its ambipolar behavior, typical of SB-FET devices. Ex-
a finite DOS is observed due to a penetration of the elec-
tracting the inverse subthreshold slope S one observes a
tronic wave-function into the gap. After self-consistency is
significant decrease of S with decreasing dox as is shown
achieved, the current flowing from source to drain is com-
in Fig. 5(c). This peculiar behavior – not expected in con-
puted using [23]
ventional-type FETs as long as electrostatic integrity is
4e preserved – is a consequence of the dependence of the car-
Ú dE Â T
d, j
Id = ( E ) [ f ( E - Efd ) - f ( E - Efj )] , (4) rier injection through the Schottky barrier on the screening
h j
length [5, 24], i.e. its dependence on d nt and dox . In order
d, j
where T ( E ) is the transmission probability between the to quantify the impact of the device geometry on the injec-
drain contact and a Büttiker probe at site j. Equation (4) is tion of carriers we use an analytical model that is based on
the Landauer result where 4e/h is the conductance of a sin- a simple metal-semiconductor contact geometry. The
gle mode (including a factor of 2 for the two conduction straight line in Fig. 5(c) is a result of this model showing
channels) and the integral gives the number of modes that excellent agreement with the experimental data in the de-
contribute to the current in the relevant energy interval. vice’s off-state.
The carrier injection, i.e. the tunneling through the
3 CNFETs as ultrathin-body Schottky-barrier Schottky barriers at the contact-channel interfaces, will in-
MOSFETs The easiest way of fabricating a CNFET is to fluence both, the off- as well as the on-state of the CNFET
disperse nanotubes on an oxidized piece of silicon and con- (see for instance [24]). However, in order to study the im-
tact them with metal electrodes (see Fig. 1(a)). The silicon pact of the device geometry, in particular the influence of
wafer then serves as a large area back-gate and the oxide the gate oxide thickness on the carrier injection, the on-
on top plays the role of the gate dielectric. Since the metal state does not provide a reliable measure since it sensi-

-5 -5
10 10
-6
Vds =-0.2V ..-1.0V -6 Vds =-0.2V ..-1.0V 3000
10 10
dox =10nm dox =10nm
-7 -7 2500
10 10
S (mV /dec)

-8 -8
10 10 2000
subthreshold
Id (A)

Id (A)

-9 -9
10 slope 10
1500
-10 -10
10 10
1000
-11 -11
10 10
-12 -12 500
10 10
(a) (b) (c)
-13 -13
10 10 0
-2.0 -1.0 0.0 1.0 2.0 -2.0 -1.0 0.0 1.0 2.0 0 100 200 300 400
Vgs(V) Vgs(V) d ox(nm)

Figure 5 (a) and (b) show typical transfer characteristics of back-gated SB-CNFETs [26]. (c) Extracted inverse subthreshold versus d ox .

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684 J. Knoch and J. Appenzeller: Tunneling phenomena in CNFETs

300 Vds =0.3V 300

FSB
(meV)

150 150

E (meV)
F SB

0 0
eff

slope=1
-150 -150

(a) (b) Ff0

-300 -300
-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0 d tunnel L
Vgs (V) x (a.u.)

300
(c) 400 (d)
Figure 6 (a) Effective SB height as a
F SB (meV)

FSB (meV)

200 300
function of Vgs . (b) shows conduction
FSB band profiles for various gate voltages.
iv) 200 eff
100 Lower part: ΦSB versus Vgs extracted
eff

eff

iii) ii)
100
from simulations (c) and experimental
slope = 1
0 dox = 5nm data (d) [25]. In addition, (c) shows re-
i) slope = 1 0 sults (dashed lines) for four different
-100 SB-CNFETs based upon Eq. (5).
-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 -0.6 -0.4 -0.2 0.0 0.2
Vgs (V) Vgs (V)

tively depends on the exact Schottky barrier height which ing that S = ln ((10) (∂I d /∂ΦSB
eff
) (∂ΦSB
eff
/∂Vgs ) ((1/I d )) -1 and
itself depends on the electrode material and the nanotube I d µ exp ( -ΦSB /kBT ) :
eff

diameter as will be discussed in detail below. Therefore,

the inverse subthreshold slope is taken in the following as kBT 1
S= ln (10)
the relevant figure of merit. The actual potential profile of q 1 - exp ( - d tunnel /λ )
the source SB can be replaced with an effective Schottky d tunnel < λ
kBT Ê1 λ ˆ
eff
barrier ΦSB ª ln (10) Á + . (6)
Ë 2 d tunnel ˜¯
for thermal emission alone. To this end a tun-
neling distance d tunnel is defined (see Fig. 6(b)) and the tun- q
neling probability through the SB is set to unity if the bar-
Equation (6) was used to calculate the straight line in
rier at some energy is thinner than d tunnel and zero otherwise.
Fig. 5(c) showing excellent agreement between the ex-
The exact value of d tunnel does not matter for the time being
perimental data and the model. To further validate the sim-
However, an estimate can be obtained using the WKB ap-
ple model for carrier injection we have simulated tempera-
proximation showing that d tunnel mainly depends on mate-
ture dependent transfer characteristics of four different SB-
rial specific parameters such as m* but only weakly de-
CNFETs with the following parameters: (i) m* = 0.1m0 ,
pends on Vgs . Since in the off-state the density of mobile
d ox = 2 nm, d nt = 1.4 nm; (ii) m* = 1.0m0 , d ox = 2 nm,
carriers is small, i.e. ρ ª 0 , Eq. (1) can be solved analyti-
d nt = 1.4 nm (iii) m* = 1.0m0 , d ox = 10 nm, d nt = 1.4 nm and
cally leading to
(iv) m* = 1.0m0 , d ox = 10 nm, d nt = 5 nm. Typical Arrhenius
eff
eff
ΦSB = Φ f (d ) = (ΦSB - Φ f0 ) exp ( - d tunnel /λ ) + Φf0 , (5) plots were employed to extract ΦSB in our analysis [25].
eff
Figure 6(c) shows the resulting ΦSB for the four different
where Φ f0 = Φ g + Φ bi is the surface potential in the channel cases. The one-to-one dependence of the extracted ΦSB eff
on
(in the case L
λ ) several λ away from the contact inter- Vgs is indeed observed in a small gate voltage range since a
face (see Fig. 6(b)). Note, that Eq. (5) has the same form as rather small SB of ΦSB = 150 meV was assumed in the
given above (see Section 2.1) in the case of a conventional simulations. For large negative Vgs a less effective modifi-
eff
device suffering from short channel effects where ΦSB cation of ΦSB eff
is observed consistent with the discussion
represents the potential barrier that determines the carrier above. The smaller d nt , dox and m* the closer is the slope of
eff
injection. Since ∂ΦSB /∂Φg < 1, SB devices appear to suffer the ΦSB eff
- Vgs curve to unity. This is due to a decreasing
from SCEs and S > 60 mV/dec can be expected although screening length λ as well as because of an increasing tun-
the device is electrostatically well-behaved. Figure 6(a) neling distance d tunnel from case (iv) to (i). Taking into ac-
eff
shows ΦSB as a function of gate voltage and (b) the cor-
responding conduction band profiles for various Vgs . count that d tunnel scales as 1/ m* [22], the dashed lines in
When Φ f0 ≥ ΦSB then ΦSB eff
= Φ f0 and consequently Fig. 6(c) are calculated using Eq. (5) which show an excel-
eff
eff
∂ΦSB /∂Φ g = 1 (gray line in Fig. 6(a)). However, as soon lent agreement with the values for ΦSB extracted from the
eff
as Φ f0 < ΦSB the curve in Fig. 6(a) deviates from the one-to- simulations. In the case (i) even negative ΦSB can be
one dependence (black line) with the slope given by achieved meaning that an excellent injection of carriers from
Eq. (5). A closed expression for S can be obtained by not- the source Schottky contact into the channel can be expected.

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phys. stat. sol. (a) 205, No. 4 (2008) 685

A CNFET with such a “thin” Schottky-barrier should ac- The considerations so far are valid only, if scattering
cordingly exhibit an excellent off- as well as on-state. can be neglected. However, scattering in the channel opens
The ability to significantly lower the effective Schott- a way to make multimode transport observable. If we de-
ky-barrier height with increasing Vgs in SB-CNFETs has note the transmission function through the SB with TSB and
also been observed experimentally. Figure 6(d) shows ΦSB eff write the transmission through the channel in the presence
as a function of gate voltage. The experimental curve of scattering as Tch = lscat /( L + lscat ) where L is the channel
shows qualitatively the same dependence as the simulated length and lscat the scattering mean free path [20] then the
data (for more details see Ref. [25]). overall transmission is

3.2 Carrier injection – observability of multi- TSBTch 1

Ttot = = . (7)
mode transport In carbon nanotubes, particularly in TSB + Tch - TSBTch L/lscat + 1/TSB
tubes with smaller diameter, the subband separation is usu-
ally much larger than kBT . Consequently, one might expect As a result, if the ratio L/lscat
1/TSB then Ttot ª lscat /L as
to observe multi-mode transport in CNFETs even at room in a conventional FET. Consequently, it is expected that
temperature. Multi-mode transport will appear as a step- multimode transport will be observable in this case.
like increase of I d when increasing Vgs where each current From Eq. (7) it is apparent that this can be achieved by
plateau corresponds to the maximum current a single mode making L very large, lscat small and/or increasing the
can carry. In experiments, however, signatures of multi- transmission TSB for a given ratio L/lscat (i.e. decreasing d nt
mode transport are usually not observed and consequently and dox ).
the transport in SB-CNFETs has been interpreted as due to An elegant way of increasing the ratio L/lscat was re-
a single mode only. However, we will argue in the follow- cently shown experimentally and relies on the introduction
ing that multi-mode transport occurs but the presence of of scattering within the channel of an SB-CNFET using
the SB prevents its observability. potassium doping [6]. Above a certain amount of doping
To be able to observe multi-mode transport it is neces- the transfer characteristics of an SB-CNFET that does not
sary that the current in one mode saturates with increasing show multimode transport without doping exhibit a step-
gate voltage before a subsequent mode significantly con- like current increase. This is shown in Fig. 7(a) where
tributes to the current. In other words, due to the thermal three modes can be identified to contribute to the current;
broadening of the current rise of each mode the subband the inset shows the same device on a larger Vgs -range. In
separation has to be significantly larger than kBT . However, order to support the experimental observations we have
the injection of carriers into a certain mode through a also performed simulations, accounting for scattering with
Schottky barrier leads to a broadening significantly larger the Büttiker probe approach outlined above. A device with
than kBT . The reason for this is that the tunneling through d nt = 1.4 nm, d ox = 2 nm in a wrap gate architecture and
the barrier itself does depend on the gate voltage which leads L/lscat = 30 was considered in order to guarantee a large TSB
to an additional broadening. As a first order approximation as well as L/lscat -ratio. The main panel of Fig. 7(b) shows
the range of broadening corresponds to the interval of Vgs the result where we also assumed a subband spacing of
eff
needed to change the effective SB height from ΦSB = ΦSB to 0.25 eV and ΦSB = 0.35 eV. One clearly observes a step-
eff
ΦSB ª 0 since then the current through a mode saturates. like increase of current and three different subbands can be
Given the fact that the subband spacing in nanotubes is on identified. However, in the case of ballistic transport
the order of 300 meV or lower for tubes with larger diameter (shown in the inset of Fig. 7(b)) the resolution of different
and looking at Fig. 6(c) it becomes apparent that only in the modes vanishes although multimode occurs in this case,
case (i) one could expect to observe multimode transport. In too, with the first three modes contributing significantly to
all other cases the broadening due to the SB is so large that the current. This inability of observing multimode trans-
current contributions of different subbands overlap and ren- port has to be taken into account when interpreting carbon
der multimode transport unobservable [22]. nanotube data.

0.35
2.5
Vds =0.1V
0.4
(a) (b) Vds =0.2V
0.30
Id (mA)

0.25
2.0 dnt =1.4nm Figure 7 (a) Experimental I d - Vgs
0.2 dox=2nm curves of an SB-CNFET exhibiting
Id (mA)

Vgs (V)
Id (mA)

0.20 1.5
0.4 0.8 1.2 1.6 multimode transport. The inset shows a
larger Vgs -range [6]. (b) shows simu-
8.0
0.15 0
-1.5 -0.5 0.5 1.0 6.0
Vgs (V) 1st mode lated transfer characteristics with
Id (mA)

0.10 4.0
0.5 strong scattering included. The inset
Vds =0.1V
0.05 2.0
shows the results of the same device in
Vds =0.2V
0.00 0.0 0.0 case of ballistic transport.
-1.6 -1.4 -1.2 -1.0 -0.8 -0.6 0.0 0.5 1.0 1.5 2.0 2.5
Vgs (V) Vgs (V)

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3.3 Carrier injection – role of contacts The simple
model of a metal in contact with the nanotube was able to
capture some aspects related to the scaling of the gate ox-
ide thickness and the tube diameter. However, a closer
look at CNFET data also reveals a number of discrepancies
between predictions of the simple SB-model and measured
CNFET characteristics. A particularly obvious aspect is the
often encountered asymmetric appearance of ambipolar
I d - Vgs curves for thin gate oxides as shown in Fig. 5(a)
and (b) which cannot be explained by the model presented
above. Furthermore, the dependence of the on-current on
the contact metal is substantially larger than predicted by
the metal-semiconductor model.
The reason for the discrepancy between experiment
and simulation is the contact geometry considered in
the SB-model compared to the actual experimental situa-
tion. Instead of a metal in direct contact with the nanotube,
today’s CNFETs usually exhibit side-contacts as was al-
ready mentioned above and depicted in Fig. 2(b). Recently,
we have introduced an extended SB-model that takes
the side-contact geometry into consideration [26]. Using
this model we were able to reproduce the I d - Vgs - charac-
teristics over a large gate voltage range as well as to extract
the Schottky barrier heights for devices with a large variety
of different nanotube diameters and different contact met-
als [8].
The side-contacts are accounted for in the calculations
as shown schematically in Fig. 8(a): The metal contact
is attached to a section of the nanotube of length lcomp
via Büttiker contacts. In the present case all Büttiker
probes are short-circuited, i.e. they share the same
Fermi energy which is set by the terminal voltage. Two pa-
rameters determine the properties of the side contacts:
the position of the Fermi energy which is given by the
work function difference and the coupling between
side-contact and nanotube. The coupling between metal
and nanotube modifies the density of states inside
the nanotube resulting in a “metal-poisoned” nanotube
segment from which carriers are injected into the channel.
It has been noted by Tersoff [27] that a substantial
potential barrier V0 > 10 eV exists at the nanotube-metal
interface in a side-contact geometry which results from
the rather large Fermi energy in the nanotube leading to a
rapid decay of the nanotube wave function perpendicular
to the tube axis. Since the metal is a van der Waals dis-
(a) (b)
l comp
r
metal
c γ .S met
r Figure 8 (a) Model of the side-contact
a γ .S 1r
nanotube r tube is described by the coupling γ. (b)
nt
effective channel
contact
© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
J. Knoch and J. Appenzeller: Tunneling phenomena in CNFETs
tance (lvdW > 3 Å) away from the nanotube the cou-
pling between both is generally weak. The parameter γ
which varies between 0 and 1 describes the coupling of the
side contact to the nanotube. γ ª 0 yields only a slight
modification of the energy gap with a small but finite den-
sity of states within the energy gap. In this case, a carrier
injection similar to a doped source–drain contact is ob-
tained (illustrated in Fig. 8(a)) and as a result, one branch
of the ambipolar characteristics of a SB-CNFETs gets sig-
nificantly suppressed, depending on where the Fermi
energy lies with respect to the conduction/valence band.
On the contrary, if γ approaches unity the energy gap
vanishes completely and the density of states of the nano-
tube resembles a metallic one. In this case, a Schottky
contact results [26]. Figure 9 shows gray-scale plots of the
local DOS for weak and strong coupling. The effect of the
coupling on the DOS can clearly be seen in the contact
areas within the band gap.
The coupling constant γ can be related to the potential
barrier present at the nano-tube metal interface by analyti-
cally calculating the transmission function T(E) through a
potential barrier of height V0 and width lvdW using elemen-
tary quantum mechanics and comparing this with the
transmission function T(E) through a single site that is
connected to the right to a semi-infinite contact and to the
left to a semi-infinite contact whose coupling is mediated
by the parameter γ. This is illustrated in Fig. 8(b) and (c)
and results in (see appendix)
V0 Ê 2m*V0 ˆ
2+ sinh 2 Á lvdW ˜
t Ë
2
¯
γ =
2
Ê
2
V0 2Ê 2m*V0 ˆˆ
ÁË 2 + t sinh ÁË
2
lvdW ˜ ˜
¯¯
- -1 . (8)
4
Note that γ explicitly depends on m* and a through the
hopping parameter t =
2 /2m*a 2 . For typical values of m*
and V0 in nanotubes, γ turns out to be less than 10–2.
The side-contact model was used to extract the actual
ΦSB of three different metals – palladium, titanium and
aluminum – and to study the impact of the nanotube di-
ameter on the resulting SB height. To do so, the on-current
(c)
l vdW with underlying finite difference grid.
V0 The coupling between metal and nano-
r
2 and (c) show the relation between γ
and a potential barrier present at the
metal – nanotube interface.
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phys. stat. sol. (a) 205, No. 4 (2008) 687

(a) "semiconductor-like" (b) "metal-like"

injection injection

Figure 9 Local DOS in a CNFET for weak cou-

1 0 1 0 pling (a), leading to a semiconductor-like carrier in-
f(E) f(E) jection and strong coupling (b) which results in a
source channel drain source channel drain Schottky contact.

for a large number of nanotube devices was measured for
each contact metal. The statistical appearance of each
measured on-current value was then correlated with a TEM
measurement of the nanotube diameters. As a result, the
on-currents for the different metallic contacts could be as-
sociated with a certain nanotube diameter as shown in
Fig. 10(b). Next, we fitted simulated transfer characteris-
tics to experimental curves. Three representative character-
istics selected from three metal samples are shown in
Fig. 10(a) along with the simulation results. A coupling
constant of γ = 0.007 gives good agreement between simu-
lation and experiment, in both the off- and the on-state.
The only adjustable parameter used for the three devices is
the SB height ΦSB . Note that the relative shift of Vth seen in
the simulations is a consequence of a varying ΦSB and this
shift matches the experimental data very well. Using this
approach, we have simulated electrical characteristics over
a wide range of ΦSB which allows associating a certain on-
current with a specific SB height. As a result, the compari-
son between experiment and simulation yields ΦSB as a
function of nanotube diameter for all three contact metals
as shown in Fig. 10(b); note, that ΦSB = 0 eV refers to a
lineup of the Fermi level with the valence band of the
nanotube. Figure 10(b) shows that the large variation of
on-current observed in CNFETs stems from a combination
of specific contact metal and tube diameter. Furthermore,
using palladium and tube diameters d nt ≥ 1.4 nm optimum
contacts can be realized yielding the highest on-currents
and showing the least variation at the same time.
-6
10
Pd contacts
-7
Ti contacts
10
Al contacts
-8
10
To conclude this section we want to address an impor-
tant implication of the side-contact model: A small cou-
pling leads to an almost intact semiconductor band gap in
the nanotube (see Fig. 9(a)) and hence one obtains a
“doped” contact from which carriers are injected into the
channel. In turn, this leads to an efficient suppression of
the undesired ambipolar characteristics as was mentioned
above. As a result, inserting an insulator between nanotube
and contact deliberately seems a viable approach to avoid
the large off-state leakage currents due to the ambipolar
operation that deteriorates particularly ultimately scaled
devices (due to the thin gate dielectric). However, so far
we assumed a semi-infinite contact. If the contact length is
finite, the coupling strength determines a minimum contact
or transfer length lcmin needed in order to get a low contact
resistance giving rise to a trade-off between small coupling,
i.e. efficient suppression of the ambipolar operation on the
one hand and small contact lengths on the other hand. Since
the coupling between metal electrode and nanotube is de-
scribed as a series of Büttiker probes all having the same
Fermi level an estimation of the minimum contact length
can be given by expressing the coupling parameter as a
mean free path for scattering. This mean free path repre-
sents the length scale over which a scattering event occurs,
i.e. it represents the length needed for a carrier to be fully
transferred from the metal to the nanotube and vice versa.
Following Venugopal and coworkers [23] we get for the
mean free path lmfp = a/γ ª lcmin where a is the lattice spac-
ing of the finite difference grid. For a coupling strength of
-5
10
-0.1
-6 Vdd = -0.5V
10
0.1
-7
10
F SB (eV)

-8
I d (A)

-9
I d (A)

10 10 0.3

-10 -9
10 10 0.5
-11 -10
10 10 Pd contacts 0.7
-12
Ti contacts
-11
10 10 Al contacts
0.9
-13
(a) -12
(b)
10 10
-2.0 -1.5 -1.0 -0.5 0.0 0.5 0.6 0.8 1.0 1.2 1.4 1.6
Vgs (V) diameter (nm)

Figure 10 (a) Comparison of simulated (straight line) and experimental SB-CNFET characteristics using the side-contact model.
(b) On-current and ΦSB as a function of tube diameter for three different contact metals [8].

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688 J. Knoch and J. Appenzeller: Tunneling phenomena in CNFETs

(a) (b)
L bg L ch L bg
0.9 source channel drain
"doped" channel "doped"
source drain 0.6
NT
source drain

E (eV)
d
0.3 Ef
Figure 11 (a) Schematics of a C-
gate CNFET. (b) shows band profiles with
insulator 0.0
s (gray dotted line) and without (black
Si back-gate Ef
-0.3 line) taking the pileup charge into ac-
count.
0 L/2 L

γ = 0.007 as was used in the analysis above a minimum
contact length of ≈70 nm is required.
4 Band-to-band tunneling in conventional
CNFETs In a conventional-type FET the source and drain
electrodes consist of doped semiconductor portions. Since
within the band gap of a semiconductor there are no states
that can be occupied, doped semiconducting electrodes
lead to unipolar characteristics and much smaller off-state
leakage currents can be expected if compared to e.g. SB-
FET devices as discussed above. Doping nanotubes on the
other hand is not as simple as in silicon based devices.
However, using a dual-gate architecture as illustrated in
Fig. 11(a), doping can be realized electrostatically hence
facilitating the investigation of transport in conventional-
type CNFETs (C-CNFETs). Such a dual-gate device has
recently been demonstrated by Lin and coworkers which
allowed a controlled transition from ambipolar to unipolar
device behavior [28]. Figure 11 shows a schematics of
such a dual-gate transistor. A highly doped silicon sub-
strate serves as a large area back-gate separated from the
nanotube by a thermally grown SiO2 (10 nm in thickness in
the actual experiment of Ref. [28]). This back-gate is used
to electrostatically “dope” the source–drain extensions. In
order to exclude any influence of the back-gate on the
channel the actual gate is deposited on top of the SiO2, ef-
fectively screening the electrical field of the back-gate. Af-
terwards, a thin oxide is grown on top of the actual gate
(approximately 4 nm thick Al2O3 is formed in the present
case; for more details see Ref. [28]). Finally, the nanotube
is dispersed on top of this dual-gate structure and contacted
with titanium electrodes.
For negative back-gate voltages, the device basically
represents a conventional p–i–p FET structure. In opera-
tion, the back-gate is kept at a constant, negative gate volt-
age while the actual gate is swept from negative to positive
voltages. For negative Vgs and Vds the device operates as
conventional p-type FET with a unipolar behavior. Fig-
ure 12(a) shows transfer characteristics of a dual-gate C-
CNFET with a channel length of 200 nm (gray curves).
The device shows regular FET transfer characteristics with
an almost ideal inverse subthreshold slope of 65 mV/dec
reinforcing that the device acts as a conventional-type tran-
sistor [28]. However, scaling down the channel length of
such a transistor leads to an unexpected behavior in the de-
vice’s off-state: If the electrostatic integrity is preserved
during scaling, the off-state should exhibit the same almost
ideal inverse subthreshold slope in the long channel as well
as in the short channel case. However, experimentally – al-
though it is ensured that the device is electrostatically well-
behaved – the scaled device with a channel length of
40 nm shows an increasing leakage current with increasing
bias as well as a substantially larger inverse subthreshold
slope [3] (black curves in Fig. 12). In order to investigate
and explain this unusual behavior we performed simula-
tions of C-CNFETs, discussed in the next section.
4.1 Charge pile-up in conventional CNFETs In
the simulations we assumed a high doping level in the
source–drain contacts that gives rise to a certain Fermi en-
ergy below the valence band edge. C-CNFETs are simu-
lated with a channel length of 10 nm and gate oxide thick-
ness of 3 nm for Vds = 0.3 and 0.5 V; the Fermi energy in
the source–drain contacts of the C-CNFET is set to 0.1 eV
and the band gap of the nanotube under consideration was
0.6 eV (see [29] for more details). Looking at the transfer
characteristics of the simulated device, as displayed in
Fig. 12(b), it is apparent that they show the same, unusual

10-5
10-7 Vds =-0.5V
Lg = 40nm
Vds =-0.3V
10-7
10-9
|Id (A)|

Figure 12 (a) Experimental transfer

Id (A)

Vds = -0.7V
Vds = -0.1V characteristics for a C-CNFET with
10-9 L = 200 nm (gray curves) and L =
10-11
L=10nm 40 nm (black curves) [32]. (b) Simu-
Lg = 200nm dox =3nm lated transfer characteristics of a scaled
(a) (b)
10-13 10-11 C-CNFET with L = 10 nm (from [29]).
-1 0 1 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
Vgs (V) Vgs (V)

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phys. stat. sol. (a) 205, No. 4 (2008)
behavior in the off-state as the experimental devices: be-
low a certain gate voltage the current levels off at an in-
verse subthreshold slope far in excess of 60 mV/dec. The
reason for this can be inferred from a closer look at
Fig. 11(b) which shows the conduction and valence bands
in a p–i–p device. For large enough bias, electrons are
likely to be injected into the conduction band within the
channel via band-to-band tunneling (BTBT) due to the low
effective mass of 0.1m0 and the steep n–p junction at the
drain side of the device. This steep n–p junction is in turn
a result of the small screening length λ , i.e. stems from the
smallness of the nanotube diameter and the thin gate oxide.
Electrons are injected into the channel and get trapped
since their flow is blocked by the energy gap of the source
contact. Consequently, this leads to a charge pileup pre-
venting the gate from effectively moving the bands to turn
the device off. Figure 11(b) shows two band profiles where
the black lines refer to the potential profile expected with-
out charge pileup and the gray dotted lines belong to the
case where the pileup, illustrated by the hatched area, is
taken into account. As a result of the pileup, the potential
barrier for holes is reduced and this leads to a large hole
leakage current in the off-state. However, as can be seen
from the transfer characteristics in Fig. 12(b), the charge
pileup significantly deteriorates device performance only if
Vds ≥ Eg /2. For smaller bias the charge pileup is much less
pronounced and allows for a proper off-state performance
of the device. In this case, the C-CNFET provides higher
on-state currents and steeper inverse subthreshold slopes
compared to SB-CNFETs due to the absence of a potential
barrier that limits the injection of carriers into the channel.
Nevertheless, particularly for small band gap nanotubes the
charge pileup can be detrimental to the device performance
of scaled C-CNFETs.
It is interesting to note that the increasing leakage cur-
rent in the device’s off-state is not due to usual SCEs since
electrostatic integrity is preserved in the device. However,
short channel effects appear if the charge in the channel
changes significantly with Vds . More precisely, SCEs ap-
pear if Cox and Cd are of the same order (see Section 2.1).
Due to the pileup of electrons, there is a significant amount
of charge in the channel even in the device’s off-state. If
(a) (b)
source
doped channel doped
source drain
gate
Ef
gate
insulator NT
Si
Figure 13 (a) Device layout of the tunneling CNFET with a wrap-gate and doped source – drain contacts. The entire device is embed-
ded into SiO2 and sits on a grounded Si wafer. (b) shows the conduction and valence bands in the device’s on-state. Carriers can only
contribute to Id within the energetic window DΦ .
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we neglect any recombination processes, the pileup charge
is determined by the drain Fermi energy, since the pileup
charge does not constitute a current flow. Consequently,
this gives rise to a quantum capacitance of the form
Cq ª 2/h ¥ 8m*/(Φ f0 - ( Efd )) with Efd = Efs - qVds . Since
the pileup charge depends equally on Φd and Φf0 (apart
from a different sign) one obtains
Cox Cd + Cq
δΦ f0 = δΦ g + δΦ d , (9)
Cox + Cd + Cq Cox + Cd + Cq
which, compared to Eq. (2), exhibits a second term de-
pending on Φd . For proper off-state performance it is re-
quired that ∂Φf0 /∂Φg = 1 and ∂Φ f0 /∂Φ d Æ 0 . The first re-
quirement leads to an ideal inverse subthreshold slope
whereas the second results in a suppression of DIBL. Usu-
ally, Cox
Cd and Cox
Cq in an electrostatically well-
behaved device in the off-state. However, due to BTBT
Cq > Cox in the present case, which leads to the appearance
of SCEs. Again, the reason for this peculiar situation is the
large band-to-band tunneling probability which in turn is a
result of the small d nt and dox . To avoid the appearance of
SCEs related to the charge pileup it is therefore counter-
intuitive to scale down the gate oxide thickness. However,
in order to suppress SCEs it is necessary that Cox
Cq
meaning that the device has to be scaled towards the so-
called quantum capacitance limit (QCL). In this limit, the
surface potential is determined only by the gate potential
and not the charge in the channel anymore as has been dis-
cussed above. As a result, scaling down d ox will lead to an
even more significant charge pileup which, however, has
no impact on the surface potential. Simulations (not shown
here) have shown that this indeed leads to a suppression of
SCEs and ideal conventional transistor characteristics with
S = 60 mV/dec are recovered.
5 Electronic transport in tunneling CNFETs We
have seen above that tunneling phenomena play an impor-
tant role in CNFETs and determine the electrical behavior
of such devices. Due to the small diameter of nanotubes
and in particular in a wrap-gate architecture tunneling in
channel drain
~l
Ff0
DF
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CNFETs is strongly promoted. From an application point
of view, this can be beneficial, e.g. in SB-CNFETs but also
detrimental as in the case of C-CNFETs. However, even if
an ideal C-CNFET could be manufactured, this device ar-
chitecture in general suffers from a fundamental limitation:
any conventional-type FET is limited to a minimum in-
verse subthreshold slope of 60 mV/dec at room tempera-
ture. This is a major obstacle to further reduce the supply
voltage Vdd and hence the power consumption of integrated
circuits: Provided a certain on/off-current ratio of ap-
proximately 3 orders of magnitude is required and if we
assume that two thirds of Vdd is needed to obtain a high on-
state current, one needs at least a gate voltage range of
3 ¥ (3 ◊ 60) mV = 0.54 V to properly operate the device.
The reason for the 60 mV/dec limit is the fact that the
switching mechanism of conventional-type devices relies
on the modulation of the injection of carriers from a ther-
mally broadened Fermi function. Hence, in order to
achieve S < 60 mV/dec, the current injection from the
source contact has to be modified in a way that it becomes
independent of a thermally broadened Fermi distribution
function. Recently, band-to-band tunneling has been pro-
posed as an effective means to accomplish this [9, 10, 30–
32]. A device consisting of a p-doped source (drain), an in-
trinsic channel and an n-doped drain (source) (p–i–n) is
ideally suited for this purpose. Consider a device structure
as depicted in Fig. 13(a). In order to obtain an optimal gate
control over the bands in the channel the transistor exhibits
a wrap-gate and a thin dox . The entire device is embedded
into SiO 2 and sits on a grounded silicon wafer. In the fol-
lowing we will investigate the electronic transport in such
a p–i–n- or tunneling CNFETs (T-CNFET) employing
analytical considerations as well as simulations.
5.1 Analytical considerations of tunneling FETs
Figure 13(b) shows the conduction and valence band in the
on-state of a T-CNFET. Only electrons within the ener-
getic window DΦ contribute significantly to I d . An ana-
lytic expression for I d can be obtained using the WKB ap-
proximation for the BTB tunneling probability [33]
DΦ
4e
Id =
h Ú dE T
0
WKB (1 - f ( E - Efs )) ª
s s
Ê Ê DΦ - Ef ˆ Ê - Ef ˆˆ
¥ Á ln Á e kBT + 1˜ - ln Á e kBT + 1˜ ˜ ,
Ë Ë ¯ Ë ¯¯
where we assumed a Vds large enough to ensure that
f ( Efd ) ª 1 within DΦ . The tunneling probability TWKB be-
comes energy-independent if one approximates the source-
channel n–p junction with a triangular potential barrier as
illustrated with the dashed area in Fig. 13(b) [31]. Since
the n–p junction has a spatial extent on the order of λ one
obtains
Ê 4λ 2m*Eg3/ 2 ˆ
TWKB ª exp Á - ˜,
Ë 3q
( Eg + DΦ ) ¯
© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
J. Knoch and J. Appenzeller: Tunneling phenomena in CNFTs
where Eg is the band gap of the nanotube. A number of in-
sights can be obtained from this simple expression together
with Eq. (10). First, the inverse subthreshold slope
S = ln (10) ((∂I d /∂Vgs ) (1/I d )) -1 can be calculated making
use of
∂I d ∂I 2e 2 Ê ∂TWKB ∂F (Φ f0 ) ˆ
= e d0 = Á F (Φ f0 ) + TWKB , (12)
∂Vgs ∂Φ f h Ë ∂Φ f 0
∂Φ f0 ˜¯
where F (Φf0 ) is the integral of f s ( E ) over the energy inte-
gral DΦ . In Eq. (12) two contributions to the change of I d
with gate voltage can be seen. These two contributions al-
low for two different mechanisms for realizing an S
smaller 60 mV/dec. Suppose the second term in Eq. (12)
becomes dominant which is the case if TWKB is large and
thus changes only slightly with gate voltage (for more de-
tails see [34]). In this case, the subthreshold swing is de-
termined by the change of the function F ( Evch ) . As a result,
the particular band situation leads to a band-pass filter ef-
fectively cutting off the high and low energy tails of the
source Fermi function. It is this “effective cooling” of
f ( Efs ) that facilitates steep inverse subthreshold slopes.
Then using again the WKB approximation, TWKB cancels
out in the expression for S and thus the subthreshold swing
becomes independent of TWKB . Expanding the integral func-
tion F ( Evch ) for small DΦ to first order yields
S ª (ln (10)/|e|) DΦ allowing for very steep subthreshold
swings if DΦ Æ 0 .
It is often argued that the insensitivity of I d to changes
in the channel length is a major advantage of a tunneling
FET. However, BTBT is usually the main scattering event
and consequently scattering within the channel can be ne-
glected unless the channel is made sufficiently long. The
smaller the BTBT probability the longer the channel has to
be in order for the scattering to dominate. As a result, the
penalty for the insensitivity of the tunneling FET to chan-
nel length variations is a low BTBT probability and hence
a low on-state current. In turn, if the BTBT probability is
made large (i.e. λ is made small) much smaller channel
lengths are sufficient to obtain scattering dominated transport
through the device. Equation (11) allows obtaining an esti-
4e
h
TWKB kBT mate of the channel length required for the scattering trans-
port in the channel to become dominant. The transmission
function due to scattering for carriers flowing through the
(10) channel can be estimated to be Tscat ª lscat /( L + lscat ). Then the
overall transmission function is [20]
TWKBTscat
Ttot =
TWKB + Tscat - TWKBTscat
1
= , (13)
Ê 4λ 2m*Eg3/ 2 ˆ L
exp Á ˜+
Ë 3q
( Eg + DΦ ) ¯ lscat
This means, scattering in the channel becomes
significant only for channel lengths Lmin ≥ lscat
(11)
¥ exp ((4λ 2m*Eg3/ 2 )/(3q
( Eg + DΦ ))). The exponential
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phys. stat. sol. (a) 205, No. 4 (2008) 691

dependence of Lmin on λ on the other hand shows that for a be reached where Cox
Cq due to the decreasing density
realistic device geometry the minimum channel length can of states. In a T-CNFET Cq will be even smaller than in a
be rather long. Therefore, scattering in tunneling FETs C-CNFET due to the proportionality of Cq to TWKB . Note
usually can be neglected. However, one has to keep in that this is only true, as long as Efd is larger than the va-
mind that this implies a deteriorated on-state current due to lence band in the channel; this important fact will be dis-
a small BTBT probability. cussed in more detail below. As as result, in a wrap-gate
T-CNFET with thin gate dielectric it is very likely that the
5.2 Advantages of one-dimensional transport QCL is reached and thus Cg ª Cq (for a detailed study on
for T-CNFETs The one-dimensionality of the T-CNFET the scaling of 1D FETs towards the QCL see Ref. [35]). At
has an interesting consequence which makes a 1D system the same time, I d µ TWKB (cf. Eq. (10)) and therefore, the
very attractive for the realization of tunneling devices. For gate delay τ becomes independent of TWKB . This means that
realistic systems the BTBT probability will always be to first order the presence of the BTBT barrier does not de-
smaller than unity and hence the on-current of a tunneling teriorate the on-state of 1D tunneling FETs as measured by
FET is deteriorated compared to a conventional-type tran- the gate delay. Consequently, 1D systems such as carbon
sistor. However, the gate delay τ = CgVdd /I d is a much more nanotubes are ideally suited for the realization of tunneling
appropriate measure to quantify intrinsic device perform- FETs since they allow combining a high on-state perform-
ance. Assuming the long-channel case (i.e. λ
L ) the gate ance with steep subthreshold swings.
capacitance is given by Cg = Cox Cq / (Cox + Cq ). For large In the derivation above we assumed a drain source bias
enough Vds (see above), Cq can be calculated using Eq. (11). large enough so that the injection of holes into the channel
Since TWKB is an exponential, after differentiation it turns from the drain contact can be neglected. However, if we
out that Cq µ TWKB: consider a device not in the QCL then for small bias the in-
jection of holes from the drain contact can result in a sig-
4λ 2m*Eg3/ 2 nificant charge density in the channel, similar to the charge
Cq ª TWKB Ú dE D( E ) (1 - f ( E - Efs )) pileup in C-CNFETs. Consequently the same reasoning as
3
( Eg + DΦ ) 2
used in Section 4.1 applies here, too. For small bias the in-
∂
(14) jection from drain leads to Cq > Cox and as a result the
∂Φ f0 Ú
s
+ qTWKB dE D( E ) (1 - f ( E - Ef )) ,
movement of the conduction/valence bands in the channel
with changing Vgs slows down. If on the other hand Vds is
where now D( E ) is the one-dimensional density of states. decreased, Cq drops since the source for injecting holes
We have discussed above that in 1D systems the QCL can is moved to higher energies. In turn the bands will

-7
6.0 10
Vgs = -0.7..-0.9V (a) (b) 1.6
(c)
-9
10
-11 1.2
10
4.0
|Id (A)|
|Id (nA)|

-13
Vth - shift 0.8
10
E (eV)

L=50nm DFd
dnt =1nm -15 0.4
10 E fs DFf0
d =10nm
2.0 ox E fd
-17 0.0
10
Vds = -0.8V h-injection
10
-19 -0.4
Vds = -0.1V
10
-21 -0.8
0.0
-0.8 -0.4 0.0 -0.9 -0.7 -0.5 -0.3 source channel drain
Vds (V) -5
Vgs (V)
8.0 10
(d) (e) 1.6 (f) L=20nm
-6
10 dnt =1nm
6.0 -7 1.2 dox =1nm
10
|Id (mA)|

0.8
|Id (A)|

E (eV)

10
-8 S=
Vgs =-0.4V 10mV/dec DFd
4.0 0.4
..-0.8V -9 E fs
10
-10
0.0 DFf0 0 E fd
2.0 10 Vds =-0.6V -0.4
-11
10
Vds =-0.4V -0.8
0.0
-0.4 -0.2 0.0 -0.6 -0.3 0.0 source channel drain
Vds (V) Vgs (V)

Figure 14 Output (a) and transfer (b) characteristics of a T-CNFET with rather large d ox . (c) shows the conduction and valence bands
for constant Vgs and two different Vds . (d) – (f) show the respective characteristics and band profiles for a device in the quantum capaci-
tance limit.

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 pss a

solidi
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status
692 J. Knoch and J. Appenzeller: Tunneling phenomena in CNFETs

L (nm) L (nm)
0 20 50 70 0 20 50 70
1.0 i) -7 iii) Vgs-Al = 1.0
10

potential (eV)
potential (eV)

i) measurement +0.05V
0.5 Vgs-Al = at T=300K 0.5
-1.1V
0.0 simulation with 0.0
10 -9 d ox-Al = 4nm

source
source

-0.5 -0.5

drain
drain

Vgs-Si ~ Vgs-Si ~

Id (A)
-1.0 -2.5V -2.5V -1.0
1.0 ii) Vgs-Al = 10 -11 mV iv) Vgs-Al = 1.0
potential (eV)

potential (eV)
-0.5V S ~ 40 dec iv) +0.2V
0.5 0.5
-13 mV
0.0 10 S ~ 65 dec 0.0
source

source
-0.5 -0.5
drain

drain
iii) Vgs-Si ~ Vgs-Si ~
ii)
-1.0 -2.5V -2.5V -1.0
10 -15
L bg L ch
-1.5 -1.0 -0.5 0.0 0.5 L bg L ch
Vgs-Al (V)
Figure 15 Transfer characteristic of a dual-gate CNFET. For negative gate voltages the device acts as a C-CNFET, for positive gate
voltages as a T-CNFET with an S = 40 mV/dec; to the left and right band profiles for the respective operation modes are shown [9].

follow the gate potential until again a new equilibrium gate voltages the device acts as a C-CNFET as has been
situation reached. This means that the position of the sur- discussed above: Negative gate voltages pull up the con-
face potential Φf0 strongly depends on the drain potential duction and valence bands in the channel such that the
Φd or in other words ∂Φ f0 /∂Φ d > 0 and SCEs can be ex- thermal emission of holes increases. This operation mode
pected to appear. In this case, drain-induced-barrier- and the respective band diagrams are schematically shown
thinning (DIBT) of the BTBT barrier occurs which results on the left of the main panel of Fig. 15. (Here, the gray
in a non-linear increase of I d for small Vds and a shift of the shaded area in the band diagrams is the actual channel of
threshold voltage with increasing bias. Figure 14 shows length Lch and Lbg is the length of the back-gated source–
simulated output (a) and transfer (b) characteristics of a drain extensions.) However, if large positive gate voltages
device not scaled towards the quantum capacitance limit. are applied, the bands are moved down far enough to open
An exponential increase of I d for small bias and a shift of up a channel for BTBT between the valence band in source
Vth can indeed be observed as predicted. The reason for this and the conduction band in the channel as indicated by the
is DIBT which is illustrated in Fig. 14(c): here, conduction arrows in the band diagrams shown in Fig. 15 (to the right
and valence bands are shown for constant Vgs and two dif- of the main panel). For increasing Vgs the barrier becomes
ferent Vds . A clear difference in surface potential can be ob- thinner and consequently the current increases. In the pre-
served which is due to the Vds -dependent injection of sent case, we observe an inverse subthreshold slope in the
charges from the drain contact into the channel. In contrast, BTBT regime of S = 40 mV/dec which is to the best of our
if the device is scaled towards the QCL, where always knowledge the first experimental demonstration of transis-
Cox
Cq one expects that DIBT is suppressed. Figure 14 tor operation with an S < 60 mV/dec due to controlled
shows simulated output (d) and transfer characteristics (e) BTB tunneling [9]. In Fig. 15 we also plot the result of a
together with the conduction/valence band for two differ- simulation using the model presented above (black line).
ent Vds (f) in case of a device in the QCL. As expected the The measured and simulated transfer curves are in excel-
non-linearity in the output characteristics as well as the Vth - lent agreement showing that the model captures well the
shift vanish. The reason can be inferred from Fig. 14(f), essential transport mechanism in our dual-gate CNFETs
namely the suppression of DIBT since ∂Φf0 /∂Φd ap- and more importantly it shows that the interpretation of the
proaches zero. Furthermore, due to the thin d ox the device experimental data in terms of BTB tunneling is appropriate.
exhibits an S ≈ 10 mV/dec and an I d ∼ 5 µA. Consequently, Note that the rather low on-current in the BTBT branch of
scaling a T-CNFET towards the QCL provides regular the characteristics shown in Fig. 15 is due to the fact that
FET characteristics as well as a high on-state performance the dual-gate structure is not ideal for a tunneling FET
and steep inverse subthreshold slopes. since the QCL is since the carriers have to tunnel through two potential bar-
much more likely to be attained in 1D systems, tunneling riers. Decreasing d ox and in particular realizing a p–i–n
FETs greatly benefit from employing 1D structures as ac- structure will greatly increase the current level in the de-
tive channel material. vice’s on-state (see for instance [10, 30, 32]).

5.3 Experimental results As a first attempt to real- 6 Conclusion The electronic transport in carbon
ize a T-CNFET experimentally the dual-gate nanotube nanotube FETs and in particular tunneling phenomena and
FET introduced in Section 4 was employed. The device es- their impact on the electrical behavior of three different
sentially is a p–i–p structure where the p-doped segments CNFET architectures have been investigated. As it turned
are realized with electrostatic “doping” [28]. For negative out, the inherently small diameter of carbon nanotubes and

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phys. stat. sol. (a) 205, No. 4 (2008)
their cylindrical shape make them ideal objects for ulti-
mately scaled devices. In addition, the one-dimensionality
of the electronic transport in carbon nanotubes leads to dis-
tinctly different behavior if compared to bulk-like MOS-
FET devices. For instance, a charge pileup in the off-state
of conventional-type CNFETs leads to short channel ef-
fects although the device is electrostatically well behaved.
Furthermore, due to the one-dimensional transport, device
operation in the quantum capacitance limit becomes attain-
able which is beneficial for the transistor performance of
e.g. tunneling CNFETs.
From an application point of view, the SB-CNFET is
the easiest structure to fabricate but exhibits some draw-
backs: the presence of the Schottky barrier yields either in-
verse subthreshold slopes significantly larger than
60 mV/dec if nanotubes with larger diameter are employed.
Or improving the injection of carriers by using small di-
ameter tubes and thin gate oxides leads to a rather large
off-state leakage current. The C-CNFET shows character-
istics superior to the SB-CNFETs. However, due to the
charge pileup in these structures, the drain source-voltage
should not exceed half of the band gap since otherwise
short channel effect appear leading to large off-state leak-
age currents. The third transistor structure, the T-CNFET,
shows very promising characteristics since this device ar-
chitecture allows combining a superior off-state with in-
verse subthreshold slopes significantly smaller than
60 mV/dec together with a high on-state performance.
Appendix The retarded Green’s function G r of the
one-site problem is
G r = [ E - 2t + t eika + γ t eika ]-1 = [γ t eika - t e - ika ]-1 .
With Γ l = 2γ t sin (ka) and Γ r = 2t sin (ka) the transmis-
sion function T ( E ) follows to be
4γ sin 2 (ka )
T (E) =
1 + γ - 2γ (cos 2 (ka ) - sin 2 (ka ))
1
ª , (15)
t (1 - γ ) 2
1+
4γ E
since ka
1. This result has to be compared with the T ( E )
given by
1
T (E) = , (16)
V02
sinh ( KlvdW )
2
V -E
1+ 0
4E
where K = 2m(V0 - E )/
2 . It was mentioned above that
V0 > 10 eV and therefore V0 - E ª V0 . As a result, T ( E ) and
T ( E ) are of the same form and a quadratic equation for γ
can be identified. Since γ has to be between 0 and 1 a
unique solution can be found yielding the value for γ given
above (Eq. (8)).
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