2010, 12th International Conference on Optimization of Electrical and Electronic Equipment, OPTIM 2010
Three-level ASNPC Converter Implemented
With an Analogue Command
L. Parvulescu, D. Floricau, M. Covrig
Politehnica University of Bucharest
Faculty of Electrical Engineering
313 Splaiul Independentei
060042 Bucharest, Romania
parvulesculuci@yahoo.com
Abstract-The three-level Active Stacked Neutral Point
Clamped converter is presented. The main advantage of
this structure is the half reduction of the average
switching frequency of all devices. This paper is focused
on the analogue command of the 3L-ASNPC structure.
The advantages of this modulation method are its
simplicity and reduce cost. Experimental results are
shown to validate the efficiency of this command method.
1. INTRODUCTION
To obtain high power converters it was necessary to
increase the voltage and current capability of the
semiconductor devices. With the increase of voltage, device
performances drop and the price goes up.
Multilevel structures were created as an alternative solution
to classical two level structures in order to reduce the voltage
stress for the power devices. Another advantage of these
structures is the increase of switching frequency. The increase
in the number of devices can be justified by the increase of
performances and the reduction and size of the filter elements.
Because of this reasons, the classical two level structures with
a reduced number of devices can no longer be considered as
ideal. These observations lead to the development of several
multilevel topologies over the last years [1].
The development of these structures began with the
solution created by Bhagwat in 1980. The structure was called
3L-SC (Stack Cells Converter) because it is made out of two
elementary cells, the result being a three level output voltage
[2]. The load current is limited by the power losses in the
middle arm. The main disadvantage of this structure is that
the power losses in the middle arm increase with the decrease
of the modulation index. Following this concept, a new
structure called 3L-NPC (Neutral Point Clamped Converter)
was created [3], [4]. This structure offered a simple solution
to increase the inverters voltage and output power
comparative to the two level solutions. Shortly after it was
created, this solution started to be used in medium voltage
applications in the voltage range 2.3 kV – 7.2 kV. Now it is
used in industrial, mining, marine and traction applications.
The better output voltage quality compared to the two level
structures is the main advantage of the 3L-NPC converter. An
important disadvantage is the unequal loss distribution among
the power devices leading to different junction temperatures.
978-1-4244-7020-4/10/$26.00 '2010 IEEE 646
I. Parvulescu
S.C. Electrotehnica Electrical Equipments S.A
B-dul Timisoara 104A, Sector 6
061334 Bucharest, Romania
ronibos@yahoo.com
Some devices become hot, while others have a low
temperature. The power losses in the most stressed switch
limits the switching frequency and the output power. The
existences of a single zero state for the 3L-NPC single-leg
converter represents a drawback.
Later a new concept was implemented on a new structure
called 3L-FC (Flying Capacitor Converter) [5]-[6]. This
structure has the advantage of doubling the apparent
switching frequency. At high switching frequency, the middle
capacitor has a small size and the overall performances are
better, compared to the previous structures. The additional
expense of flying capacitors, particularly at low and moderate
switching frequencies (200Hz–1kHz), is the main
disadvantage of 3L-FC topology.
In 2001 a new structure was introduced. It was called 3L-
ANPC (Active Neutral Point Clamped Converter) and
represents an improvement of the 3L-NPC by the increase in
the output power and performances when the output voltage
is zero [7]-[11]. An improvement of this structure is
represented by the 3L-SNPC (Stacked Neutral Point Clamped
Converter). This topology combines the concepts of 3L-SC
and 3L-NPC structures. It has the advantage of a better power
loss distribution among the semiconductor devices [12].
At the 3L-ANPC and 3L-SNPC converters, two switches
work at the fsw frequency over the entire reference period.
This is a disadvantage of these structures.
In [13] a new conversion topology was presented. The
structure was called 3L-ASNPC (Active Stacked NPC) and
had a digital PWM control. Its objective was to improve the
disadvantages of the previous structures by half reducing the
switching frequency for all the power devices.
In this paper is presented the 3L-ASNPC made with an
analogue PWM command. This PWM method is simple and
easy to implement on a structure and has a low price.
2. PROGRESS OF MULTILEVEL STRUCTURES
Among the high power converters, the 3L-NPC converter
(Fig. 1), introduced 25 years ago, is the most widely used in
all types of industrial applications. This structure is made out
of 4 switches that make two commutational cells: S1-S3C, S2-
S4C and two clamping diodes. By using a sinusoidal control
method it is observed that this structure has only three
commutation states: P, O and N (Table I). The drawbacks of
this topology are the existence of only a zero state sequence In this paper, the PWM strategy that doubles the apparent
for the single-leg converter and the unequal loss distribution switching frequency is presented.
among the power devices.
Inh
UC1 S1
~ Inh Inh
S1 Sr S1C
VDC m
2 InhN UC2
S2 InhN

O Du A Iload
UC2 S2
S3C Sr
Dd R UC1 Inh
/\/\ S2C
VDC L
S4C UC1
2 n Ud1
InhN
VDC
UC2
Fig. 1. Three-level NPC Converter. Sr
UC2 InhN
\/\/ S3
The main advantage of this structure is the reduce price due
Ud2 UC1
to the presence of only four switches and 2 clamping diodes S3C
Inh InhN
compared to the following multilevel topologies.
The average switching frequency (fav) is equal to half of the Fig. 3. Used PWM strategy for
switching frequency (fsw), while the apparent switching 3L-ANPC and 3L-SNPC converters.
frequency (fap) is equal to fsw.
In Fig. 3 is presented an analogical representation of the
TABLE I PWM strategy for the 3L-ANPC and 3L-SNPC converters.
SWITCHING SEQUENCE OF 3L-NPC CONVERTER
Switching Sequence Middle arm switches
Output Voltage (VAO) Switching States
S1 S1C S2 S2C
O A
Vdc/2 P 1 0 1 0 3L-NPC 3L-SNPC
0 O 0 1 1 0 S2C S3
-Vdc/2 N 0 1 0 1 Fig. 4. Three-level SNPC Converter.

The 3L-ANPC converter is derived from the 3L-NPC
converter having two more active transistors in parallel with
clamping diodes.
Active Switch
m The structure is made from 3 cells and two clamping
S1C
3L-NPC O 3L-ANPC
S4
n voltage state is obtained depending on the PWM strategy
Fig. 2. Three-level ANPC Converter.
This topology can be controlled using different PWM
strategies [10]. To obtain the P state, the switches S1 and S2
must be on, while for the N state S2C and S3C must be on. The
O state is obtained depending on the PWM strategy used.
This is one of the advantages of this structure.
From the PWM strategy, it results six switching states: P,
O1+, O2+, N, O1- and O2-. This PWM strategy has the
advantage of balancing the power losses inside the switches
because the O state is made from the conduction of one
transistor and one diode. This is the first structure, without
flying capacitors, that allows the doubling of the apparent
switching frequency (fap=2fsw).
The 3L-SNPC converter (Fig. 4) results from the
combination of the 3L-NPC converter and two switches on
the middle arm. This structure can also be commanded to
double the apparent frequency. The PWM strategy used is the
same as for the 3L-ANPC structure (Fig. 3).
diodes. The middle arm is made from two reversed parallel
switches to allow a bidirectional current flow. To obtain
positive output voltage, S1 and S2 must be on, while for
negative output voltage S2C and S3C must be on. The zero
used.
The advantages of this structure are a better loss
distribution and different inductive current path depending on
the PWM strategy used. The S2 and S2C devices switch on the
entire period (Tsw) with the switching frequency, while the
others only on half a period, so fav=fsw/2.
3. ASNPC CONVERTER
The 3L-ASNPC converter (Fig. 5) is derived from the 3L-
SNPC converter having two more active transistors in parallel
with clamping diodes. All devices are sized to support a
voltage equal to VDC/2. This structure has more degrees of
freedom compared to 3L-ANPC and 3L-SNPC converters.

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 A sinusoidal reference wave (Ur) compared with two
carrier waves (Sd1 and Sd2) phase-shifted with half a period
are used to implement the PWM strategy.
Active Switch
m Similar S3C and S4C have the following command:
3L-SNPC
O
3L-ASNPC
n S2C switch
Fig. 5. Three-level ASNPC Converter.
TABLE II
SWITCHING SEQUENCE OF 3L-ASNPC CONVERTER
Output Switch Sequence
Switching
Voltage
State S1 S1C S2 S2C S3 S3C S4 S4C
(VAO)
VDC/2 P 1 0 1 0 1 0 0 0 S3 switch
O1+ 0 1 1 0 0 0 0 0 When the reference is negative and S3C is turned off, S3 is
O2+ 1 0 0 1 1 0 0 0
0
O1- 0 0 0 0 0 1 1 0
O2- 0 0 0 1 1 0 0 1 for the reactive load current. In the same time when the
-VDC/2 N 0 0 0 1 0 1 0 1 reference is negative and S4C is turned off, the reverse diode
From the PWM strategy results six switching states: P, O1+,
O2+, N, O1- and O2- (Table II). The P state is obtained when S1
and S2 are turned on. Similarly for the N state, S3C and S4C
must be turned on. S3 is also turned on for the P state and S2C
for the N state but have no effect on the current path
The power loss distribution for these states can not be
influenced. For the zero voltage level, four different control
sequences are used. The distribution of the conduction losses
during the zero states can be controlled by selecting the upper
(S1C-S2), lower (S4-S3C) or middle (S2C-S3) current paths.
During the zero states, one active switch and one diode are in
conduction. Even if more than two devices turn on, only one
active switch and one diode will be in conduction, depending
on the load current direction.
The zero states O1+ and O2+ are obtained when the
reference voltage is positive, while the states O1- and O2- are
obtained when the reference voltage is negative. The zero
state O1+ is obtained when the switches S1C and S2 are turned
on, while the others are turned off. The state O2+ is obtained
when S2C and S3 are turned on. S1 is also turned on but it does
not influence the paths of the load current. The other switches
(S1C, S2, S3C, S4 and S4C) are turned off. The state O1- is
obtained when the switches S3C and S4 are turned on, while
the other ones are turned off. The zero switching state O2- is
obtained when S2C and S3 are turned on. S4C is also turned on
but it does not influence the paths of the load current. The
other switches (S1, S1C, S2, S3C and S4) are turned off and the
paths of the load current are similar to the state O2+.
In this paper a new implementation for the PWM control
strategy from [13] is presented. An experimental model was
created having an analogical type PWM command that will
be presented in the following paragraphs.
The PWM reference is a sinusoidal signal with 10V
amplitude and a frequency of 0.5-50 Hz.
Two logical signals were introduced: SENSP = 1 when
Sr>0 and SENSN = 1 otherwise.
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The PWM strategy for the S1 and S2 switches is the following:
1) When Sr>0, SENSP = 1, duty cycle (Δ) for S1 and S2
rises from 50% to 95%.
2) Otherwise SENSP = 0, S1 = 0, S2 = 0.
3) When Sr<0, SENSN = 1, Δ for S3C and S4C rises
from 50% to 95%.
4) Otherwise SENSN = 0, S4C = 0, S3C = 0.
The middle arm switches, S2C and S3, operate as follows:
When the reference is positive and S2 is turned off, S2C is in
conduction with the reversed diode of S3 creating the path for
the reactive load current. In the same time when the reference
is positive and S1 is turned off, the reverse diode of S1C and
the S2 transistor gives the path for the reactive load current.
When the reference is negative, the S2C transistor is off.
in conduction with the reversed diode of S2C creating the path
of S4 and the S3C transistor gives the path for the reactive load
current. When the reference is positive, the S3 transistor is off.
Creating the carrier wave
C1
R2
P15
P15
R1
R2
Ud1
D D
M D Dz D
N15 M
M N15
P1
Fig. 6. Analogue implementation of the carrier wave.
The base oscillator gives two carrier waves (Ud1 and Ud2)
symmetrical to zero (Fig. 6). The oscillator is made is made
from an integrator and a trigger Schmidt circuit.
The C1 capacitor is loaded with the current:
Ic = U/R2 (1)
U = Uz+2*Ud (2)
The maximum voltage is chosen UAO=10V. The capacitor
is loaded between –UAO and +UAO on half a cycle (Tsw/2).
Q = Ic*(T/2) = C1*(2*U0) (3)
T = 2*[C1*(2*UAO)] / (U/R2) (4)
For the experimental model it was chosen the PWM
frequency: fsw= 3.5 kHz.
From (3) and (4), for C1 = 10nF results R2=4.5KΩ.
The amplitude for the oscillator is obtained from the
comparison between the output voltage VAO and U= Uz+2Ud.
The comparison is current dependent. From the P1
potentiometer the amplitude is set to Vmax = 10V.
To obtain the switches control strategy it is used the
oscillator direct and reversed output which is compared with
the sinusoidal reference voltage Ur. If the reference is S4C have Δ between 50% and 95%. Otherwise they are
negative the pulses for S1 are suppressed by SENSP = 0. suppressed by SENSN=0. For S2, the comparison is made
When the reference is positive the pulses for the S1 switch between Ud2 and Ur without the interference of SENSP.
have Δ between 50% and 95%. If the reference is positive the output pulses for S2 have Δ
Ud1 from 50% to 95%. Otherwise the output pulses for S2 are
+Vmax suppressed. The output voltage VAO for positive reference
Tsw 2Tsw t(s) values is a result of the superposition of S1 and S2 switches
-Vmax (Fig. 9). When Sr is zero, S1 and S2 have Δ = 50% and are
reversed phase shifted. The output voltage in this case is zero.
Ud2
For a maximum reference value, S1 and S2 have Δ = 95% and
+Vmax
Tsw 2Tsw VAO reach its maximum value. If the reference is negative, S1
t(s)
and S2 are turned off and the output voltage results from the
-Vmax
PWM strategy of S4C and S3C.
Fig. 7. Carrier waves. From Fig. 10 it can be seen that the frequency of VAO is the
double of fsw.
The Ud2 signal used when the reference is negative is the The switches from the middle arm (S2C and S3) have the
reverse of signal Ud1 (Fig.7). role of creating a path for reactive current flow. For positive
load current, the active current component is obtained with S1
1
S1 4073 SENSP and S2 on, while the reactive component is obtained with S1
2 off. For negative load current, the active current component is
3
S1C 4073 obtained with S3C and S4C on, while the reactive component is
obtained with S4C off.
CON
ERR START
4093

Ur
Ud1 4093

Fig. 8. Analogical command for S1 and S1C switches.

Ud1 is compared with the reference value to obtain the

command for the S1 switch (Fig. 8).
The logic gates 4093 are used as NAND gates. The 4073
gates are used as OR gates that give at their output the PWM
control for the S1 and S1C switches. The block CON gives the Fig. 10. Experimental command device.
connection of this circuit with the rest of the experimental
model. For the START/STOP command or when an error In Fig. 10 it is presented the board from the experimental
(ERR) occur it is necessary to close both exits at the same model that gives the analogical command for the ASNPC
time. For this reason, the START command was used on both converter.
exists. For the circuit to be active only when the reference is Because the command and control circuits are made only
positive, the command SENSP was used. with logical gates and comparison blocks, the price for the
product made with this type of PWM control is small.
S1 In the following chapter several tests made on the
1 experimental model will be shown in order to validate the
0
efficiency of this PWM method.
Tsw 2Tsw t(s)
S2 4. EXPERIMENTAL TESTS
1
0 The 3L-ASNPC single-phase inverter was designed to
Tsw 2Tsw
VA0(V) t(s) have several function modes:
VDC/2 1) Step-down circuit with positive or negative output
0
Tsw 2Tsw voltage
t(s) 2) Inverter with adjustable frequency
Fig. 9. Output voltage—VAO and S1, S2 pwm 3) Current regulator
strategy for Sr>0. All this configurations were made with a simple analogical
To obtain the command for S4C is made a comparison PWM command. For the measurements it was used an
between Ud2 and Ur. If the reference is negative the pulses for adjustable load of 0…50Ω with an interior inductance of

649
1mH. The mains supply voltage used was 3x400V ± 10%,
50Hz while the maximum output voltage was set to 100V ca.
Test 1
The system was set to create a sinusoidal adjustable voltage
synchronous with the ac. line. The measurements were made
at an output voltage of 60V on a 10Ω load.
Fig. 11. Output current--I_load and middle arm current ---
I_S2C (10A/div and 5ms/div).
Fig. 12. PWM control of S1 and S4C devices
(10V/div and 2ms/div).
In Fig. 11 it can be seen the sinusoidal output current with
a maximum distortion factor of 11%. The current through the
middle arm is PWM modulated with a frequency of 7 kHz.
The carrier frequency was set to 3.5 kHz, resulting in the
doubling of the apparent frequency with this control method.
The middle arm current represents the reactive component of
the load current.
Test 2
The system was set to generate an adjustable output current
with a frequency of 50Hz. The measurements were made at a
650
load current of 6A ca. on a 10Ω load. In Fig. 12 the command
for S1 and S4C is shown. The passing between positive and
negative values can be seen.
Test 3
The system was set to generate an adjustable output voltage
with an adjustable frequency of 4…50Hz. The measurements
were made at a load current of 60V ca. on a 10Ω load.
Fig. 13. Current reference—I_r and
output current—I_load (10A/div and 5ms/div).
Fig. 14. Output current--I_load and middle arm current ---
I_S2C (2A/div and 0.1ms/div).
The measurements from Fig. 13 were made at a frequency
of 29Hz. When the frequency is modified, the amplitude for
the output current remains the same.
Test 4
The system was set to generate a dc positive and adjustable
voltage. The measurements were made at an output voltage of
60V on a 10Ω load.
Fig. 14 presents the output and the middle arm current. The
PWM period is 280μs, while the current impulse period is
140μs. From this it can be seen once more the doubling of the
apparent switching frequency.
From the measurements presented as a result of the
experimental model, it could be seen the great variety of
configurations that could be made with this command
method. At the same time it was shown the efficiency of this
method.
5. CONCLUSIONS
[11] T. Bruckner, S. Bernet, P.K. Steimer, “Feedforward Loss Control of
Three-Level Active NPC Converters” IEEE Trans. on Ind.
Applications, Vol 43, Issue 6, Nov.-dec. 2007 pp 1588-1596
[12] D. Floricau, G. Gateau, M. Dumitrescu, and R. Teodorescu, “A new
stacked NPC converter: 3L-topology and control”, 12th European
Conference on Power Electronics and Applications – EPE’07, Aalborg,
Denmark, pp.1-10, Sept. 2007.
[13] D. Floricau, G. Gateau, E. Floricau, A. Leredde, “Reducing of the
Average Switching Frequency using Three-level Active-SNPC
Converter”, 13th European Conference on Power Electronics and
Applications – EPE’09, Barcelona, Spain, pp.1-7, Sept. 2009.

This paper has shown the 3L-ASNPC converter made with

analogue circuits and a PWM strategy that allows the
doubling of the apparent switching frequency.
The advantages of this command method are its simplicity,
the low price of its components and the increased efficiency.
The main disadvantage is the difficulty in changing the PWM
control strategy. Methods of compensating this problem will
be presented in future studies.
Experimental results were shown in order to validate the
efficiency of this new command method.

ACKNOWLEDGMENT
The authors would like to thank the National University
Research Council (CNCSIS) and the National Centre for
Programme Management (CNMP) from Romania for
supporting this work under projects ID_1037/2007 and
Mecener_21017/2007.

REFERENCES
[1] J. Rodriquez, S. Bernet, B. Wu, J.O. Pontt, and S. Kouro, “Multilevel
voltage-source-converter topologies for industrial medium-voltage
drives”, IEEE Trans. on Ind. Electronics, Vol.54, pp. 2930-2945, Dec.
2007
[2] P. Bhagwat, V.R. Stefanovic, Generalized structure of a multilevel PWM
inverter, IEEE Industry Applications Society Annual Meeting, 1980,
pp.761-76.
[3] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped
PWM inverter”, IEEE Trans. on Industry Applications, Vol.IA-17, pp.
518-523, 1981.
[4] L. Demas., T.A. Meynard., H. Foch. , G. Gateau, ”Comparative study of
multilevel topologies: NPC, multicell inverter and SMC with IGBT”,
IECON 2002 28th Annual Conference of the Industrial Electronics
Society.
[5] T.A. Meynard and H. Foch, “Multi-level conversion: high voltage
choppers and voltage-source-inverters”, IEEE on Power Electron
Specialist Conference, pp. 397-403, July 1992.
[6] T.A. Meynard, M. Fadel, and N. Aouda, “Modelling of multilevel
converters”, IEEE Trans. on Ind. Electronics, Vol.44, no. 3, pp. 356-
364, Jun. 1997.
[7] T. Bruckner, S. Bemet, “Loss balancing in three-level voltage source
inverters applying active NPC switches”
IEEE 32nd Annual Power Electronics Specialists Conference, PESC.
2001.
[8] Li Jun, A.Q. Huang, S. Bhattacharya, Tan Guojun “Three-Level Active
Neutral-Point-Clamped (ANPC) Converter with Fault Tolerant
Ability”, Twenty-Fourth Annual IEEE Applied Power Electronics
Conference and Exposition, APEC 2009.
[9] P. Barbosa, P. Steimer, J. Steinke, M. Winkelnkemper, N. Celanovic,
“Active-neutral-point-clamped (ANPC) multilevel converter
technology”, 2005 European Conference on Power Electronics and
Applications.
[10] D. Floricau, E. Floricau, M. Dumitrescu, “Natural Doubling of the
Apparent Switching Frequency using Three-Level ANPC Converter”,
International School on Nonsinusoidal Currents and Compensation –
ISNCC’08, Łagów, Poland, pp.1-6, 2008.

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