Beruflich Dokumente
Kultur Dokumente
90
APPLICATIONS 80
70
D Mini/Micro Audio System
60 6Ω
D DVD Receiver
50
D Home Theater
40
DESCRIPTION 30
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital and PowerPAD are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
! "#$ %!& % Copyright 2005, Texas Instruments Incorporated
"! "! '! ! !( ! %% )*&
% "!+ %! !!$* $%! !+ $$ "!!&
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SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
The TAS5152 is available in a 36-pin PSOP3 (DKD) MODE Selection Pins
thermally enhanced package. The package contains a MODE PINS PWM INPUT OUTPUT PROTECTION
heat slug that is located on the top side of the device for CONFIGU- SCHEME
convenient thermal coupling to the heatsink. M3 M2 M1 RATION
2N (1) AD/BD 2 channels
0 0 0 BTL mode (2)
modulation BTL output
DKD PACKAGE 0 0 1 Reserved
(TOP VIEW)
1N (1) AD 2 channels
0 1 0 BTL mode (2)
modulation BTL output
GVDD_B 1 36 GVDD_A PBTL mode.
OTW BST_A 1N (1) AD 1 channel
2 35 0 1 1 Only PWM_A
modulation PBTL output
SD 3 34 PVDD_A input is used.
PWM_A 4 33 OUT_A Protection works
RESET_AB 5 32 GND_A similarly to BTL
PWM_B 6 31 GND_B mode (2). Only
OC_ADJ 7 30 OUT_B difference in SE
GND 8 29 PVDD_B 1N (1) AD 4 channels mode is that
1 0 0
modulation SE output OUT_x is Hi-Z
AGND 9 28 BST_B
instead of a
VREG 10 27 BST_C pulldown through
M3 11 26 PVDD_C internal pulldown
M2 12 25 OUT_C resistor.
M1 13 24 GND_C 1 0 1
PWM_C 14 23 GND_D
1 1 0 Reserved
RESET_CD 15 22 OUT_D
1 1 1
PWM_D 16 21 PVDD_D
(1) The 1N and 2N naming convention is used to indicate the required
VDD 17 20 BST_D
number of PWM lines to the power stage per channel in a specific
GVDD_C 18 19 GVDD_D
mode.
(2) An overload protection (OLP) occurring on A or B causes both
channels to shut down. An OLP on C or D works similarly. Global
errors like overtemperature error (OTE), undervoltage protection
(UVP) and power-on reset (POR) affect all channels.
Package Heat Dissipation Ratings (1)
PARAMETER TAS5152DKD
RθJC (°C/W)—2 BTL or 4 SE 1.28
channels (8 transistors)
RθJC 〈°C/W)—1 BTL or 2 SE 2.56
channel(s) (4 transistors)
RθJC (°C/W)—(1 transistor) 8.6
Pad area (2) 80 mm2
(1) JC is junction-to-case, CH is case-to-heatsink.
(2) RθCH is an important consideration. Assume a 2-mil thickness of
typical thermal grease between the pad area and the heatsink. The
RθCH with this condition is 0.8°C/W for the DKD package and
1.8°C/W for the DDV package.
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Terminal Functions
TERMINAL
FUNCTION (1)
FUNCTION DESCRIPTION
NAME NO.
AGND 9 P Analog ground
BST_A 35 P HS bootstrap supply (BST), external capacitor to OUT_A required
BST_B 28 P HS bootstrap supply (BST), external capacitor to OUT_B required
BST_C 27 P HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D 20 P HS bootstrap supply (BST), external capacitor to OUT_D required
GND 8 P Ground
GND_A 32 P Power ground for half-bridge A
GND_B 31 P Power ground for half-bridge B
GND_C 24 P Power ground for half-bridge C
GND_D 23 P Power ground for half-bridge D
GVDD_A 36 P Gate-drive voltage supply requires 0.1-µF capacitor to AGND
GVDD_B 1 P Gate-drive voltage supply requires 0.1-µF capacitor to AGND
GVDD_C 18 P Gate-drive voltage supply requires 0.1-µF capacitor to AGND
GVDD_D 19 P Gate-drive voltage supply requires 0.1-µF capacitor to AGND
M1 13 I Mode selection pin
M2 12 I Mode selection pin
M3 11 I Mode selection pin
OC_ADJ 7 O Analog overcurrent programming pin requires resistor to ground
OTW 2 O Overtemperature warning signal, open drain, active-low
OUT_A 33 O Output, half-bridge A
OUT_B 30 O Output, half-bridge B
OUT_C 25 O Output, half-bridge C
OUT_D 22 O Output, half-bridge D
PVDD_A 34 P Power-supply input for half-bridge A requires close decoupling of 0.1-µF capacitor to
GND_A
PVDD_B 29 P Power-supply input for half-bridge B requires close decoupling of 0.1-µF capacitor to
GND_B
PVDD_C 26 P Power-supply input for half-bridge C requires close decoupling of 0.1-µF capacitor to
GND_C
PVDD_D 21 P Power-supply input for half-bridge D requires close decoupling of 0.1-µF capacitor to
GND_D
PWM_A 4 I Input signal for half-bridge A
PWM_B 6 I Input signal for half-bridge B
PWM_C 14 I Input signal for half-bridge C
PWM_D 16 I Input signal for half-bridge D
RESET_AB 5 I Reset signal for half-bridge A and half-bridge B, active-low
RESET_CD 15 I Reset signal for half-bridge C and half-bridge D, active-low
SD 3 O Shutdown signal, open drain, active-low
VDD 17 P Power supply for digital voltage regulator requires 0.1-µF capacitor to GND.
VREG 10 P Digital regulator supply filter pin requires 0.1-µF capacitor to AGND
(1) I = input, O = Output, P = Power
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SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
OTW
System
Microcontroller SD
TAS5508
OTW
SD
BST_A
Bootstrap
BST_B Capacitors
VALID RESET_AB
RESET_CD
PWM_A
OUT_A
2nd-Order L-C
Left- Output
Input Output Filter
Channel H-Bridge 1
H-Bridge 1 OUT_B for Each
Output PWM_B
Half-Bridge
2-Channel
H-Bridge
BTL Mode
OUT_C
PWM_C 2nd-Order L-C
Right- Output
Output Filter
Channel H-Bridge 2
Input OUT_D for Each
Output H-Bridge 2 Half-Bridge
PWM_D
GVDD_A, B, C, D
M1
PVDD_A, B, C, D
GND_A, B, C, D
BST_C
Hardwire
M2 Bootstrap
Mode
OC_ADJ
M3
4 4 4
PVDD GVDD
PVDD Power- VDD
35 V Supply Hardwire
VREG
System Decoupling OC Limit
Power-Supply
Power Decoupling
Supply
GND
GND
VAC
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SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
SD
Power
On
M1
Reset AGND
Protection
M2 and
I/O Logic
M3 Temp.
Sense GND
RESET_AB
Overload
RESET_CD Isense OC_ADJ
Protection
GVDD_D
BST_D
PVDD_D
PWM Gate
PWM_D Ctrl. Timing OUT_D
Rcv. Drive
BTL/PBTL−Configuration
Pulldown Resistor
GND_D
GVDD_C
BST_C
PVDD_C
PWM Gate
PWM_C Ctrl. Timing OUT_C
Rcv. Drive
BTL/PBTL−Configuration
Pulldown Resistor
GND_C
GVDD_B
BST_B
PVDD_B
PWM Gate
PWM_B Ctrl. Timing OUT_B
Rcv. Drive
BTL/PBTL−Configuration
Pulldown Resistor
GND_B
GVDD_A
BST_A
PVDD_A
PWM Gate
PWM_A Ctrl. Timing OUT_A
Rcv. Drive
BTL/PBTL−Configuration
Pulldown Resistor
GND_A
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ELECTRICAL CHARACTERISTICS
RL= 4 Ω. FPWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise
specified.
TAS5152
SYMBOL PARAMETER CONDITIONS
MIN TYP MAX UNITS
Internal Voltage Regulator and Current Consumption
VREG Voltage regulator, only used as a reference node VDD = 12 V 3 3.3 3.6 V
Operating, 50% duty cycle 7 17
IVDD VDD supply current mA
Idle, reset mode 6 11
50% duty cycle 5 16
IGVDD_x Gate supply current per half-bridge mA
Reset mode 0.3 1
50% duty cycle, without
15 25 mA
IPVDD_x Half-bridge idle current output filter or load
Reset mode, no switching 7 25 µA
Output Stage MOSFETs
TJ= 25°C, includes
RDSon,LS Drain-to-source resistance, LS metallization resistance, 140 155 mΩ
GVDD = 12 V
TJ= 25°C, includes
RDSon,HS Drain-to-source resistance, HS metallization resistance, 140 155 mΩ
GVDD = 12 V
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PO − Output Power − W
90
1
80
70
6Ω 60 6Ω
4Ω
50
0.1
40
30
20 8Ω
0.01 8Ω 10
0
1 10 100 0 5 10 15 20 25 30 35
PO − Output Power − W PVDD − Supply Voltage − V
Figure 1 Figure 2
90 70 4Ω
Efficiency − %
80 4Ω 60
70
50
60
50 40
6Ω
40 30
30
20
20
8Ω 10 TC = 25°C
10
Two Channels
0 0
0 5 10 15 20 25 30 35 0 25 50 75 100 125 150 175 200 225 250
PVDD − Supply Voltage − V PO − Output Power − W
Figure 3 Figure 4
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SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
PO − Output Power − W
35
100
Power Loss − W
30 90
6Ω 80
25
70
20 60
8Ω
50
15
40
10 30
20
5 8Ω
10 THD+N @10%
0 0
0 25 50 75 100 125 150 175 200 225 250 10 20 30 40 50 60 70 80 90 100 110 120
PO − Output Power − W TC − Case Temperature − °C
Figure 5 Figure 6
NOISE AMPLITUDE
vs
FREQUENCY
0
−10 TC = 75°C
−20 –60 dB
1 kHz
−30
−40
Noise Amplitude − dBr
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
0 2 4 6 8 10 12 14 16 18 20 22
f − Frequency − kHz
Figure 7
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SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
TC = 75°C TC = 75°C
10 45
PVDD = 35 V THD+N @ 10%
One Channel
40
PO − Output Power − W
35
1 30 3Ω
25
3Ω
20
0.1 15
10 4Ω
4Ω
5
0.01 0
1 10 50 0 5 10 15 20 25 30 35
PO − Output Power − W PVDD − Supply Voltage − V
Figure 8 Figure 9
OUTPUT POWER
vs
CASE TEMPERATURE
60
55 3Ω
50
45
PO − Output Power − W
40
35
30 4Ω
25
20
15
10
5 THD+N@ 10%
0
10 20 30 40 50 60 70 80 90 100 110 120
TC − Case Temperature − °C
Figure 10
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SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
PO − Output Power − W
180
1
160 2Ω
140
120
2Ω
100
0.1
80
60
3Ω
40
3Ω
0.01 20
0
1 10 100 0 5 10 15 20 25 30 35
PO − Output Power − W PVDD − Supply Voltage − V
Figure 11 Figure 12
240
220 3Ω
200
180
160
140
120
100
10 20 30 40 50 60 70 80 90 100 110 120
TC − Case Temperature − °C
Figure 13
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PVDD
10 Ω 3.3 Ω
100 nF
GVDD 10 nF 1000 µF
47 µF 50 V
10 µF 50 V
10 Ω 50 V
10 nF
TAS5152DKD
50 V
100 nF
1 36 100 nF
Microcontroller GVDD_B GVDD_A 50 V
33 nF 3.3 Ω
2 35
0Ω OTW BST_A
Optional 3 34 100 nF 10 µH @ 10 A
BKND_ERR SD PVDD_A 50 V
470 nF
4 33
PWM_P_1 PWM_A OUT_A 100 V
10 µH @ 10 A
5 32
VALID RESET_AB GND_A
6 31 100 nF
PWM_M_1 PWM_B GND_B 50 V 3.3 Ω
22 kΩ 30
7
PWM_P_2 OC_ADJ OUT_B
10 nF
8 29 50 V
GND PVDD_B
9 28 33 nF 100 nF 47 µF
PWM_M_2 AGND BST_B 50 V 50 V
10 nF
10 27
VREG BST_C 100 nF 47 µF 50 V
100 nF 11 33 nF 50 V 50 V 100 nF
26
TAS5508 M3 PVDD_C 50 V 3.3 Ω
12 25
M2 OUT_C
13 24 10 µH @ 10 A
M1 GND_C
470 nF
14 23 100 V
PWM_C GND_D
10 µH @ 10 A
15 22
RESET_CD OUT_D
16 21 100 nF
PWM_D PVDD_D 50 V 3.3 Ω
1Ω 17 20 100 nF 47 µF
GVDD VDD BST_D 50 V 50 V
10 nF
100 nF 18 19 33 nF
10 µF GVDD_C GVDD_D
50 V
PVDD
10 Ω 100 nF 100 nF
3.3 Ω
10 nF 1000 µF
10 Ω
50 V 50 V
Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters
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SLES127A − FEBRUARY 2005 − REVISED NOVEMBER 2005
PVDD
10 Ω 3.3 Ω
100 nF
GVDD 10 nF 1000 µF
47 µF 50 V
10 µF 50 V
10 Ω 50 V
10 nF
TAS5152DKD
50 V
100 nF
1 36 100 nF
Microcontroller GVDD_B GVDD_A 50 V
33 nF 3.3 Ω
2 35
0Ω OTW BST_A
Optional 3 34 100 nF 10 µH @ 10 A
BKND_ERR SD PVDD_A 50 V
470 nF
4 33
PWM_P_1 PWM_A OUT_A 100 V
10 µH @ 10 A
5 32
VALID RESET_AB GND_A
6 31 100 nF
No connect PWM_B GND_B 50 V 3.3 Ω
22 kΩ 30
7
OC_ADJ OUT_B
10 nF
8 29 50 V
GND PVDD_B
9 28 33 nF 100 nF 47 µF
PWM_P_2 AGND BST_B 50 V 50 V
10 nF
100 nF 10 27
VREG BST_C 100 nF 47 µF 50 V
33 nF 50 V 50 V 100 nF
11 26
M3 PVDD_C 50 V
TAS5508 3.3 Ω
12 25
M2 OUT_C
13 24 10 µH @ 10 A
M1 GND_C
470 nF
14 23 100 V
PWM_C GND_D
10 µH @ 10 A
15 22
RESET_CD OUT_D
16 21 50 nF
No connect PWM_D PVDD_D 100 V 3.3 Ω
1Ω 17 20 100 nF 47 µF
GVDD VDD BST_D 50 V 50 V
10 nF
100 nF 18 19 33 nF
10 µF GVDD_C GVDD_D
50 V
PVDD
10 Ω 100 nF 100 nF
3.3 Ω
10 nF 1000 µF
10 Ω
50 V 50 V
Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters
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10 Ω
100 nF PVDD
GVDD
47 µF
10 µF 3.3 Ω
10 Ω 50 V
TAS5152DKD
10 nF 1000 µF
100 nF 50 V 50 V
1 36
Microcontroller GVDD_B GVDD_A
33 nF
2 35
0Ω OTW BST_A A
Optional 3 34 100 nF 10 µH @ 10 A
BKND_ERR SD PVDD_A 50 V
4 33
PWM_P_1 PWM_A OUT_A
10 µH @ 10 A
5 32
VALID RESET_AB GND_A B
6 31
PWM_P_2 PWM_B GND_B
39 kΩ 30
7
PWM_P_3 OC_ADJ OUT_B
8 29
GND PVDD_B
9 28 33 nF 100 nF 47 µF
PWM_P_4 AGND BST_B 50 V 50 V
100 nF 10 27
VREG BST_C 100 nF 47 µF
33 nF 50 V 50 V
11 26
TAS5508 M3 PVDD_C
12 25
M2 OUT_C C
13 24 10 µH @ 10 A
M1 GND_C
14 23
PWM_C GND_D
10 µH @ 10 A
15 22
RESET_CD OUT_D D
16 21
PWM_D PVDD_D
1Ω 17 20 100 nF 47 µF
GVDD VDD BST_D 50 V 50 V
100 nF 18 19 33 nF
10 µF GVDD_C GVDD_D
PVDD
10 Ω 100 nF 100 nF
3.3 Ω
10 nF 1000 µF
10 Ω
50 V 50 V
10 nF 10 nF
50 V 50 V
100 nF 100 nF
100 V 100 V
3.3 Ω 3.3 Ω
A C
1 µF 10 nF @ 50 V 1 µF 10 nF @ 50 V
2.7 kΩ 50 V 2.7 kΩ 50 V
100 nF 100 nF
PVDD 100 V PVDD 100 V
220 µF 3.3 Ω 220 µF 3.3 Ω
50 V 50 V
PVDD/2 PVDD/2
220 µF 220 µF
50 V 50 V
10 nF 10 nF
50 V 50 V
100 nF 100 nF
100 V 100 V
3.3 Ω 3.3 Ω
B D
1 µF 10 nF @ 50 V 1 µF 10 nF @ 50 V
2.7 kΩ 50 V 2.7 kΩ 50 V
100 nF 100 nF
PVDD 100 V PVDD 100 V
220 µF 3.3 Ω 220 µF 3.3 Ω
50 V 50 V
PVDD/2 PVDD/2
220 µF 220 µF
50 V 50 V
PVDD
10 Ω 3.3 Ω
100 nF
GVDD 10 nF 1000 µF
47 µF 50 V
10 µF 50 V
10 Ω 50 V
10 nF
TAS5152DKD
50 V
100 nF
1 36 100 nF
Microcontroller GVDD_B GVDD_A 100 V
33 nF 3.3 Ω
2 35
0Ω OTW BST_A
Optional 3 34 100 nF 10 µH @ 10 A
BKND_ERR SD PVDD_A 50 V
4 33
PWM_P_1 PWM_A OUT_A 470 nF
10 µH @ 10 A
5 32 63 V
VALID RESET_AB GND_A
6 31 100 nF
PWM_M_1 PWM_B GND_B 100 V 3.3 Ω
30 kΩ 30
7
OC_ADJ OUT_B
10 nF
8 29 50 V
GND PVDD_B
9 28 33 nF 100 nF 47 µF
AGND BST_B 50 V 50 V
100 nF 10 27
VREG BST_C 100 nF 47 µF
33 nF 50 V 50 V
11 26
M3 PVDD_C
TAS5508
12 25
M2 OUT_C
13 24 10 µH @ 10 A
M1 GND_C
14 23
PWM_C GND_D
10 µH @ 10 A
15 22
RESET_CD OUT_D
16 21
PWM_D PVDD_D
1Ω 17 20 100 nF 47 µF
GVDD VDD BST_D 50 V 50 V
100 nF 18 19 33 nF
10 µF GVDD_C GVDD_D
PVDD
10 Ω 100 nF 100 nF
3.3 Ω
10 nF 1000 µF
10 Ω
50 V 50 V
Figure 17. Typical Differential (2N) PBTL Application With AD Modulation Filters
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PVDD
10 Ω 3.3 Ω
100 nF
GVDD 10 nF 1000 µF
47 µF 50 V
10 µF 50 V
10 Ω 50 V
TAS5152DKD
100 nF
1 36
Microcontroller GVDD_B GVDD_A
33 nF
2 35
0Ω OTW BST_A
Optional 3 34 100 nF 10 µH @ 10 A
BKND_ERR SD PVDD_A 50 V
4 33
PWM_P_1 PWM_A OUT_A
10 µH @ 10 A 10 nF
5 32 50 V
VALID RESET_AB GND_A
6 31 100 nF
No connect PWM_B GND_B 100 V 3.3 Ω
30 kΩ 30
7
OC_ADJ OUT_B
8 29
GND PVDD_B
470 nF
9 28 33 nF 100 nF 47 µF 63 V
AGND BST_B 50 V 50 V
100 nF 10 27
VREG BST_C 100 nF 47 µF
33 nF 50 V 50 V 100 nF
11 26
M3 PVDD_C 100 V 3.3 Ω
TAS5508
12 25
M2 OUT_C 10 nF
13 24 10 µH @ 10 A
50 V
M1 GND_C
14 23
No connect PWM_C GND_D
10 µH @ 10 A
15 22
RESET_CD OUT_D
16 21
No connect PWM_D PVDD_D
1Ω 17 20 100 nF 47 µF
GVDD VDD BST_D 50 V 50 V
100 nF 18 19 33 nF
10 µF GVDD_C GVDD_D
PVDD
10 Ω 100 nF 100 nF
3.3 Ω
10 nF 1000 µF
10 Ω
50 V 50 V
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Note that asserting either RESET_AB or RESET_CD low Overcurrent (OC) Protection With Current
forces the SD signal high, independent of faults being Limiting and Overload Detection
present. TI recommends monitoring the OTW signal using
the system microcontroller and responding to an
overtemperature warning signal by, e.g., turning down the The device has independent, fast-reacting current
volume to prevent further heating of the device resulting in detectors with programmable trip threshold (OC threshold)
device shutdown (OTE). on all high-side and low-side power-stage FETs. See the
To reduce external component count, an internal pullup following table for OC-adjust resistor values. The detector
resistor to 3.3 V is provided on both SD and OTW outputs. outputs are closely monitored by two protection systems.
Level compliance for 5-V logic can be obtained by adding The first protection system controls the power stage in
external pullup resistors to 5 V (see the Electrical order to prevent the output current from further increasing,
Characteristics section of this data sheet for further i.e., it performs a current-limiting function rather than
specifications). prematurely shutting down during combinations of
high-level music transients and extreme speaker load
impedance drops. If the high-current situation persists,
i.e., the power stage is being overloaded, a second
protection system triggers a latching shutdown, resulting
DEVICE PROTECTION SYSTEM
in the power stage being set in the high-impedance (Hi-Z)
state. Current limiting and overload protection are
TAS5152 contains advanced protection circuitry carefully independent for the half-bridges A and B and, respectively,
designed to facilitate system integration and ease of use, C and D. That is, if the bridge-tied load between
as well as to safeguard the device from permanent failure half-bridges A and B causes an overload fault, only
due to a wide range of fault conditions such as short half-bridges A and B are shut down.
circuits, overload, overtemperature, and undervoltage.
The TAS5152 responds to a fault by immediately setting
the power stage in a high-impedance state (Hi-Z) and D For the lowest-cost bill of materials in terms
asserting the SD pin low. In situations other than overload, of component selection, the OC threshold
the device automatically recovers when the fault condition measure should be limited, considering the
has been removed, i.e., the junction temperature has power output requirement and minimum
dropped or the voltage supply has increased. For highest load impedance. Higher-impedance loads
possible reliability, recovering from an overload fault require a lower OC threshold.
requires external reset of the device (see the Device Reset D The demodulation-filter inductor must retain
section of this data sheet) no sooner than 1 second after at least 3 µH of inductance at twice the OC
the shutdown. threshold setting.
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Unfortunately, most inductors have decreasing inductance resulting in all half-bridge outputs being set in the
with increasing temperature and increasing current high-impedance state (Hi-Z) and SD being asserted low.
(saturation). To some degree, an increase in temperature OTE is latched in this case. To clear the OTE latch, both
naturally occurs when operating at high output currents, RESET_AB and RESET_CD must be asserted.
due to core losses and the DC resistance of the inductor’s Thereafter, the device resumes normal operation.
copper winding. A thorough analysis of inductor saturation
Undervoltage Protection (UVP) and Power-On
and thermal properties is strongly recommended. Reset (POR)
Setting the OC threshold too low might cause issues such The UVP and POR circuits of the TAS5152 fully protect the
as lack of enough output power and/or unexpected device in any power-up/down and brownout situation.
shutdowns due to too-sensitive overload detection. While powering up, the POR circuit resets the overload
In general, it is recommended to follow closely the external circuit (OLP) and ensures that all circuits are fully
component selection and PCB layout as given in the operational when the GVDD_X and VDD supply voltages
Application section. reach 9.8 V (typical). Although GVDD_X and VDD are
independently monitored, a supply voltage drop below the
For added flexibility, the OC threshold is programmable UVP threshold on any VDD or GVDD_X pin results in all
within a limited range using a single external resistor half-bridge outputs immediately being set in the
connected between the OC_ADJ pin and AGND. (See the high-impedance state (Hi-Z) and SD being asserted low.
Electrical Characteristics section of this data sheet for The device automatically resumes operation when all
information on the correlation between programming- supply voltages have increased above the UVP threshold.
resistor value and the OC threshold.) It should be noted
that a properly functioning overcurrent detector assumes
the presence of a properly designed demodulation filter at DEVICE RESET
the power-stage output. Short-circuit protection is not
provided directly at the output pins of the power stage but Two reset pins are provided for independent control of
only on the speaker terminals (after the demodulation half-bridges A/B and C/D. When RESET_AB is asserted
filter). It is required to follow certain guidelines when low, all four power-stage FETs in half-bridges A and B are
selecting the OC threshold and an appropriate forced into a high-impedance state (Hi-Z). Likewise,
demodulation inductor: asserting RESET_CD low forces all four power-stage
OC-Adjust Resistor Values Max. Current Before OC FETs in half-bridges C and D into a high-impedance state.
(kW) Occurs (A) Thus, both reset pins are well suited for hard-muting the
15 10.8
power stage if needed.
22 9.4 In BTL modes, to accommodate bootstrap charging prior
27 8.6 to switching start, asserting the reset inputs low enables
39 6.4
weak pulldown of the half-bridge outputs. In the SE mode,
the weak pulldowns are not enabled, and it is therefore
47 6
recommended to ensure bootstrap capacitor charging by
69 4.7 providing a low pulse on the PWM inputs when reset is
asserted high.
Overtemperature Protection
Asserting either reset input low removes any fault
The TAS5152 has a two-level temperature-protection
information to be signalled on the SD output, i.e., SD is
system that asserts an active-low warning signal (OTW)
forced high.
when the device junction temperature exceeds 125°C
(nominal) and, if the device junction temperature exceeds A rising-edge transition on either reset input allows the
155°C (nominal), the device is put into thermal shutdown, device to resume operation after an overload fault.
22
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Jun-2009
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Jun-2009
Pack Materials-Page 2
PACKAGE OUTLINE
DKD0036A SCALE 1.000
PowerPAD TM SSOP - 3.6 mm max height
PLASTIC SMALL OUTLINE
C
14.5 SEATING PLANE
TYP
13.9
A
PIN 1 ID AREA 0.1 C
34X 0.65
36
1
EXPOSED
THERMAL PAD
12.7 2X
16.0 12.6
11.05
15.8
NOTE 3
18
19
0.38
36X
0.25
0.12 C A B
(2.95)
5.9
5.8
11.1
B
10.9
NOTE 4
(0.15)
EXPOSED THERMAL PAD
3.6
3.1
(0.28) TYP
SEE DETAIL A
0.35
GAGE PLANE
1.1 0.3
0 -8 0.8 0.1
DETAIL A
TYPICAL
4222166/B 06/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. The exposed thermal pad is designed to be attached to an external heatsink.
www.ti.com
EXAMPLE BOARD LAYOUT
DKD0036A PowerPAD TM SSOP - 3.6 mm max height
PLASTIC SMALL OUTLINE
36X (0.45)
34X (0.65)
SYMM
(R0.05) TYP
18 19
(13.2)
EXPOSED
METAL EXPOSED
0.05 MAX 0.05 MIN METAL
AROUND AROUND
www.ti.com
EXAMPLE STENCIL DESIGN
DKD0036A PowerPAD TM SSOP - 3.6 mm max height
PLASTIC SMALL OUTLINE
36X (2)
SYMM
1
36
36X (0.45)
34X (0.65)
SYMM
(R0.05) TYP
18 19
(13.2)
4222166/B 06/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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