Beruflich Dokumente
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SCLS141E − DECEMBER 1982 − REVISED AUGUST 2003
D Wide Operating Voltage Range of 2 V to 6 V D Low Power Consumption, 80-µA Max ICC
D High-Current 3-State True Outputs Can D Typical tpd = 14 ns
Drive Up To 15 LSTTL Loads D ±6-mA Output Drive at 5 V
D Eight D-Type Flip-Flops in a Single Package D Low Input Current of 1 µA Max
D Full Parallel Access for Loading
SN54HC374 . . . J OR W PACKAGE SN54HC374 . . . FK PACKAGE
SN74HC374 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW)
(TOP VIEW)
VCC
OE
1Q
8Q
1D
OE 1 20 VCC
1Q 2 19 8Q 3 2 1 20 19
2D 4 18 8D
1D 3 18 8D 2Q 17 7D
5
2D 4 17 7D 3Q 6 16 7Q
2Q 5 16 7Q 3D 7 15 6Q
3Q 6 15 6Q 4D 8 14 6D
3D 7 14 6D 9 10 11 12 13
4D 8 13 5D
4Q
GND
CLK
5Q
5D
4Q 9 12 5Q
GND 10 11 CLK
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the ’HC374 devices are edge-triggered D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or
the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP − N Tube of 20 SN74HC374N SN74HC374N
Tube of 25 SN74HC374DW
SOIC − DW HC374
Reel of 2000 SN74HC374DWR
−40°C
−40 C to 85
85°C
C SOP − NS Reel of 2000 SN74HC374NSR HC374
SSOP − DB Reel of 2000 SN74HC374DBR HC374
Tube of 2000 SN74HC374PWR
TSSOP − PW HC374
Reel of 250 SN74HC374PWT
CDIP − J Tube of 20 SNJ54HC374J SNJ54HC374J
−55°C
−55 C to 125
125°C
C CFP − W Tube of 85 SNJ54HC374W SNJ54HC374W
LCCC − FK Tube of 55 SNJ54HC374FK
SNJ54HC374FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
! " #$%! " &$'(#! )!%* Copyright 2003, Texas Instruments Incorporated
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
&)$#!" #&(! ! 0
1 (( &%!%" % !%"!%)
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% $(%"" !+%-"% !%)*
(( !+% &)$#!" &)$#!
!%"!/ (( &%!%"* &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"*
FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUT
OE CLK D Q
L ↑ H H
L ↑ L L
L H or L X Q0
H X X Z
11
CLK
C1 2
3 1Q
1D 1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC374 SN74HC374
VCC UNIT
MIN MAX MIN MAX MIN MAX
2V 6 4 5
fclock Clock frequency 4.5 V 30 20 24 MHz
6V 35 24 28
2V 80 120 100
tw Pulse duration, CLK high or low 4.5 V 16 24 20 ns
6V 14 20 17
2V 100 150 125
tsu Setup time, data before CLK↑ 4.5 V 20 30 25 ns
6V 17 25 21
2V 10 13 12
th Hold time, data after CLK
CLK↑ 4.5 V 5 5 5 ns
6V 5 5 5
VCC
Reference 50%
VCC Input
High-Level 0V
50% 50%
Pulse tsu th
0V
tw Data VCC
90% 90%
Input 50% 50%
Low-Level VCC 10% 10% 0 V
Pulse 50% 50% tr tf
0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATIONS SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VCC Output
VCC
Input 50% 50% Control
50% 50%
(Low-Level
0V 0V
Enabling)
tPLH tPHL
tPZL tPLZ
In-Phase VOH Output ≈VCC ≈VCC
90% 90%
Output 50% 50% Waveform 1 50%
10% 10% V 10%
OL (See Note B) VOL
tr tf
tPHL tPLH tPZH tPHZ
VOH Output VOH
90% 90% 90%
Out-of- 50% 50% Waveform 2 50%
Phase 10% 10%
VOL (See Note B) ≈0 V
Output tf tr
www.ti.com 24-Aug-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
5962-8407101VRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8407101VR
A
SNV54HC374J
5962-8407101VSA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8407101VS
A
SNV54HC374W
84071012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84071012A
SNJ54HC
374FK
8407101RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 8407101RA
SNJ54HC374J
8407101SA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 8407101SA
SNJ54HC374W
JM38510/65602BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65602BRA
M38510/65602BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65602BRA
SN54HC374J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC374J
SN74HC374DBR ACTIVE SSOP DB 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC374
& no Sb/Br)
SN74HC374DW ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC374
& no Sb/Br)
SN74HC374DWE4 ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC374
& no Sb/Br)
SN74HC374DWG4 ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC374
& no Sb/Br)
SN74HC374DWR ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC374
& no Sb/Br)
SN74HC374DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC374
& no Sb/Br)
SN74HC374N ACTIVE PDIP N 20 20 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC374N
(RoHS)
SN74HC374NE4 ACTIVE PDIP N 20 20 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC374N
(RoHS)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2018
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Dec-2018
Pack Materials-Page 2
PACKAGE OUTLINE
DB0020A SCALE 2.000
TSSOP - 2 mm max height
SMALL OUTLINE PACKAGE
C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
18X 0.65 PLANE
20
1
2X
7.5
5.85
6.9
NOTE 3
10
11 0.38
20X
0.22
5.6 0.1 C A B
B
5.0
NOTE 4
2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE
DETAIL A
A 15
TYPICAL
4214851/A 12/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A TSSOP - 2 mm max height
SMALL OUTLINE PACKAGE
1 (R0.05) TYP
20X (0.45) 20
SYMM
18X (0.65)
10 11
(7)
4214851/A 12/2017
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A TSSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
18X (0.65)
10 11
(7)
4214851/A 12/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC
13.0 2X
12.6 11.43
NOTE 3
10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4
0.33
TYP
0.10
0.25
SEE DETAIL A GAGE PLANE
1.27 0.3
0 -8 0.40 0.1
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10 11
(9.3)
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
10 11
(9.3)
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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