1.What is Mosfet?

Explain types, Operating regions,VI charateristcs,transfer

characteristics,threshold voltage?
2. What happens if Vds is increased over saturation?
3. In the I-V characteristics curve, why is the saturation curve flat or constant?
4. why do we operate a MOSFET in saturation when we use them for switching purpose
ANSWER:
MOSFET is a voltage controlled field effect transistor that differs from a JFET in
that it has a “Metal Oxide” Gate electrode which is electrically insulated from the
main semiconductor n-channel or p-channel by a very thin layer of insulating
material usually silicon dioxide, commonly known as glass.
This ultra thin insulated metal gate electrode can be thought of as one plate of a
capacitor. The isolation of the controlling Gate makes the input resistance of
the MOSFET extremely high way up in the Mega-ohms ( MΩ ) region thereby
making it almost infinite.
As the Gate terminal is isolated from the main current carrying channel “NO
current flows into the gate” and just like the JFET, the MOSFET also acts like a
voltage controlled resistor were the current flowing through the main channel
between the Drain and Source is proportional to the input voltage. Also like the
JFET, the MOSFETs very high input resistance can easily accumulate large
amounts of static charge resulting in the MOSFET becoming easily damaged unless
carefully handled or protected.
Like the previous JFET tutorial, MOSFETs are three terminal devices with
a Gate, Drainand Source and both P-channel (PMOS) and N-channel (NMOS)
MOSFETs are available. The main difference this time is that MOSFETs are
available in two basic forms:
● Depletion Type – the transistor requires the Gate-Source voltage, ( V ) GS

to switch the device “OFF”. The depletion mode MOSFET is equivalent to a

“Normally Closed” switch.
● Enhancement Type – the transistor requires a Gate-Source voltage,
( VGS ) to switch the device “ON”. The enhancement mode MOSFET is
equivalent to a “Normally Open” switch.
The symbols and basic construction for both configurations of MOSFETs are
shown below.
The four MOSFET symbols above show an additional terminal called
the Substrate and is not normally used as either an input or an output connection
but instead it is used for grounding the substrate. It connects to the main
semiconductive channel through a diode junction to the body or metal tab of the
MOSFET.
Usually in discrete type MOSFETs, this substrate lead is connected internally to
the source terminal. When this is the case, as in enhancement types it is omitted
from the symbol for clarification.
The line between the drain and source connections represents the semiconductive
channel. If this is a solid unbroken line then this represents a “Depletion”
(normally-ON) type MOSFET as drain current can flow with zero gate potential. If
the channel line is shown dotted or broken it is an “Enhancement” (normally-OFF)
type MOSFET as zero drain current flows with zero gate potential. The direction
of the arrow indicates whether the conductive channel is a p-type or an n-type
semiconductor device.
Basic MOSFET Structure and Symbol

The construction of the Metal Oxide Semiconductor FET is very different to that of
the Junction FET. Both the Depletion and Enhancement type MOSFETs use an
electrical field produced by a gate voltage to alter the flow of charge carriers,
electrons for n-channel or holes for P-channel, through the semiconductive drain-
source channel. The gate electrode is placed on top of a very thin insulating layer
and there are a pair of small n-type regions just under the drain and source
electrodes.
We saw in the previous tutorial, that the gate of a junction field effect transistor,
JFET must be biased in such a way as to reverse-bias the pn-junction. With a
insulated gate MOSFET device no such limitations apply so it is possible to bias
the gate of a MOSFET in either polarity, positive (+ve) or negative (-ve).
This makes the MOSFET device especially valuable as electronic switches or to
make logic gates because with no bias they are normally non-conducting and this
high gate input resistance means that very little or no control current is needed as
MOSFETs are voltage controlled devices. Both the p-channel and the n-channel
MOSFETs are available in two basic forms, the Enhancement type and
the Depletion type.

Depletion-mode MOSFET
The Depletion-mode MOSFET, which is less common than the enhancement mode
types is normally switched “ON” (conducting) without the application of a gate
bias voltage. That is the channel conducts when VGS = 0 making it a “normally-
closed” device. The circuit symbol shown above for a depletion MOS transistor
uses a solid channel line to signify a normally closed conductive channel.
For the n-channel depletion MOS transistor, a negative gate-source voltage, -
VGS will deplete (hence its name) the conductive channel of its free electrons
switching the transistor “OFF”. Likewise for a p-channel depletion MOS transistor
a positive gate-source voltage, +VGS will deplete the channel of its free holes
turning it “OFF”.
In other words, for an n-channel depletion mode MOSFET: +VGS means more
electrons and more current. While a -VGS means less electrons and less current. The
opposite is also true for the p-channel types. Then the depletion mode MOSFET is
equivalent to a “normally-closed” switch.

Depletion-mode N-Channel MOSFET and circuit Symbols

The depletion-mode MOSFET is constructed in a similar way to their JFET

transistor counterparts were the drain-source channel is inherently conductive with
the electrons and holes already present within the n-type or p-type channel. This
doping of the channel produces a conducting path of low resistance between
the Drain and Sourcewith zero Gate bias.

Enhancement-mode MOSFET
The more common Enhancement-mode MOSFET or eMOSFET, is the reverse of
the depletion-mode type. Here the conducting channel is lightly doped or even
undoped making it non-conductive. This results in the device being normally
“OFF” (non-conducting) when the gate bias voltage, VGS is equal to zero. The
circuit symbol shown above for an enhancement MOS transistor uses a broken
channel line to signify a normally open non-conducting channel.
For the n-channel enhancement MOS transistor a drain current will only flow when
a gate voltage ( VGS ) is applied to the gate terminal greater than the threshold
voltage ( VTH ) level in which conductance takes place making it a transconductance
device.
The application of a positive (+ve) gate voltage to a n-type eMOSFET attracts
more electrons towards the oxide layer around the gate thereby increasing or
enhancing (hence its name) the thickness of the channel allowing more current to
flow. This is why this kind of transistor is called an enhancement mode device as
the application of a gate voltage enhances the channel.
Increasing this positive gate voltage will cause the channel resistance to decrease
further causing an increase in the drain current, ID through the channel. In other
words, for an n-channel enhancement mode MOSFET: +VGS turns the transistor
“ON”, while a zero or -VGS turns the transistor “OFF”. Then, the enhancement-
mode MOSFET is equivalent to a “normally-open” switch.
The reverse is true for the p-channel enhancement MOS transistor.
When VGS = 0 the device is “OFF” and the channel is open. The application of a
negative (-ve) gate voltage to the p-type eMOSFET enhances the channels
conductivity turning it “ON”. Then for an p-channel enhancement mode
MOSFET: +VGS turns the transistor “OFF”, while -VGSturns the transistor “ON”.

Enhancement-mode N-Channel MOSFET and Circuit

Symbols
Enhancement-mode MOSFETs make excellent electronics switches due to their
low “ON” resistance and extremely high “OFF” resistance as well as their
infinitely high input resistance due to their isolated gate. Enhancement-mode
MOSFETs are used in integrated circuits to produce CMOS type Logic Gates and
power switching circuits in the form of as PMOS (P-channel) and NMOS (N-
channel) gates. CMOS actually stands for Complementary MOS meaning that the
logic device has both PMOS and NMOS within its design.

The MOSFET Amplifier

Just like the previous Junction Field Effect transistor, MOSFETs can be used to
make single stage class “A” amplifier circuits with the enhancement mode n-
channel MOSFET common source amplifier being the most popular circuit. The
depletion mode MOSFET amplifiers are very similar to the JFET amplifiers,
except that the MOSFET has a much higher input impedance.
This high input impedance is controlled by the gate biasing resistive network
formed by R1 and R2. Also, the output signal for the enhancement mode common
source MOSFET amplifier is inverted because when VG is low the transistor is
switched “OFF” and VD(Vout) is high. When VG is high the transistor is switched
“ON” and VD (Vout) is low as shown.

Enhancement-mode N-Channel MOSFET Amplifier

The DC biasing of this common source (CS) MOSFET amplifier circuit is virtually
identical to the JFET amplifier. The MOSFET circuit is biased in class A mode by
the voltage divider network formed by resistors R1 and R2. The AC input
resistance is given as RIN = RG = 1MΩ.
Metal Oxide Semiconductor Field Effect Transistors are three terminal active
devices made from different semiconductor materials that can act as either an
insulator or a conductor by the application of a small signal voltage.
The MOSFETs ability to change between these two states enables it to have two
basic functions: “switching” (digital electronics) or “amplification” (analogue
electronics). Then MOSFETs have the ability to operate within three different
regions:
● 1. Cut-off Region – with V < V GS the gate-source voltage is lower
threshold

than the threshold voltage so the MOSFET transistor is switched “fully-

OFF” and IDS = 0, the transistor acts as an open circuit
● 2. Linear (Ohmic) Region – with V > V and VDS < VGS the
GS threshold

transistor is in its constant resistance region and behaves as a voltage-

controlled resistor whose resistive value is determined by the gate
voltage, VGS
● 3. Saturation Region – with V > V GS the transistor is in its constant
threshold

current region and is switched “fully-ON”. The current IDS = maximum as the
transistor acts as a closed circuit
MOSFET Summary
The Metal Oxide Semiconductor Field Effect Transistor, or MOSFET for short, has
an extremely high input gate resistance with the current flowing through the
channel between the source and drain being controlled by the gate voltage.
Because of this high input impedance and gain, MOSFETs can be easily damaged
by static electricity if not carefully protected or handled.
MOSFET’s are ideal for use as electronic switches or as common-source amplifiers
as their power consumption is very small. Typical applications for metal oxide
semiconductor field effect transistors are in Microprocessors, Memories,
Calculators and Logic CMOS Gates etc.
Also, notice that a dotted or broken line within the symbol indicates a normally
“OFF” enhancement type showing that “NO” current can flow through the channel
when zero gate-source voltage VGS is applied.
A continuous unbroken line within the symbol indicates a normally “ON”
Depletion type showing that current “CAN” flow through the channel with zero
gate voltage. For p-channel types the symbols are exactly the same for both types
except that the arrow points outwards. This can be summarised in the following
switching table.

MOSFET type VGS = +ve VGS = 0 VGS = -ve

N-Channel Depletion ON ON OFF

N-Channel Enhancement ON OFF OFF

P-Channel Depletion OFF ON ON

P-Channel Enhancement OFF OFF ON

So for n-type enhancement type MOSFETs, a positive gate voltage turns “ON” the
transistor and with zero gate voltage, the transistor will be “OFF”. For a p-channel
enhancement type MOSFET, a negative gate voltage will turn “ON” the transistor
and with zero gate voltage, the transistor will be “OFF”. The voltage point at
which the MOSFET starts to pass current through the channel is determined by the
threshold voltage VTH of the device.
In the next tutorial about Field Effect Transistors instead of using the transistor as an
amplifying device, we will look at the operation of the transistor in its saturation
and cut-off regions when used as a solid-state switch. Field effect transistor
switches are used in many applications to switch a DC current “ON” or “OFF”
such as LED’s which require only a few milliamps at low DC voltages, or motors
which require higher currents at higher voltages.
5.what is BJT?

6. what are different types of BJT configurations and when do we use them.

7. why do we operate a BJT in saturation when we use them for switching purpose

Bipolar Junction Transistor or BJT

In 1947 J. Barden, W. Bratterin and W. Shockley invented transistor. The term transistor was
given by John R. Pierce. Through initially it was called the solid state version of the vacuum
triode, but the term transistor has survived. As we will go through the topic, we will know
about the transistor, mainly bipolar junction transistor or BJT. Nowadays the use of BJT’s
has declined towards CMOS technology in the design of IC’s. The word transistor is derived
from the words “Transfer” and “Resistor” it describes the operation of a BJT i.e. the transfer
of an input signal from a low resistance circuit to a high resistance circuit. This type of
transistor is made up of semiconductors. We know that silicon (Si) and Germanium (Ge) are
the examples of semiconductors. Now, why this is called junction transistor? The answer lies
behind the construction. We already know what is p-type and n-type semiconductors.

Now, in this type of transistor any one type of semiconductors is sandwiched between the
other type of semiconductor. For example, an n - type can be sandwiched between two p-type
semiconductors or similarly one p-type can be sandwiched between two n-type
semiconductors. These are called p-n-p and n-p-n transistors respectively. We will discuss
about them later. Now as there are two junctions of different types of semiconductors, this is
called junction transistor. It’s called bipolar because the conduction takes place due to both
electrons as well as holes.

Definition of BJT
A bipolar junction transistor is a three terminal semiconductor device consisting of two p-n
junctions which is able to amplify or magnify a signal. It is a current controlled device. The
three terminals of the BJT are the base, the collector and the emitter. A signal of small
amplitude if applied to the base is available in the amplified form at the collector of the
transistor. This is the amplification provided by the BJT. Note that it does require an external
source of DC power supply to carry out the amplification process.
The basic diagrams of the two types of bipolar junction transistors mentioned above are given
below.
 From the above figure, we can see that every BJT has three parts named emitter, base and
collector. JE and JCrepresent junction of emitter and junction of collector respectively. Now
initially it is sufficient for us to know that emitter based junction is forward biased and
collector base junctions is reverse biased. The next topic will describe the two types of this
transistors.

N-P-N Bipolar Junction Transistor

As started before in n-p-n bipolar transistor one p-type semiconductor resides between two
n-type semiconductors the diagram below a n-p-n transistor is shown

No
w IE, IC is emitter current and collect current respectively and VEB and VCB are emitter base
voltage and collector base voltage respectively. According to convention if for the emitter,
base and collector current IE, IBand IC current goes into the transistor the sign of the current is
taken as positive and if current goes out from the transistor then the sign is taken as negative.
We can tabulate the different currents and voltages inside the n-p-n transistor.

Transistor type IE IB IC VEB VCB VCE

n-p-n - + + - + +

P-N-P Bipolar Junction Transistor

Similarly for p-n-p bipolar junction transistor a n-type semiconductors is sandwiched
between two p-type semiconductors. The diagram of a p-n-p transistor is shown below

For p-n-
p transistors, current enters into the transistor through the emitter terminal. Like any bipolar
junction transistor, the emitter-base junction is forward biased and the collector-base junction
is reverse biased. We can tabulate the emitter, base and collector current, as well as the
emitter base, collector base and collector emitter voltage for p-n-p transistors also.

Transistor type IE IB IC VEB

p-n-p + - - +

Working Principle of BJT

Figure shows an n-p-n transistor biased in the active region (See transistor biasing), the BE
junction is forward biased whereas the CB junction is reversed biased. The width of the
depletion region of the BE junction is small as compared to that of the CB junction. The
forward bias at the BE junction reduces the barrier potential and causes the electrons to flow
from the emitter to base. As the base is thin and lightly doped it consists of very few holes so
some of the electrons from the emitter (about 2%) recombine with the holes present in the
base region and flow out of the base terminal. This constitutes the base current, it flows due
to recombination of electrons and holes (Note that the direction of conventional current flow
is opposite to that of flow of electrons). The remaining large number of electrons will cross
the reverse biased collector junction to constitute the collector current. Thus by KCL,
The base current is very small as compared to emitter and collector
current. Here, the majority charge carriers are electrons. The
operation of a p-n-p transistor is same as of the n-p-n, the only difference is that the majority
charge carriers are holes instead of electrons. Only a small part current flows due to majority
 carriers and most of the current flows due to minority charge carriers in a BJT. Hence, they
are called as minority carrier devices.

Equivalent Circuit of BJT

A p-n junction is represented by a diode. As a transistor has two p-n junctions, it is equivalent
to two diodes connected back to back. This is called as the two diode analogy of the BJT.

Bipolar Junction Transistors Characteristics

The three parts of a BJT are collector, emitter and base. Before knowing about the bipolar
junction transistor characteristics, we have to know about the modes of operation for this
type of transistors. The modes are

1. Common Base (CB) mode

2. Common Emitter (CE) mode
3. Common Collector (CC) mode
All three types of modes are shown below

Now coming to the characteristics of BJT there are different characteristics for different
modes of operation. Characteristics is nothing but the graphical forms of relationships among
different current and voltage variables of the transistor. The characteristics for p-n-p
transistors are given for different modes and different parameters.

Common Base Characteristics

Input Characteristics
For p-n-p transistor, the input current is the emitter current (IE) and the input voltage is the
collector base voltage (VCB).
As the emitter - base junction is forward biased, therefore the graph of IE Vs VEB is similar to
the forward characteristics of a p-n diode. IE increases for fixed VEB when VCB increases.

Output Characteristics
The output characteristics shows the relation between output voltage and output current IC is
the output current and collector-base voltage and the emitter current IE is the input current and
works as the parameters. The figure below shows the output characteristics for a p-n-p
transistor in CB mode.
As we know for p-n-p transistors IE and VEB are positive and IC, IB, VCB are negative. These
are three regions in the curve, active region saturation region and the cut off region. The
active region is the region where the transistor operates normally. Here the emitter junction is
reverse biased. Now the saturation region is the region where both the emitter collector
junctions are forward biased. And finally the cut off region is the region where both emitter
and the collector junctions are reverse biased.

Common Emitter Characteristics

Input characteristics
IB (Base Current) is the input current, VBE (Base - Emitter Voltage) is the input voltage for CE
(Common Emitter) mode. So, the input characteristics for CE mode will be the relation
between IB and VBE with VCE as parameter. The characteristics are shown below
The typical CE input characteristics are similar to that of a forward biased of p-n diode. But
as VCB increases the base width decreases.
Output Characteristics
Output characteristics for CE mode is the curve or graph between collector current (IC) and
collector - emitter voltage (VCE) when the base current IB is the parameter. The characteristics
is shown below in the figure.
Like the output characteristics of common - base transistor CE mode has also three regions
named (i) Active region, (ii) cut-off regions, (iii) saturation region. The active region has
collector region reverse biased and the emitter junction forward biased. For cut-off region the
emitter junction is slightly reverse biased and the collector current is not totally cut-off. And
finally for saturation region both the collector and the emitter junction are forward biased.

Application of BJT
BJT's are used in discrete circuit designed due to availability of many types, and obviously
because of its high transconductane and output resistance which is better than MOSFET.
BJT's are suitable for high frequency application also. That’s why they are used in radio
frequency for wireless systems. Another application of BJT can be stated as small signal
amplifier, metal proximity photocell, etc.

Bipolar Junction Transistor Amplifier

To understand the concept of Bipolar Junction Transistor Amplifier, we should look
through the diagram of a p-n-p transistor first.
Now as the input voltage is changed a little, say ΔV i of the emitter-base voltage changes the
barrier height and the emitter current by ΔIE. This change in emitter current develops a
voltage drop ΔVO across the load resistance RL, where,
ΔVO gives the output voltage of the amplifier. There is a negative sign
because of the collector current gives a voltage drop across RL with polarity opposite to the
reference polarity. The voltage gain AV for the amplifier is given the ratio between the output

voltages ΔVO to the input voltage ΔVi, so, is

called the current gain ratio of the transistor. From the figure diagram shown above we can
see that an increase in the emitter voltage reduces the forward bias at the emitter junction thus
decreases the collector current. It indicates that the output voltage and the input voltage are in
phase. Now, finally the power gain Ap of the transistor is the ratio between the output power

and the input power

Regions of operation[edit]

B-C
Applied B-E junction
junction Mode (NPN)
voltages bias (NPN)
bias (NPN)

E<B<C Forward Reverse Forward-active

E<B>C Forward Forward Saturation

E>B<C Reverse Reverse Cut-off

 E>B>C Reverse Forward Reverse-active

B-C
Applied B-E junction
junction Mode (PNP)
voltages bias (PNP)
bias (PNP)

E<B<C Reverse Forward Reverse-active

E<B>C Reverse Reverse Cut-off

E>B<C Forward Forward Saturation

E>B>C Forward Reverse Forward-active

Bipolar transistors have four distinct regions of operation, defined by BJT junction biases.
Forward-active (or simply active)
The base–emitter junction is forward biased and the base–collector junction is reverse
biased. Most bipolar transistors are designed to afford the greatest common-emitter
current gain, βF, in forward-active mode. If this is the case, the collector–emitter
current is approximately proportional to the base current, but many times larger, for
small base current variations.
Reverse-active (or inverse-active or inverted)
By reversing the biasing conditions of the forward-active region, a bipolar transistor
goes into reverse-active mode. In this mode, the emitter and collector regions switch
roles. Because most BJTs are designed to maximize current gain in forward-active
mode, the βF in inverted mode is several times smaller (2–3 times for the ordinary
germanium transistor). This transistor mode is seldom used, usually being considered
only for failsafe conditions and some types of bipolar logic. The reverse bias
breakdown voltage to the base may be an order of magnitude lower in this region.
Saturation
With both junctions forward-biased, a BJT is in saturation mode and facilitates high
current conduction from the emitter to the collector (or the other direction in the case
of NPN, with negatively charged carriers flowing from emitter to collector). This
mode corresponds to a logical "on", or a closed switch.
Cut-off
In cut-off, biasing conditions opposite of saturation (both junctions reverse biased) are
present. There is very little current, which corresponds to a logical "off", or an open
switch.
Avalanche breakdown region
 The relationship between , and

The modes of operation can be described in terms of the applied voltages

(this description applies to NPN transistors; polarities are reversed for PNP
transistors):
Forward-active
Base higher than emitter, collector higher than base (in this mode the collector current
is proportional to base current by ).

Saturation
Base higher than emitter, but collector is not higher than base.
Cut-off
Base lower than emitter, but collector is higher than base. It means the transistor is not
letting conventional current go through from collector to emitter.
Reverse-active
Base lower than emitter, collector lower than base: reverse conventional current goes
through transistor.
In terms of junction biasing: (reverse biased base–collector
junction means Vbc < 0 for NPN, opposite for PNP)
Although these regions are well defined for sufficiently large
applied voltage, they overlap somewhat for small (less than a
few hundred millivolts) biases. For example, in the typical
grounded-emitter configuration of an NPN BJT used as a
pulldown switch in digital logic, the "off" state never
involves a reverse-biased junction because the base voltage
never goes below ground; nevertheless the forward bias is
close enough to zero that essentially no current flows, so this
end of the forward active region can be regarded as the cutoff
region.
8. What is difference between latch and flipflop?

The main difference between latch and FF is that latches are level sensitive while FF
are edge sensitive. They both require the use of clock signal and are used in sequential logic.
For a latch, the output tracks the input when the clock signal is high, so as long as the clock is
logic 1, the output can change if the input also changes. FF on the other hand, will store the
input only when there is a rising/falling edge of the clock.

9.What is DFII ?

Cadence Design Framework II (dfII) consists of Cadence tools for design management
(Library Manager), schematic entry (Virtuoso Schematics), physical layout (Virtuoso
Layout), verification (Assura), and simulation (Spectre).
Cadence Design Framework II is only installed on the SPARC Solaris ≥7 platform and
it requires a paletted 8-bit (256-colour) display

10.What is GDS?

GDSII stream format, common acronym GDSII, is a database file format which is
the de facto industry standard for data exchange of integrated circuit or IC layout artwork.
It is a binary file format representing planar geometric shapes, text labels, and other
information about the layout in hierarchical form. The data can be used to reconstruct all
or part of the artwork to be used in sharing layouts, transferring artwork between different
tools, or creating photomasks.
It was originally developed by Calma for its layout design software, "Graphic Data
System" ("GDS") and "GDSII".
GDS II files are usually the final output product of the IC design cycle and are given
to IC foundries for IC fabrication. GDS II files were originally placed on magnetic tapes.
This moment was fittingly called tape out though it is not the original root of the term.
Objects contained in a GDSII file are grouped by assigning numeric attributes to them
including a "layer number", "datatype" or "texttype". While these attributes were designed
to correspond to the "layers of material" used in manufacturing an integrated circuit, their
meaning rapidly became more abstract to reflect the way that the physical layout is
designed.
11. Why do we need poly end cap
 During fabrication due to the poly etch rate variation there may be a chances of drain and
source area may get shorted then the transistor will not work as expected. So to avoid it
we need to use poly end cap.

12. What is setup time and hold time?

13. What is Cross Talk?

In electronics, crosstalk (XT) is any phenomenon by which a signal transmitted on

one circuit or channel of a transmission system creates an undesired effect in
another circuit or channel. Crosstalk is usually caused by
undesired capacitive, inductive, or conductive coupling from one circuit, part of a
circuit, or channel, to another.
14. What happens when the PMOS and NMOS are interchanged with one another in an
inverter

It works as a degraded buffer.

15. How does Resistance of the metal lines vary with increasing thickness and increasing
length?

Resistance of uniform slab can be calculated by using

ρ l
R= ohms ......................(1)
t w

Here t = thickness

l = conductor length

w =conductor width

ρ= resistivity

Sheet resistance of metal can be calculated by

ρ
Rs= ohms
t

l
Then equation (1) becomes R=Rs . ohms
w

As per the formula, if you increase the thickness of the metal the resistance will
decrease.

If u increase the length of the metal the resistance will increase.

16. What happens, if the body or bulk of a MOSFET is left floating?

N-P junctions act as diodes, and because the layers of the mosfet have P-type and N-type
materials in close contact, diodes are formed from the body to the drain or source, as shown
the 4-terminal mosfet. If you were to leave the body connection floating, there could be no
voltage flow through the two PN body diodes because they are reverse connected to each
other.

17. Why dummies are required? (There expectation answer was related to well
proximity effect)
Dummys are used to protect the active devices, Due to the WPE effect the ions are
accumulated near the Nwell. Because of these ions the nearby devices threshold voltage may
vary. The dummy devices are placed near the well and then active devices are placed and
hence the effect is on dummy devices and active devices are protected.
18. What is latch up in CMOS? How it occurs and how to avoid it?
Why Guarding is done? (To reduce Substrate Resistance)
Because of more numbers of junctions in the Bulk CMOS structure, parasitic(we
don’t need them, but still exists) bipolar transistors are usually formed. The collector of each
BJT is connected to the base of the other transistor in a positive feedback structure. A
phenomenon called latch-up can occur when both BJT's conduct, creating a low resistance
path between Vdd and GND and the product of the gains of the two transistors in the
feedback loop, is greater than one. The result of latchup is at the minimum a circuit
malfunction, and in the worst case, the destruction of the device.

Latchup may begin when Vout drops below GND due to a noise spike or an improper circuit
hookup (Vout is the base of the lateral NPN Q2). If sufficient current flows through Rsub to
turn on Q2 (I Rsub > 0.7 V ), this will draw current through Rwell. If the voltage drop across
Rwell is high enough, Q1 will also turn on, and a self-sustaining low resistance path between
the power rails is formed. If the gains are such that b1 x b2 > 1, latchup may occur. Once
latchup has begun, the only way to stop it is to reduce the current below a critical level,
usually by removing power from the circuit.

Preventing latchup

1. Reduce the gain product b1 x b1

o move n-well and n+ source/drain farther apart increases width of the base of
Q2 and reduces gain beta2 > also reduces circuit density
o buried n+ layer in well reduces gain of Q1
2. Reduce the well and substrate resistances, producing lower voltage drops
o higher substrate doping level reduces Rsub
 o reduce Rwell by making low resistance contact to GND
o guard rings around p- and/or n-well, with frequent contacts to the rings,
reduces the parasitic resistances.

Guard rings are used to avoid latch up. We need to protect the precision circuit from
the substrate noise injected by the adjacent devices. Guard rings reduce the substrate
resistance and also attracts the minority carriers which are responsible for turn-on the
parasitic transistors. If not, substrate noise might cause the parasitic BJTs turn on, it may
results in low impedance path between power rails

19. Why guarding required?

Guard rings are used to avoid latch up. We need to protect the precision circuit from
the substrate noise injected by the adjacent devices. Guard rings reduce the substrate
resistance and also attracts the minority carriers which are responsible for turn-on the
parasitic transistors. If not, substrate noise might cause the parasitic BJTs turn on, it may
results in low impedance path between power rails.

20. If a block of transistors are covered by guarding from all sides, is there any need for
dummies to place at the end of the row?
Guard rings are used to avoid latch up and dummy’s are used to avoid poly etch rate
variations and to protect devices from WPE effect. So, dummy’s are added even though
guard rings are present.

21. Why we usually don’t put the dummies at all sides? Why we put dummies only at
the end of the row?
To minimize the etch effects during fabrication. Usually length of the transistor is of major
concern than width. So small variations in the width are accepted. Also poly caps will be
there on top and bottom, that reduces etch effects.
The poly end-caps are there at the top and bottom of the transistor that’s why
don’t need of dummys at the top and bottom of tx matching.
In sometimes for resistor matching we can use the dummies at top and bottom depends
on ckt designer guide lines.

22. What is Antenna Effect and how to avoid it?

During the Fabrication Process the large amount of charge is induced in plasma etching, ion
implantation and in other processes. If a large interconnect (Poly or other Conducting
material) is connected to the Gate of a MOSFET, then this larger conducting material will act
as Antenna and will receive the induced charge of the Fabrication Process.
The charge due to these extra carriers might be too much for the thin gate to handle it,
and it may also damage the thin oxide layer. So, Antenna effect may result in breakdown of
Gate Oxide or degrade the I-V Characteristics.
To avoid the antenna effect we need to avoid large Interconnect Area to Gate of a
MOSFET or we can also use the Antenna diode placed near the MOSFET, so that the diode
will provide a conductive path to substrate, if the induced charge is above a limit.
Charge accumulation on gate electrode or gate connected metal during
fabrication which raptures/brakes the gate oxide of the transistor is called antenna
effect. It’s also called plasma induced damage. During fabrication process the etching is
done by pour of gases or acids which contains large number of ions which accumulated
on the metal which applies large potential on the gate due to which gate oxide will break
down is called antenna effects.
The metal acts as antenna which receives charge and applies large voltage on
gate.
Avoiding techniques: ● Use metal jumpers
● Use Antenna diode.

● How antenna diode connected?

-We mostly use N-type diode. Because it don’t have any n-well. And faster than p-type.
If you use p-type again extra mask for N-well.
-1 terminal we will connect to gate and other terminal is automatically substrate (no
need to connect)
● Which diode you have used?
-n-type (don’t ever say reverse bias diode)

23. Where do you place the Antenna diode and what is the reason for it?
The Antenna diode placed near the MOSFET gate, so that the diode will provide a conductive
path to substrate, so that the charges on the metal discharge through the substrate and protects
the device.

24) What is Electro migration? How it will be taken care in a STD cell layout?
 Electro-migration is the gradual displacement of metal atoms in a semiconductor. It
occurs when the current density is high enough to cause the drift of metal ions in the direction
of the electron flow, and is characterized by the ion flux density. This density depends on the
magnitude of forces that tend to hold the ions in place, i.e., the nature of the conductor,
crystal size, interface and grain-boundary chemistry, and the magnitude of forces that tend to
dislodge them, including the current density, temperature and mechanical stresses.

There are two different EM failure mechanisms that occur due to asymmetry in the
ion flow. The first example in Figure 2 shows a void where the outgoing ion flux exceeds the
incoming ion flux, resulting in an open circuit. The second example shows a hillock where
the incoming ion flux exceeds the outgoing ion flux, resulting in a short circuit.

Electro-migration is the gradual displacement of metal atoms in a

semiconductor. It occurs when the current density is high enough to cause the drift of
metal ions in the direction of the electron flow, and is characterized by the ion flux
density. This density depends on the magnitude of forces that tend to hold the ions in
place, i.e., the nature of the conductor, crystal size, interface and grain-boundary
chemistry, and the magnitude of forces that tend to dislodge them, including the
current density, temperature and mechanical stresses.
To mitigate EM:
● Increase the width of the metal layer if area permits.
● Multiple vias: Multiple vias must be organized such that the resulting
current flow is distributed as evenly as possible through all the vias.
● 90-degree corner bends must be avoided, since the current density in such
bends is significantly higher than that in oblique angles.
● BY using low resistance metals.
25) If our metal has bending then where is more chance of Electro migration
happening? Why?

If our metal has bending then we are going to have more EM at the corners of the bending.
Since Current density is more in that area.

26) How Inverter Fabricated (Fabrication Steps)

 27) Top View and Cross Sectional View of Inverter

TOP VIEW

CROSS SECTIONAL

28) Inverter Characteristic with Regions

29) How PMOS or NMOS operates with graph(ID vs. VDS)
30) ESD

Static charge is an unbalanced electrical charge at rest. Typically, it is created by

insulator surfaces rubbing together or pulling apart. One surface gains electrons, while the
other surface loses electrons. This results in an unbalanced electrical condition known as
static charge. When a static charge moves from one surface to another, it becomes ESD. ESD
is a miniature lightning bolt of charge that moves between two surfaces that have different
potentials. It can occur only when the voltage differential between the two surfaces is
sufficiently high to break down the dielectric strength of the medium separating the two
surfaces. When a static charge moves, it becomes a current that damages or destroys, gate
oxide, metallization, and junctions. ESD can occur in any one of four different ways: a
charged body can touch an IC, a charged IC can touch a grounded surface, a charged machine
can touch an IC, or an electrostatic field can induce a voltage across a dielectric sufficient to
break it down.

31.About Matching and Types of MATCHING(Common Centroid and Inter Digit)

During fabrication process there may be variation in the gate oxide deposition, doping
concentration,( which are collectively called process gradients) due to which the
parameters(Vt,Id) of the devices may vary. To avoid this we are going to place the
devices in such a way that all the devices should have same effects. This pattern of
placing the devices is called Matching.

There are two types of matching technique.

1. Common Centroid

2. Inter Digitization
32.Which Matching type you prefer for Current Mirror circuit and Diff Pair circuit
and WHY?
Why interdigitization for current mirror? And common centroid for diff pair?

-In analog matching Vgs and Ids are more important to avoid mismatches.
-Voltages are more precise than current, so will use common centroid for diff pair.
-Because common centroid gives more precise matching and it will take more area than
interdigitization.
-We will use interdigitization as current mirror allows very small mismatch for currents.
-We can also use common centroid for current mirrors but it will take more area.
-To avoid that we will prefer interdigitization.
-Interdigitization is good for DC matching.

For current mirror we prefer inter-digitization, because inter-digitization is good for

matching DC condition.
For diff pair we prefer Common Centroid, because when the input differential signal
frequency is pretty high (like in RF or high speed IO/CML), the interdigi' structure will
cause cross-coupling between gate fingers. Obviously, common centroid is sort of free of
this problem.
EX:-
interdigi': ABAB
commoncentriod: A B
commoncentriod: B A

Interdigitation
◆ The simplest sort of common-centroid array consists of a series of devices arrayed in
one dimension.
■ One-dimensional common-centroid arrays are ideal for long, thin devices,
such as resistors.
■ Since the segments of the matched devices are slipped between one another to
form the array, the process is often called interdigitation.

◆ Not all interdigitated arrays are made equal!

■ Certain arrays precisely align the centroids of the matched devices (A, C).
These provide superior matching.
■ Other arrays only approximately align the centroids (B). These provide
inferior matching.
 2D Cross-coupled Arrays

◆ The simplest two-dimensional cross-coupled array contains four segments.

■ This type of array is called a cross-coupled pair.
■ For many devices, particularly smaller ones, the cross-coupled pair provides
the best possible layout.
■ More complicated 2D arrays containing more segments provide better
matching for large devices because they minimize the impact of nonlinearities.

33.Why Poly is kept extra at Active or OD?

The poly kept extra at active is called poly end cap. If we kept the poly in the same
level of active/OD region, while fabrication there may be chances of poly etch rate
variation due to which source and drain may short. So to avoid this we keep this poly
end cap.

There may be chance of active area of transistor may vary (reduction of active
area).

34.What is PITCH?
Pitch is the total distance of minimum width of metal and minimum space between
same metals. Metal means it may be poly or metal1 or metal2 and so on.

i.e., pitch= W+S

Here W is the width of the metal and S is the distance between two metals.
 Pitch is the sum of the minium space and minimum width of device or metals or
poly or contacts etc..

35.Why BULK is connected to Source?

The pn junctions defined by source-bulk and drain-bulk, which are basically two
diodes, must be reverse-biased to stop them from leaking current from the
source/drain to the substrate. That means that the source potential must always be
equal or greater than the bulk potential. Since drain voltage is always greater or equal
than source voltage, we don't even consider the drain-bulk junction.

36.What is Body Effect?

When VS>VB, the depletion width of the pn junction increases (remember the pn junction
depletion region?). That makes it more difficult to create a channel with the same VGS,
effectively reducing the channel depth. In order to return to the same channel
depth, VGS needs to increase accordingly. The body effect can be seen as a change in
threshold voltage.

37. Why Routing is not done with Ploy? (More Resistance and More Delay)

Routing with poly increases the Resistance and hence more Delay (RC Increases).

38. Expand the following:

1. DRC=Design Rule Check

2. LVS=Layout versus Schematic
3. ERC=Electrical Rule Check
4. CMOS=Complementary Metal Oxide Semiconductor
5. ESD=Electro Static Discharge
6. VLSI=Very Large Scale Integration
7. ADC=Analog to Digital Converter
8. DAC=Digital to Analog Converter
9. EOX=Electric field across oxide
10. EOS= Electrical overstress
11. STI=Shallow Trench Isolation
12. NSD=N-type Source Drain
13. PSD=P-type Source Drain
14. LDD= lightly doped drain

39. How does a MOS acts as a capacitor?

When source and drain terminals are shorted, it acts as a one terminal of the
capacitor and gate acts as another terminal and gate oxide acts as a dielectric between
these two.
40. How to differentiate Floor planning & Placement?

Floor planning refers to how standard cells and macros are placed in your die
area. While placement refers to how cells within these standard cells & macros are
placed.

Floorplaning

Goals of floor planning:

• arrange the blocks on a chip,
• decide the location of the I/O pads,
• decide the location and number of the power pads,
• decide the type of power distribution, and
• decide the location and type of clock distribution.

Objectives of floor planning are:

• To minimize the chip area, and

• minimize delay.

Placement

Goals:
● Guarantee the router can complete the routing step
● Minimize all the critical net delays
● Make the chip as dense as possible
Objectives:
(1) Minimize power dissipation
(2) Minimize crosstalk between signals

41.What is IR drop

The power supply in the chip is distributed uniformly through metal layers
(Vdd and Vss) across the design. These metal layers have finite amount of resistance.
When voltage is applied to this metal wires current start flowing through the metal
layers and some voltage is dropped due to that resistance of metal wires and current.
This Drop is called as IR Drop.

42. Well proximity effect (WPE)

Highly scaled bulk CMOS technologies make use of high energy implants to
form the deep retrograde well profiles needed for latch-up protection and suppression
of lateral punch-through. During the implant process, atoms can scatter laterally from
the edge of the photoresist mask and become embedded in the silicon surface in the
vicinity of the well edge as illustrated in Fig. The result is a well surface
concentration that changes with lateral distance from the mask edge, over the range
 of 1um or more. This lateral non-uniformity in well doping causes the MOSFET
threshold voltages and other electrical characteristics to vary with the distance of the
transistor to the well-edge. This phenomenon is commonly known as the well
proximity effect (WPE).

WPE effect can be reduced by placing the active devices away from well edge
and placing dummies beside the active devices.

43. Length of diffusion effect (LOD)

Length of diffusion (LOD) effect is nothing but shallow trench isolation (STI)
effect. the trenches do mechanical stress on the MOS causing change in the MOS
behavior according to how far it is from the trench so using dummy fingers decrease
this effect cause u put the fingers far from the trench while using multipliers is better
cause all the MOS will have the same stress (better matched).
 Due to this the current in the NMOS and PMOS transistors got affected. To
avoid this effect in layout you have to avoid shearing the active regions for the
matched pairs like current mirrors, diff pairs... in other wards try using single or
double figure devices for the matching purpose. Do not use more than 2 or 3 fingers
in the layout especially for the current mirrors and diff pairs.

44.What are 7 tracks in STD cell? How will you calculate the height of the std cell?

Track is generally used as a unit to define the height of the STD cell.
Track= min metal2 width + min space between metal2
7 tracks= 7*Track
Note: Track width = metal width.
Track spacing = metal min spacing.

45.What is the difference between 7 track and 12 track library?

One track is approximately the minimum spacing between metal1 and metal1
via in a technology node. Track is generally used as a unit to define the height of the
STD cell. a 12 track cell will be taller than a 7 track cell. a 12 track std cell will be
taller , that means more metal1 routing space is available within the cell, hence cells
will be faster. Where as in a 7 track cell, the cell will be compact, but speed is less
compared to 12 tracks.
7track -> less area, less speed compared to 12 tracks.
12track -> more area, more speed compared to 7 tracks.

46.Is it possible to make from 12 tracks to 9 track library or visa-versa? What are the
issues while doing this?

We can make 9 track libraries from 12 tracks. There is no issue while doing 12
track libraries from 9 tracks but while doing 9 tracks from the 12 tracks there will be
a area issue and more congestion.

47. What are the types of STD cell libraries? What is the difference between HVT and
LVT standard cells apart from the layer?

The standard cell libraries provide three separate architectures, high-speed

(HS), high-density (HD) and ultra high-density (UHD), to optimize circuits for
performance, power and area tradeoffs.
The standard cell libraries include multiple voltage threshold implants (VTs),
appropriate VT cells have to be chosen as per whether the design is timing critical or
power critical.
HVT: High V threshold cells consume less power (since speed of operation is less
and hence less leakage) used in the paths where timing is not critical.
 LVT: Low V threshold cells are used in timing critical paths. These cells are fast but
consume more power due to its leakage. So use only when timing is critical.
SVT: Standard V threshold. Best of both world. These cells have Medium delay and
medium power requirement. So if timing is not met by small margin with HVT, you
should try with SVT and at last LVT.
It is better to use low vt cells for timing critical path and high vt cells for non-
timing critical path so that power target can be achieved

48. How will you draw the good layout? Or what are the main steps to do the better
layout?

● Same poly and metal routing orientation throughout the circuit

● Proper floorplannig, placement and routings.
● By using matching techniques: diff pair, current mirror, resistor, capacitor,
BJT's etc.,
● Avoid unnecessary routing
● Shielding critical nets
● Use minimum two via contacts
● Use dummies
● Avoid metal bending(except in preventing EM)

49. What is LEF? How you will create abstract views?

The LEF file is an ASCII representation of the Abstract. A Library Exchange

Format (LEF) file contains library information for a class of designs. Library data
includes layer, via, placement site type, and macro cell definitions.
The abstract view provides information like: „ Cell name, site name, cell
orientation, Cell PR boundary, Pin names, locations, pin metal layer, type and
direction (input/output/input-output). Also provides location of all metal track and
vias in the layout (obstructions). This information is passed to the P & R tool in the
LEF format (Library Exchange Format). The LEF file contains technology
information along with all the cell descriptions. We will use Cadence Abstract
Generator tool for producing the abstract view from your standard cell layout view

50. What is PNR? What are the uses of PNR?

PNR is placement and routing
Placement:
After you have done floor planning, i.e. created the core area, placed the
macros, and decided the power network structure of your design, it is time to do
standard cell placement. We determine the location of each of the components (in
digital design, standard cell instantiations) on the die. Various factors come into play,
 like the timing requirement of the system, the interconnect lengths and hence the
connections between cells, power dissipation etc. The interconnect lengths depend on
the placement solution used, and it is very important in determining the performance
of the system as the geometries shrink. Placement also determines the routability of
your design.
Placement does not just place the standard cells available in the synthesized
netlist. It also optimizes the design, thereby removing any timing violations created
due to the relative placement on die.

Routing:
The routing process determines the precise paths for interconnections. This
includes the standard cell and macro pins, the pins on the block boundary or pads at
the chip boundary,t he logical connectivity as defined by the netlist. In routing stage,
metal and vias are used to create the electrical connection in layout so as to complete
all connections

51. Why exactly the tracks are for in standard cells?

Track is the path in which wires can pass through. Track is generally used as a
unit to define the height of the standard cell. Standard cells are basic building blocks.
Device performance (speed) depends on height of the design, if height is more we
will get more space for horizontal metal routing then the area increases but speed is
more and vice versa.

52. Main differences between analog and digital layouts?

In Digital Layout, the W/L ratios used are the minimum feature size. This is
done to minimize the area and maximize the packing density. When the area is
minimized, the delay also gets minimized. Digital design is easier because we can use
cell-based methodology to do a layout, wherein you already have predefined layouts
of standard cells and use them to create larger blocks. This saves time and money.

Analog layout on the other hand is tougher as more importance is given to transistor
and interconnects details. This is done to acheive matching and the required currents
and voltages. Analog design is based mostly on the drain currents and bias voltages.
So, layout has to be done carefully to achieve these voltages and currents else the
design will fail when manufactured. In analog layout/design we trade off area for
performance.

53. metal usage in standard cell?

We usually use poly, metal 1 and maximum of metal 2 layer for routing in the
standard cell.

54. What are the things needed to start a standard cell layout
 In Standard cell layout in the design are layed out with standard dimensions
for heights, widths, actives and wells, and have standard power (vdd) and ground
(gnd) busses. All the standard cells in the library will have a fixed height, so what is
the track used is most important in standard cell library.

Other the things to be considered are the pin placement which can be
accessible from both left and right side.

Main thing in standard cell is it should follow abutment rule any std cell
should reside next to any other std cell.

55.Explain about DRM

Design Rules constitute the interface between semiconductor design and

manufacturing. Design rules are written by fab process engineers and reflect the
fabrication limitations for each drawn layer or combination of layers. Design rules are
captured in the Design Rule Manual (DRM). The DRM is a book published by the
foundry that represent a contract between the fab (or foundry) and the design house: if
the designers keep all physical design features “legal” according to the DRM description,
the resulting device can be fabricated successfully with good yield.

56. What is DFM? How OPC related to DFM?

Design for manufacturability (DFM) includes a set of techniques to modify

the design of integrated circuits (IC) in order to make them more manufacturable, i.e.,
to improve their functional yield, parametric yield, or their reliability.
Optical Proximity Correction OPC is used in lithography to increase the
achievable resolution and pattern transfer fidelity for IC manufacturing. i.e.,to
compensate for image errors due to diffraction or process effects. The need for OPC
is seen mainly in the making of semiconductor devices and is due to the limitations of
light to resolve ever-finer details of patterns on the photo masks that are used to etch
semiconductor passivation layers and create the building blocks of the transistors and
other elements that make up integrated circuits. These projected images appear with
irregularities such as rounded corners and with trace widths that are narrower than
designed.
DFM will allow potential problems to be fixed in the design phase which is
the least expensive place to address them. Hence these irregularities should be
anticipated in the design phase itself so that manufacturing yield increases.

57. Why n-well process used mostly for IC Fabrication?why not using n-substrate?

In design we use multiple positive voltages and common ground. So entire psub is
connected to gnd and n-well can be isolated and connected to multiple supplies. But if we
take nsub how can we connect it to multiple supplies. Then we have to use twin well process
which is costly process.

58.Why nmos is more preferred/ why not using n-substrate?

 The mobility of the carrier for nmos is higher than pmos. So, with small w/l of nmos
we can get what pmos can give. That means small real estate for nmos in IC which mean
lower cost for product. There are few more reason in term of performance in which nmos is
better. In fact, before we have CMOS tech, circuitry was made up by nmos. So, I don't see
any good reason to use n-sub instead of p-sub.

59. which gate is preferred more NAND or NOR and Why?

NAND gate is preferred more, because

1. NAND offers less delay.

As you were saying, the equation for delay is

Delay=t(gh+p)
But the logical effort g for NAND is less than that of NOR. Consider the figure
showing 2 input CMOS NAND and NOR gate. The number against each
transistor is a measure of size and hence capacitance.

The logical effort can be calculated as g=Cin/3. Which gives

● g=4/3 for 2 input NAND and g=n+23 for n input NAND gate
● g=5/3 for 2 input NOR and g=2n+13 for n input NOR gate
 h=1 for a gate (NAND or NOR) driving the same gate and p=2 for both NAND and
NOR. Hence NAND has lesser delay when compared with NOR.

2. NOR occupies more area.

Adding the sizes of transistors in figure, it is clear that size of NOR is greater than that
of NAND. And this difference in size will increase as the number of inputs are
increased.
NOR gate will occupy more silicon area than NAND gate.
3. NAND uses transistors of similar sizes.
Considering the figure again, all the transistors in NAND gate have equal size where
as NOR gates don't. Which reduces manufacturing cost of NAND gate. When
considering gates with more inputs, NOR gates requires transistors of 2 different sizes
whose size difference is more when comparing with NAND gates.

60.What is the difference between a contact and a via? What is a "stacked" via process?

Via: a contact between two conductive layers.

Contact:Opening in an insulating film to allow contact to an underlying electronic device.
The placement of vias directly over the contacts or other,lower vias is known as stacked via.

61. Why higher metal layers are preferred for Vdd and Vss?

Because it has less resistance and hence leads to less IR drop.

62. What is signal integrity? How it affects Timing?
IR drop, Electro Migration (EM), Crosstalk, Ground bounce are signal
integrity issues.
If IR drop is more==>delay increases.
Crosstalk==>there can be setup as well as hold violation.

63. Differentiate between L and XL?

XL L

1.we can generate instances from the 1. we have to take instances manualy
schematic.

2. Easily map the devices and nets 2.not available

between Schematic and layout

3.XL probe is available 3.Not available.

64. What are the Differences between BJT&MOSFET?

BJT
1.It is faster
2.Low package density
3.Fabrication cost is more
4.Power dissipation more
5.high driving capability
6.cuurent controlled device
7.Low NM
MOSFET
1.It is slower compare to BJT
2.High package density
3.Fabrication cost is less
4.power dissipation is less
5. low driving capability
6.voltage control device
7.high NM(noise margin)

65. LVS and DRC Errors

LVS Errors:

Rewire: open and short wires

Nets: unmatched nets

Devices: One of the floating terminals in the device.

Pins: pins missing in the layout

Parameters: device properties changed

DRC Errors:

Min spacing

Min width

Min enclosure

Min extension

Stamping errors

Latch-up errors

66. what is meant by drive strength ?

in a CMOS circuit, what is meant by drive strength ? For example in TSMC cell library there
are cells labeled AOI221X1 AOI221X2 etc. What is the significance of X1, X2 etc. Kindly
give me a detailed reply by stating the defenition of drive strenth, signaifcance and factors
affecting drive strenth. In CMOS circuits the drive strength is the Current Capability of the
device i.e. Ids.

Ids can be increased by incresing the W/L ratio.

It is with this current the present state can drive the next stage i.e. charge the next stage
capacitance.

X1 means only one transistor(include a pmos and a nmos) in cells's drive stage.

X2 means two transistor in parallel in cells's drive stage..

x4 means four transistor in parallel in cells's drive stage.

more transistor, more current drive ability.

General it specifies the driving strength

xL--> 0.5xdriving strength of cell (low-drive cell)

x1--> 1x driving strength cell

x2--> 2x driving strength cell

etc...

gate drive strength

The symbols, 1X, 2X, 3X...etc in an ASIC flow in used for convinience. What it means is a
gate with 2X drive strength will have the same rise/fall time while driving a capacitance of
2C farads as that of a gate with X drive strength driving a capacitance of C farads. You can
look at the schematic and see that gates with 2X drive strengths have approximately twice the
widths on output pull up/pull down trasistors as comapred to the same gate with 1X drive
strength. Similarly definitions for 3X, 4X etc.

This is to ensure that ratio of width to load capacitance remains constant, thus resulting in the
same transition times. It is desired that the transition times in an ASIC chip be within a
certain limit (DRV critereon). This will be met if the following rule is followed -

If 1X drive strength is sufficient to drive a load of C farads (ie, transition time is satisfactory)
then 2X drive is satisfactory to drive loads between C farads and 2C farads, 3X drive is
sufficient to drive loads between 2C and 3C farads....etc.
drive strength is defined interms of basic gate i.e. NAND / NOT gate

let the basic gate is NOT

then X2 defines the gate you are using can drive cap ie is 2 times of NOT gate

generally NOT gate is used for define metrics in CMOS technology

67. Why is polysilicon used as a gate contact instead of metal in CMOS?

One reason for the initial switch to polysilicon is that fabrication processes after the
initial doping required very high temperature annealing. Metal gates would melt under such
conditions whereas polysilicon would not. Using polysilicon allowed for a one-step process
of etching the gates compared to elaborate multi-steps that we see today in metal-gate
processes.

The other reasons is that the threshold voltage of the MOSFET inversion layer is
correlated with the work-function difference between the gate and the channel. Using metal
would result in a higher Vt compared to polysilicon since a polysilicon gate would be of the
same or similar material composition as the bulk silicon channel.

As we reach smaller and smaller scales, the need for a higher Vt has become
important again due to problems of leakage. Higher conductivity in the gate has also become
important as the oxide dielectric layers cannot be shrunk any further to increase speed. Thus,
metal gates with a high-k dielectric are used in modern CMOS transistors.

68. Diff b/w fingering and multipliers?

- There is no difference between fingering and multipliers except distribution.

- You cannot distribute fingered device but a multiplier can.
If you take 2 fingers for 10 u device
Finger: - 1 device with 2 s/d and 1 s/d and 2 poly with 5um. You can’t separate
2 Poly.
Multiplier: - 2 devices with 1 s and 1 d and 1poly for each device with 5um. You
can distribute 2 Poly.
-But effective widths are same.

69. What is the alternate other than shielding?

-Placing clock or high freq nets away from other nets.

-By giving 1width and 2space.
Or
-Route near gnd and the other side provide 2space from other signals.

70. Constraints in standard cell?

-Grid should be set.

 -Tracks (height) should decide.
- PR boundary.
-power rails continuity.
-pin locations i/p left and o/p right.
-Metal routing use M1 only.
-Half DRC
-Boundary and abutment checks.

71. Soft check errors in LVS?

Soft check database is under ERC.

-Well not connected to Tap.
-Body connections
-Multiple substrates are not connected together.
-N-well floating etc.

72. Deep n-well?

Deep n-well is an extra n-well deeply trenched in to the global substrate to avoid noise
between to substrates. To isolate two different substrates.

● Why?
To isolate the local substrate from global substrate

● How it will isolate the wells?

- A deep n-well created in psub (Global) and in it a p-well is created for nmos and
we will have n-well for pmos.
Here psub is having global connection, the nmos is having its own p-well so bulk
of the nmos will directly goes to source of nmos instead psub (global).
So two substrates are isolated.

● Draw cross sectional for deep N-well?

 ● What is the advantage?
Noise isolation.
● Why we are not using normally?
Costly process. Because of extra layer.

73 .Explain about BJT matching? How you have done ?why we follow 1:8 pattern?

- Those are vertical PNP BJTs.

- Given 1:8 Pattern.
- So i have taken 1 reference BJT and 8 mirror BJTs.
- Placed reference BJT in the middle and mirrored BJTs are around the reference
one.
- So BJTs sees same effects from all the sides.
- Placed by row column instantiation to provide equal distances between BJTs.
- And connections done by m2 to keep m1 uniformity.

74.Single-Ended Vs Differential Inputs

One of the most common questions asked is the difference between single-ended and
differential inputs, and what applications they should be considered in. First, a simple
definition:

● DIFFERENTIAL INPUTS - A signal input circuit where SIGNAL LO and SIGNAL

HI are electrically floating with respect to ANALOG GROUND. For example, a
differential input A/D card will have one HI (+) and one LOW (-) pin for each input.
There will also be a LLGND (LOW LEVEL GROUND) pin which may be used if a
ground connection is required. This allows the measurement of the voltage difference
between two signals tied to the same ground and provides superior common-mode
noise rejection. Where should differential inputs be used? Whenever electromagnetic
interference (EMI) or radio frequency interference (RFI) is present, a voltage can be
induced on BOTH signal wires. A differential input amplifier will reject the
COMMON MODE VOLTAGE, provided that the common mode voltage plus the
 input signal does not exceed the device's CMR specification. The effect on a single-
ended input is usually a voltage fluctuation between signal high and signal ground.
● SINGLE-ENDED INPUTS - A single-ended input has no common mode range
because there is only ONE low wire, which is shared by all inputs. For example, if
you have an A/D board with 16 single-ended inputs, there will be 16 HIGH (+) lines
and one LOW (-) line (sometimes called LLGND). Some cards may have several
LOW lines to provide extra places to make your ground connection; however, these
lines are tied together and are basically the same thing.

WHEN TO USE SINGLE-ENDED OR DIFFERENTIAL INPUTS

Differential inputs provide a more stable reading when EMI or RFI is present, and therefore,
it is recommended to use them whenever noise is generally a problem. This is especially true
when measuring THERMOCOUPLE, STRAIN GAGE and BRIDGE TYPE PRESSURE
SENSOR inputs, since they produce very small signals that are very succeptible to noise.

Single-ended inputs are lower in cost, and provide twice the number of inputs for the same
size wiring connector, since they require only one analog HIGH (+) input per channel and
one LLGND (-) shared by all inputs. Differential inputs require signal HIGH and LOW
inputs for each channel and one common shared LLGND. Single-ended inputs save
connector space, cost, and are easier to install.

75.What is signal integrity?

A: Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital
electronics, a stream of binary values is represented by a voltage (or current) waveform.
However, digital signals are fundamentally analog in nature, and all signals are subject to
effects such as noise, distortion, and loss. Over short distances and at low bit rates, a simple
conductor can transmit this with sufficient fidelity. At high bit rates and over longer distances
or through various mediums, various effects can degrade the electrical signal to the point
where errors occur and the system or device fails. Signal integrity engineering is the task of
analyzing and mitigating these effects. It is an important activity at all levels of electronics
packaging and assembly, from internal connections of an integrated circuit (IC),through
the package, the printed circuit board (PCB), the backplane, and inter-system
connections. While there are some common themes at these various levels, there are also
practical considerations, in particular the interconnect flight time versus the bit period, that
cause substantial differences in the approach to signal integrity for on-chip connections
versus chip-to-chip connections.
Some of the main issues of concern for signal integrity are ringing, crosstalk, ground
bounce, distortion, signal loss, and power supply noise.
76. What is an integrator and differentiator?

A: The integrator produces a voltage output proportional to the product (multiplication) of

the input voltage and time; and the differentiator (not to be confused with differential)
produces a voltage output proportional to the input voltage’s rate of change.
● A differentiator circuit produces a constant output voltage for a steadily changing
input voltage.
● An integrator circuit produces a steadily changing output voltage for a constant input
voltage.
 ● Both types of devices are easily constructed, using reactive components (usually
capacitors rather than inductors) in the feedback part of the circuit.

77. What is Fan Out?

Fan-out is a term that defines the maximum number of digital inputs that the output of
a single logic gate can feed. Most transistor-transistor logic (TTL ) gates can feed up to 10
other digital gates or devices. Thus, a typical TTL gate has a fan-out of 10.

78. Why do we need a Gate Driver for Mosfet in Switching operations?

Maximizing the switching speed (driving gate capacitance).
79. What is thermal run away?
"Thermal runaway" describes a process which is accelerated by increased
temperature, in turn releasing energy that further increases temperature.
80.Why do we call BJT as current controlled device and MOSFET as voltage controlled
device?
In FET’s devices (such as JFET, MOSFET and many more), output which is defined
in terms of Current (Ids) whereas in case of BJT’s devices output defined also in terms
of Current only (Ic).

In case of FET’s devices, input parameter is nothing but the voltage between Gate and Source
terminal ( i.e Vgs)f but in case of BJT it is a current i.e Base Current ( Ib ).

Means output is controlled by voltage (for FET’s ) and current (for BJT).Hence FET’s are
called Voltage Controlled Current Source (VCCS) and BJT is called Current Controlled
Current Source (CCCS).
81. What is the difference between flip flop and latch?

82. What are the differences between positive and negative feedback in amplifiers?

If original input signal and feedback signal are in phase, the feedback type is known
as positive feedback.
It tends to increase the output. If original input signal and feedback signal are out of phase,
the feedback type is known as negative feedback. It tends to reduce the output.
83. What are the advantages of using darlington pair of transistors?
● High current gain: It has already been seen that the current gain from the Darlington is
very high.
● Base emitter voltage: The Darlington pair exhibits a higher voltage between the input
base and the output emitter than a single transistor.
● Frequency response: Darlington pair transistor circuits are not normally used for high
frequency applications.
84. what are the different types of semiconductors (Hint:-direct band gap and indirect
band gap)?
The minimal-energy state in the conduction band and the maximal-energy state in
the valence band are each characterized by a certain crystal momentum (k-vector) in
the Brillouin zone. If the k-vectors are the same, it is called a "direct gap". If they are
different, it is called an "indirect gap". The band gap is called "direct" if the momentum of
electrons and holes is the same in both the conduction band and the valence band; an electron
can directly emit a photon. In an "indirect" gap, a photon cannot be emitted because the
electron must pass through an intermediate state and transfer momentum to the crystal lattice.
Examples of direct bandgap material includes some III-V materials such as InAs, GaAs.
Indirect bandgap materials include Si, Ge.