Introduction to Microprocessors

Mr. P.Sagar Babu

M.Tech (VLSI & ES), (Ph.D)
 INTRODUCTION TO µP

The Microprocessor is the one of the most important component of a digital

computer.
It acts as the Brain of the computer system.
A Digital Computer is a programmable machine which consist of central
processing unit (CPU), Memory, Input and Output device.
The CPU built on a single IC is called Microprocessor.
A digital Computer in which one microprocessor has been provided to act as
a CPU is called Micro computer.
A computer whose CPU contains more than one microprocessor is called
multiprocessor system.
 Microprocessors
General-purpose microprocessor
• CPU for Computers
• No RAM, ROM, I/O on CPU chip itself
• Example：Intel’s x86, Motorola’s 680x0
CPU Data Bus Many chips on mother’s board

General- Serial
I/O
Purpose RAM ROM Timer COM
Port
Micro- Port
processor
Address Bus
General-Purpose Microprocessor System
 Microcontroller

• A smaller computer
• On-chip RAM, ROM, I/O ports...
• Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X

CPU RAM ROM

A single chip
I/O Serial
Timer COM
Port
Port Microcontroller
 Word length of a Microprocessor

The word length of the microprocessor is given as 8,16,32 or 64

bit.
An 8 bit microprocessor can process 8 bit data at a time.
Similarly 16 bit processor, handles 16 bit data at a time and etc.,
A processor of longer word length is more powerful and can
process data at faster speed as compared to processor of shorter
word length.
Evolution of Microprocessor

6
 DATA SIZE
Nibble 4 bit

Byte 8 bit

Word 16 bit

Long word 32 bit

7
 Evolution of Microprocessors
• The first microprocessor
- Intel 4004 (4 bit) -1971.
- Intel 4040 (4 bit) enhanced version of 4004.
- Rockwell International’s PPS - 4
- Toshiba’s T3472
• The Second microprocessor
- Intel introduced first 8 bit processor in 1972.
- Intel 8008 with PMOS technology.
- In 1973, Intel 8080 with faster 8 bit NMOS technology
and compatible with TTL logic (it need 3 power supplies)
- In 1975, Intel 8085 was developed with an improved
version of 8080 which uses only one +5 volt supply.
The 8 bit processors of other manufacturers are
- Zilog’s Z80 and Z800.
- National Semiconductor’s NSC 800.
- Motorola’s MC 6800 and MC 6809.
- MOS Technology’s 6500 series.
- Rockwell International’s PPS-8,
RCA COSMAC (it uses CMOS Technology).
 Generally, the memory addressing capacity of 8 bit microprocessors
are 64 KB. The clock frequency between 1 – 6 MHz. The Z800 can
address more memory i.e. 500 KB and it operates at 25 MHz.
The 8 bit microprocessors use LSI technology and contain 5000 to
10,000 transistors.
In 1978, Intel introduced as 16 bit processor Intel 8086.
The other 16 bit processors are
- Intel 80186, Intel 8088, Intel 80188, Intel 80286.
- Zilog’s Z8000
- Motorola’s 68000, 68010, 68012,
- National Semiconductors PACE and INS 8900.
- Fairchild’s 9440
- Texas Instruments TMS 9900 series and so on.
 Clock Data
Name Date Transi stor s Micron s MIPS
speed w idth
8080 1974 6,000 6 2 MHz 8 bits 0.64
16 bits
8088 1979 29,000 3 5 MHz 8-bit 0.33
bus
80286 1982 134,000 1.5 6 MHz 16 bits 1
80386 1985 275,000 1.5 16 MHz 32 bits 5
80486 1989 1,200, 000 1 25 MHz 32 bits 20
32 bits
Pentium 1993 3,100, 000 0.8 60 MHz 64-bit 100
bus
32 bits
233
Pentium II 1997 7,500, 000 0.35 64-bit ~300
MHz
bus
32 bits
450
Pentium III 1999 9,500, 000 0.25 64-bit ~510
MHz
bus
32 bits
Pentium 4 2000 42,000,000 0.18 1.5 GHz 64-bit ~1,700
bus
32 bits
Pentium 4
2004 125,000,000 0.09 3.6 GHz 64-bit ~7,000
"Prescott"
bus
 8086 Features

•16-bit Arithmetic Logic Unit

•16-bit data bus (8088 has 8-bit data bus)
•20-bit address bus - 220 = 1,048,576 = 1 meg
•The address refers to a byte in memory. In the 8086, bytes at even addresses come in
on the low half of the data bus (bits 0-7) and bytes at odd addresses come in on
the upper half of the data bus (bits 8-15).
•The 8086 can read a 16-bit word at an even address in one operation and at an odd
address in two operations.
•The least significant byte of a word on an 8086 family microprocessor is at the lower
address.
 The Architecture of 8086
•The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit
(EU).

•The BIU fetches instructions, reads and writes data, and computes the 20-bit
address. The EU decodes and executes the instructions using the 16-bit ALU.

•The BIU contains the following registers:

IP - the Instruction Pointer
CS - the Code Segment Register
DS - the Data Segment Register
SS - the Stack Segment Register
ES - the Extra Segment Register
The BIU fetches instructions using the CS and IP, written CS:IP, to contact the
20-bit address.

Data is fetched using a segment register (usually the DS) and an effective
address (EA) computed by the EU depending on the addressing mode.

The EU contains the following 16-bit registers:

AX - the Accumulator BX - the Base Register
CX - the Count Register DX - the Data Register
SP - the Stack Pointer / defaults to stack segment
BP - the Base Pointer
SI - the Source Index Register
DI - the Destination Register
The 8086 architecture is internally divided in to two separate functional
units.
1. Bus Interface Unit (BIU) and 2. Execution Unit (EU)
These two functional unit can work simultaneously to increase system
speed and hence the throughput.
Throughput is a measure of number of instructions executed per unit
time.
• Bus Interface Unit (BIU)
The BIU provides a full 16 bit bi-directional data bus and 20 bit address
bus. It is responsible for performing all external bus operations as follows.
1.It sends address if the memory or I/O.
2. It fetches instruction from memory.
3. It reads data from port/memory.
4. It writes data into port/memory.
5. It supports instruction queuing.
6. It provides the address relocation facility.
To implement the above functions, the BIU contains the instruction
queue, segment registers, instruction pointer, address summer and
bus control logic.
 INSTRUCTION QUEUE:
• To speed up program execution , the BIU fetches 6 instructions
bytes ahead time from the memory. These prefetched instruction
bytes are held for the execution unit in the group of registers called
Queue.
i.e., with the help of queue it is possible to fetch the next instruction
when current instruction is in execution.
• The queue operates on the principle of FIFO. So that the EU gets the
instructions for execution in the order they are fetched.
• In case of JUMP and CALL instructions, instruction already fetched
in queue are of no use.
• Hence in these cases queue is dumped and newly formed by
loading from new address specified by JUMP or CALL
instruction. The feature of fetching the next instruction while the
current instruction is executing is called Pipelining
Execution Unit (EU): The execution unit tells the BIU from where to fetch
instruction or data, decodes instructions and execution instructions. It
contains

1. Control circuitry : The control circuitry in the EU directs internal

operations.

2. Instruction Decoder : A decoder in the EU translates the instructions fetched

from the memory into a series of actions which the EU performs.

3. Arithmetic Logic Unit : ALU is 16 bit. It can add, subtract, AND, OR, XOR,
Increment, Decrement, Complement and Shift binary numbers.
Register Organization : The 8086 has a powerful set of registers. It
includes general purpose registers, segment registers, Pointers and
index registers and flag register.

General Purpose Registers: The general purpose registers are either

used for holding data, variable and intermediate result temporarily.
They can also be used as counters or used for sorting offset address
for some particular addressing modes.
 General Purpose Registers
Gene ral Purpos e In dex
AH AL
BP
AX

SP
BH BL
BX
SI

CH CL
DI
CX

DH DL
DX Se gme nt

CS

Sta tus and Contro l SS

Flag s DS

IP ES
 The General purpose registers (16 – bit):

AX - the Accumulator BX - the Base Register

CX - the Count Register DX - the Data Register
SP - the Stack Pointer / defaults to stack segment
BP - the Base Pointer
SI - the Source Index Register
DI - the Destination Register

These are referred to as general-purpose registers, although, as

seen by their names, they often have a special-purpose use for some
instructions.
 The AX, BX, CX, and DX registers can be considers as two 8-bit
registers, a High byte and a Low byte.

This allows byte operations and compatibility with the previous

generation of 8-bit processors, the 8080 and 8085. 8085 source code
could be translated in 8086 code and assembled.
The 8-bit registers are:
AX ----- AH, AL
BX ----- BH, BL
CX ----- CH, CL
DX ----- DH, DL
 AX AH AL Accumulator

BX BH BL Base Register
CX CH CL Count Register

DX DH DL Data Register

SP Stack Pointer
EU registers BP Base Pointer

SI Source Index Register

DI Destination Index Register

FLAGS
Instructions execute faster if the data is in a register AX, BX, CX,
DX are the data registers
Low and High bytes of the data registers can be accessed separately
- AH, BH, CH, DH are the high bytes
- AL, BL, CL, and DL are the low bytes
Data Registers are general purpose registers but they also perform
special functions
AX
- Accumulator Register
- Preferred register to use in arithmetic, logic and data
transfer instructions because it generates the shortest
- Machine Language Code
- Must be used in multiplication and division
operations and also be used in I/O operations
BX
- Base Register
- Also serves as an address register
- Used in array operations
- Used in Table Lookup operations (XLAT)
CX
- Count register
- Used as a loop counter
- Used in shift and rotate operations
DX
- Data register
- Used in multiplication and division
- Also used in I/O operations
AX, BX, CX and DX are two
bytes wide and each byte can
be accessed separately
These registers are used as
memory pointers.

Flags will be discussed later

Segment registers are used

as base address for a segment
in the 1 M byte of memory
 8086 Programmer’s Model
ES Extra Segment
BIU registers CS Code Segment
(20 bit adder)
SS Stack Segment
DS Data Segment
IP Instruction Pointer

EU registers AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS
29
Segment Registers : The 8086 addresses a segmented memory. The
complete 1 megabyte memory is divided into 16 logical segments.
Each segment contains 64 Kbytes of memory.
1. The 8086 allows only four active segment at a time. These four
registers are Code Segment (CS), Data Segment (DS), Stack Segment
(SS) and Extra Segment (ES) registers.
2. The Physical address of the 8086 is 20 bit wide to access 1 MB
memory location. However, its segment registers and memory
location contains logical addresses are just 16 bit wide.
3. The Physical address is calculated from two parts, the first is segment
address and the second is offset.
4. The segment registers contain 16 bit segment base address related
to different segments. The pointers, Index registers or BX may contain
the offset of the location to be addressed
5. The advantage is that instead of maintaining a 20 bit register for
physical address, the processors just maintains two 16 bit registers
which are with in the word length capacity of the machine.
6. A segment register points to the starting address of a memory
segment currently being used. For ex. The code segment register
points to the starting address of the code segment, the data segment
register points to the starting address of the code segment and so on.
7. The value in CS identifies the starting address of 64 KB memory. The
starting address is also known as base address or segment base.
8. The BIU always inserts zeros for the lower 4 bits in the contents of
segment register to generate 20 bit base address. Ex. If the code segment
register contains 348AH, then code segment will start at address
348A0H.
Starting Address Base Registers
of Segments
20000 2000 CS
CS
40000 4000 DS
DS
60000 6000 SS
SS
80000 8000 ES
ES

Memory Segments
Memory Segmentation and Segment Registers
Address
FFFFFH

Extra Segment 64 K
ES

Stack Segment 64 K
SS 1 Mbyte
Physical
Data Segment 64 K Memory
DS

Code Segment 64 K
CS
00000H
 Functions of Segment Registers :

1. The CS register holds the upper 16 bits of the starting address of the
segment from which the BIU is currently fetching the instruction
byte.
2. The SS register is used for the upper 16 bits of the starting address for
the program stack (all stack related instruction will operate on stack)
3. ES and DS register are used to hold the upper 16 bits of the starting
address of the two memory segments which are used for data.
 Rule for Memory Segmentation :

1. The four segments can overlap for small programs. In a minimum

system all four segments can start at the address 00000H.
2. The segment can begin/start at any memory address which is
divisible by 16.
Advantages of memory segmentation:
1. It allows the memory addressing capacity to be 1 Mbyte even through
the address associated with individual instruction is only 16 bit.
2. It facilitates use of separate memory areas for program, data and
stack.
3. It allows instruction code, data, stack and portion of program to be
more than 64 KB long by using more than one code, data, stack and
extra segment.
4. It permits a program or its data to be put in different areas of
memory, each time the program is executed i.e. program can be
relocated which is very useful in multiprogramming.
Generation of 20 bit address:
1. To access a specific memory location from any segment we need 20 bit
physical address. The 8086 generates this address using the
contents of segment register and the offset register associated with it.
2. The CS register holds the base address of the code segment
3. The 8086 provides an instruction pointer (IP) which holds the 16 bit
address of the of next code byte with in the code segment.
4. The value contained in the IP is referred to as an offset. This value must
be offset from (added to) the segment base address in CS to produce the
required 20 bit physical address.
5. The contents of the CS are multiplied by16, i.e. shifted by 4 position to
the left by inserting 4 zero bits and then the offset i.e. the contents of IP are
added to the shifted contents of CS to generate physical address
For Ex. The contents of CS are 348AH, therefore the shifted contents CS are
388A0H.
When the BIU adds the offset of 4214H in the IP to the starting
address, we get 38AB4H as a 20 bit physical address of memory.
Physical Addresses
Top of code segment
4489FH
Code byte 38AB4H
IP = 4214H
CS = 348AH Start of code
segment 348A0H

CS 3 4 8 A 0
Implied zero
(nibble) 4 zero bits
IP + 4 2 1 4
Physical Address 3 8 A B 4

Note: Similar way the 20 bit physical address is generated in the other segments.
 Pointers and index register
1. All segment registers are 16 bit. But it is necessary to put 20 bit
address (physical address) on the address bus. To get 20 bit physical
address one or more register is associated with each segment register
the way IP is associated with CS

2. These additional registers belong to the pointer and index group. The
pointer and index group consists of instruction pointer (IP), stack
pointer (SP), base pointer (BP), source index (SI) and destination index
(DI) registers.
Stack Pointer (SP): The stack pointer (SP) register contains the 16-bit
offset from the start of the segment to the top of stack. For stack
operation, physical address is produced by adding the contents of stack
pointer register to the segment base address in SS. If the contents of SP
are 9F20H and SS are 4000H then the physical address is calculated as
follows.
SS = 4000H after shifting four bits left SS = 40000H
Now SS 40000H
+ SP 9F20H

Physical address = 49F20H

Base Pointer, Source Index and Destination Index, these three 16 bit registers
can be used as general purpose registers. However, their main use is to hold
the 16 bit offset of the data word in one of the segments.
Base pointer: The BP register can be used instead of SP to access the stack
using the base addressing mode. Then the 20 bit physical stack address is
calculated from BP and SS.
Source Index: The SI can be used to hold the offset of a data word in the data
segment. Then the 20 bit physical data address is calculated from SI and DS.
Destination Index: The ES register points to the extra segments in which
data is stored. String instruction always use ES and DI to determine the 20
bit physical address.
 The 8086/8088 Microprocessors: Registers

Registers
- Registers are in the CPU and are referred to by specific names
- Data registers
i) Hold data for an operation to be performed
ii) There are 4 data registers (AX, BX, CX, DX)
- Address registers
i) Hold the address of an instruction or data element
ii) Segment registers (CS, DS, ES, SS)
iii) Pointer registers (SP, BP, IP)
iv) Index registers (SI, DI)
- Status register
i) Keeps the current status of the processor
ii) On an IBM PC the status register is called the FLAGS register
 FLAG REGISTER

Overflow Carry flag

Direction Parity flag
Interrupt enable Auxiliary flag
Trap Zero
Sign
6 are status flags
3 are control flag
 Conditional flags:
They are set according to some results of arithmetic operation.
You do not need to alter the value yourself.
Control flags:
Used to control some operations of the MPU. These flags are to be
set by you in order to achieve some specific purposes.

Flag x x x x O D I T S Z x A x P x C

Bit no. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CF (carry): This flag is set if there is a carry out of the MSB. (Contains
carry from left most bit following arithmetic, also contains last bit from a
shift or rotate operation). The carry flag also serves as a borrow flag for
subtraction. It is set when borrow is needed.
 PF (parity): Indicates the number of 1 bits that result from an operation.
It is set for even ones; otherwise zero.
AF (auxiliary carry): Contains carry out of bit 3 into bit 4 for specialized
arithmetic. i.e. set to 1, if there is a overflow out of bit 3 i.e., carry from
lower nibble to higher nibble (D3 to D4). This flag is used for BCD
operations.
ZF (zero): The zero flag sets if the result of operation in ALU is zero and
flag resets if the result is nonzero. The zero flag is also set if a certain
register content becomes zero following an increment or decrement
operation of that register.
SF (sign): After the execution of arithmetic or logical operation, if the
MSB of the result is 1, the sign bit is set. i.e., the sign bit 1 indicates the
 TF (trap): Permits operation of the processor in single step mode. i.e.,
to debug a program , run the program one instruction at a time and see the
contents of used register and memory variables after execution of every
instruction. This process is called ‘single stepping’ through a program.
Trap flag is used for single stepping through a program.

IF (interrupt): Indicates whether external interrupts are being

processed or ignored. It used to allow /prohibit the interruption of a
program. If the flag is set, a certain type of interrupt (a maskable interrupt)
can be recognized by the 8086, otherwise these interrupts are ignored.
 DF (direction): Indicates left or right for moving or comparing string
data. (It is used with string instruction. If DF = 0 (reset), the string is
processed from its beginning with the element having the lowest
address. If DF = 1(set) then the string is processed from the high address
towards the low address).
OF (overflow): Indicates overflow of the leftmost bit during
arithmetic. i.e., For addition this flag is set when there is a carry into the
MSB and no carry out of the MSB or vice – versa. For subtraction, it is set
when the MSB needs a borrow and there is no borrow from the MSB or
vice – versa
Example: For addition,
0110 0101 1101 0001
+ 0010 0011 0101 1001
1000 1001 0010 1010
Flag Status: SF = 1, ZF = 0, PF = 1, CF = 0, AF = 0, OF = 1
For subtraction,

0110 0111 0010 1001

- 0011 0101 0100 1010
0011 0001 1101 1111

Flag Status: SF = 0, ZF = 0, PF = 1, CF = 0, AF = 1, OF = 0
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