The Journal of Engineering

The 14th IET International Conference on AC and DC Power

Transmission (ACDC 2018)

Capacitor voltage balancing control with eISSN 2051-3305

Received on 24th August 2018
Accepted on 19th September 2018
reducing the average switching frequency in doi: 10.1049/joe.2018.8643
www.ietdl.org
MMC
Shunliang Wang1, Tianqi Liu1 , XingChuan Huang2, Yuexiao Yu1
1College of Electrical Engineering and Information Technology, Sichuan University, Chengdu, People's Republic of China
2Jiangxispecial equipment inspection institute Jiujiang Branch, Jiujiang, People's Republic of China
E-mail: tqliu@scu.edu.cn

Abstract: Modular multilevel converter (MMC) has a very good application prospect in the flexible high-voltage direct current
(HVDC) transmission, but higher self-loss will affect the efficiency and restrict the development. Here, the MMC in voltage
source converter-based HVDC as the research object, the control and modulation algorithms are designed on the basis of
analysing its working principle. The capacitor voltage imbalance problem is existed in the converter because that the capacitor
of each module is independent. The factors of switching actions in balancing control technology based on the sorting method of
sub-module capacitor voltages are analysed in detail. Then, an optimised balancing control algorithm by setting two balancing
control thresholds is proposed to reduce the average switching frequency. Finally, a two ends HVDC transmission system was
built in MATLAB/SIMULINK to verify the optimisation. The simulation research results show that the optimised balancing control
can ensure sub-module capacitor voltage is in balanced and does not increase the AC output voltage harmonic content, and
obviously reduce the average switching frequency of switching devices, and with the increase of number of level, the more
obvious optimisation effect.

1 Introduction Based on the analysis of the topology and operation principle of

German scholar Rainer Marquardt proposed the conception about
modular multilevel converter (MMC) in 2001, and also he
introduced the basic working principle of MMC [1, 2]. After that,
SIEMENS developed the MMC and applied it to the field of high-
voltage direct current (HVDC). Since MMC has many advantages,
such as high modularisation, easy expansion for voltage and power
level, small harmonic content, and strong fault clearing capability,
it is more suitable for high-voltage and high-power direct current
transmission than traditional two-level or three-level converters.
With the deepening research of MMC, the application of MMC in
the field of HVDC will be more and more extensive. The flexible
HVDC system based on MMC will be the development direction
of the HVDC field [3–5].
Since DC-side voltage of MMC is maintained by the sub-
module capacitive voltages in series, MMC will disperse the
energy into the sub-module capacitor of each phase of the bridge
arms [6]. Therefore, the DC voltage control of MMC not only
needs to control the total DC voltage but also balances the
capacitor voltages of each sub-module, so as to ensure the uniform
distribution of energy in each sub-module capacitor. So far, most of
the control of the capacitor voltage of sub-module is based on the
capacitor voltage sorting method and is implemented in
combination with the modulation algorithm. For example,
reference [7], based on module voltage-sequencing results, selects
corresponding modules to insert or bypass, and balance module
voltage by charging or discharging effect of bridge arm current on
capacitor. This strategy is effective and widely applied in practical
engineering, but all modules need to be sorted in real time,
occupying a large number of controller computing resources,
resulting in the decline of system operation speed. At the same
time, this requires the switch's high-frequency action, which
increases the loss of the power device. The [8] proposed a
modulation method based on a fixed pulse pattern under multiple
fundamental frequency periods where the stored energy in each
sub-module remains stable, converter can work in the control mode
without capacitor voltage feedback. The balance of energy storage
of sub-module capacitor depends on the type of load and converter
operation condition, and its dynamic adjustment speed is also slow.
MMC, a simplified equivalent mathematical model of MMC is
established, and control and modulation algorithms are designed.
Aiming at the problem that the capacitor of each sub-module is
independent of each other and the capacitor voltage is prone to
imbalance, this paper analyses the sub-module capacitor voltage
balancing control technique based on sorting method, and
optimises it, and gives the detailed implementation flow chart.
Finally, the proposed optimisation algorithm is simulated and
verified.
2 Operation principle of MMC
2.1 Topology
The circuit topology of MMC is shown in Fig. 1, the bridge arm of
each phase consists of 2N modules which are connected in series.
urj and irj (j = a, b, c) are AC-side output voltage and current,
respectively. upj and unj represent the total voltage of the upper
bridge arm module and the lower bridge arm module on the j
phase, respectively. ipj and inj represent the upper bridge arm
current and the lower bridge arm current on the j phase,
respectively. Udc and idc indicate the voltage and current in DC-
link, respectively. Node O is zero potential reference point. The
following two conditions should be met when the MMC is running
in normal steady state: (1) DC-link voltage of the converter should
be kept constant, that is, Udc should be kept constant; (2) the output
of converter's AC-side should be three-phase AC voltage, that is,
ura, urb, urc should be three-phase AC voltage.
As shown in Fig. 1, in order to keep Udc constant, the total
output voltage of the sub-module of each phase bridge arm should
be constant and that is Udc. Ignoring the voltage drop on the
inductance of the bridge arm (1) should to be satisfied.
upj + unj = udc ( j = a, b, c) (1)
The number of sub-modules of the upper bridge arm in on-state on
the j phase at any time is npj, and the number of sub-modules of the
lower bridge arm in on-state is nnj. Ignoring the sub-module

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Fig. 1  Topology of MMC
Fig. 2  Diagram of control algorithm
redundancy, each phase bridge of MMC consists of 2N series
modules, namely the upper and lower bridge arm have N sub-
modules, respectively. MMC output voltage level number is (n +  The traditional sub-module capacitor voltage balancing control
1), and the total input module number at any time of each phase
bridge must satisfy (2).
npj + nnj = N (2)
Through reasonable control of the insert or bypass of the sub-
modules in upper and lower bridge arm of each phase according to
the sine regulation, the amplitude of AC-side output voltage
changing in − Udc/2–Udc/2 can be achieved.
2.2 Control and modulation algorithms
The control algorithm based on outer loop voltage control and
inner loop current control is widely used in VSC control because of
its simple control structure, fast response speed, decoupling of
active power and reactive power. Here, the external loop DC
voltage PI control + internal loop direct current control technique is
used to control the MMC.
The schematic diagram of control algorithm is shown in Fig. 2.
The outer loop controller first generates the suitable AC current
reference value according to the power or the DC voltage
instruction value issued by the system-level control layer, and
transfers it to the inner loop controller. The inner loop controller
receives this command signal. By adjusting the amplitude and
phase of the AC side of converter output voltage, the alternating
current can track its reference value rapidly. Through appropriate
modulation algorithm, a modulated signal is generated and sent to
the valve-side of the control layer to achieve control of the VSC
switching device.
2 J. Eng.
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The modulation algorithm enables the AC-side output voltage
of the MMC to track modulated reference signal by controlling the
sub-module in on- or off-state for the bridge arm of each phase.
Nearest level modulation (NLM) has been widely used in MMC
because of its small switching loss and easy realisation. The basic
idea is that when the MMC level is high enough, the step wave can
directly approach the modulation wave through the superposition
of the instantaneous level, and no longer need the pulse width
control.
3 Sub-module capacitor voltage balancing
control
3.1 Traditional balancing control
determine the insert or bypass of the sub-modules through the
combination of controller and the modulation algorithm,
calculating the number of sub-modules of each bridge arm needed
to insert at the current time, and together with the sorting result of
the capacitor voltage of each sub-module.
The flow chart of the traditional sub-module voltage balancing
control is shown in Fig. 3, and the detailed implementation
methods are as follows:
(i) Controller gets the number of sub-modules in on-state at the
current moment of the bridge arm is Non by the algorithm
calculating;
(ii) Monitoring the capacitor voltage of all the sub-modules of each
arm, and sending the feedback value to the controller for ascending
order.
(iii) Monitor the current flow of the bridge arm and determine its
effect on the capacitor voltage of each sub-module.
(iv) Before the current control signal is sent, if the effect of the
bridge arm current on the sub-module capacitor is charging, Non
sub-modules at the back of the sub-module capacitor voltage
sorting will be in on-state, and other sub-modules will be in off-
state. Conversely, if the effect of the bridge arm current on the sub-
module capacitor is discharging, Non sub-modules of the bridge
arm in the front of the sub-module capacitor voltage sorting will be
in on-state, and other sub-modules will be in off-state.
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Fig. 3  Flow chart of traditional sub-modules capacitor voltage balancing
control
3.2 Optimised balancing control
Although the traditional sub-module capacitor voltage balancing
control can achieve the balanced control of sub-module capacitor
voltage well; however, before each control signal is generated, the
authors need to sort the feedback values of sub-module capacitor
voltage, so as to determine the insert or bypass of each sub-module.
Therefore, a small change of the sub-module capacitor will have an
impact on the sequencing results, which leads to the control signal
of each sub-module to adjust. This is bound to create a frequent
switching of sub-module in the on- or off-state, making the average
switching frequency very high, resulting in high switching losses.
The traditional sub-module capacitor voltage balancing control is
devoted to controlling the difference among the capacitor voltages
of modules in a minimum value. In fact, the balancing control of
the capacitor voltage is not the pursuit of the full consistency of the
capacitor voltage of each module, but the control of its fluctuation
range.
Accordingly, in order to reduce the average switching frequency
of switching devices, the voltage balancing control of sub-module
capacitors is optimised, and an optimised balancing control which
can reduce the average switching frequency is proposed. The basic
idea is to select two thresholds near the sub-module capacitor
voltage rating and to ensure that the sub-module keeps the original
switching state as much as possible under the premise of ensuring
the voltage balance of the sub-module, so as to achieve the goal of
reducing the average switching frequency. The specific way of
realisation is that if the capacitor voltage of the sub-module in the
on-state at the last time is within the selected threshold, it will
continue to hold on-state in the selected threshold. Otherwise, it
will be sorted with the remaining sub-modules, so as to decide the
switching state.
For a better interpretation of the balancing control of the
capacitor voltage of the sub-module, uc_up, and uc_down are set to
represent the upper threshold and the lower threshold, respectively.
Non_last indicates the number of sub-modules in on-state at the last
cycle. Non_chose indicates the number of sub-modules in on-state at
the last cycle whose capacitor voltage value is in the threshold
range. Non_now represents the number of sub-modules should be in
on-state at the current cycle, and i represents bridge arm current of
the bridge arm.
(i) i ≥ 0, Non_now ≥ Non_last. The effect of the bridge arm current on
the capacitor of the sub-module is to charge, and the number of
sub-modules in on-state at present cycle should be bigger than that
of sub-modules in on-state at last cycle. First, compare the value of
sub-module capacitor voltage at the last cycle with uc_up. If the
sub-module capacitor voltage in on-state at the last cycle is less
than uc_up, this sub-module will continue to be put into on-state at
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present. Otherwise, this sub-module will be sorted with the residual
module to determine its state. Second, obtain Non_chose. Finally,
sort the remaining sub-module, and insert Non_now − Non_chose sub-
module capacitors with lower voltage value in on-state.
(ii) i ≥ 0, Non_now <  Non_last. The effect of the bridge arm current on
the capacitor of the sub-module is to charge, and the number of
sub-modules in on-state at present cycle should be smaller than that
of sub-modules in on-state at the last cycle. First, compare the
value of sub-module capacitor voltage with uc_up at the last cycle.
Second, obtain Non_chose. Finally, compare the value of Non_now
and Non_chose. If Non_chose ≥ Non_now, Non_now sub-modules with
lower capacitor voltage value are selected by sorting method
among the sub-modules in on-state at the last cycle, and the
remaining sub-modules are resected. On the contrary, insert
Non_chose sub-modules whose capacitor voltage is lower than uc_up
and in on-state at the last cycle. Sort the remaining sub-modules
and input Non_now − Non_chose sub-modules with lower capacitor
voltage value.
(iii) i < 0, Non_now ≥ Non_last. The effect of bridge arm current on
sub-module capacitor is discharge, and the number of sub-modules
in on-state at present cycle should be bigger than that of sub-
modules in on-state at last cycle. First, compare the value of sub-
module capacitor voltage at the last time with uc_down. If the sub-
module capacitor voltage at the last time is greater than uc_down,
more sub-modules will be continually invested at this time. On the
other hand, this sub-module will be sorted with residual modules to
determine its state. Second, gain Non_chose. Finally, sort the
remaining sub-modules, and insert Non_now − Non_chose sub-
modules with higher capacitor voltage.
(iv) i < 0, Non_now < Non_last. The effect of bridge arm current on
sub-module capacitor is discharge, and the number of sub-modules
in on-state at present cycle should be smaller than that at the last
cycle. First, compare the value of sub-module capacitor voltage at
the last cycle with uc_down. Second, gain Non_chose. Finally,
compare the value of Non_now and Non_chose. Non_now sub-modules
with higher capacitor voltage are selected by sorting method
among the sub-modules in on-state at the last cycle, and the
remaining sub-modules are resected. On the contrary, insert
Non_chose sub-modules whose capacitor voltage is higher than
uc_down and in on-state at the last cycle. Sort the remaining sub-
modules and insert Non_now − Non_chose sub-modules with higher
capacitor voltage.
The flow chart of the whole module capacitor voltage optimised
balancing control algorithm is shown in Fig. 4.
4 Simulation results
In order to verify the effectiveness of the optimised sub-module
capacitor voltage balancing control, simulation models of two-
terminal active MMC-HVDC system based on 5-level and 21-level
MMC are built in the MATLAB/SIMULINK simulation platform,
respectively, and the sub-module capacitor voltage balancing
control is verified. In the steady-state operation, MMC1 adopt DC-
voltage control and reactive-power control. DC voltage command
for 15 kV and reactive power command is 0 Mvar. MMC2 is set in
active-power and reactive-power control. The instruction for active
power is 1.5 MW, and instruction for reactive power is 0 Mvar. The
other main parameters in this system are shown in Table 1.
4.1 5 Level
The simulation results of 5-level MMC are given in Figs. 5–7.
Fig. 5 is the capacitor voltage of sub-module of the upper bridge
arm of phase a. Fig. 6 is the trigger pulse of IGBT that locate lower
side at the first sub-module (SM1) of upper bridge arm, and Fig. 7
is spectrum analysis diagram of the AC-side output voltage.
From Fig. 5, the authors can see that the 5-level MMC can keep
voltage fluctuating near the rated voltage 1250 V under both the
traditional control and optimised sub-module capacitor voltage
balancing control. The authors can see from Fig. 6, the optimised
3
Fig. 4  Flow chart of optimised sub-modules capacitor voltage balancing control
Table 1 Main parameters
Transformer ratio Leakage inductance
10 kV/2.5 kV 1 mH
Fig. 5  Capacitor voltages of phase a upper arm sub-modules in 5 level
MMC
(a) Traditional balancing control, (b) Optimised balancing control
balancing control has a certain optimisation effect on the trigger
signal of the sub-module IGBT. In the same period of time, the
time of IGBT turn-on and turn-off commutation action decreased
in comparison with the traditional balancing control, namely IGBT
average switching frequency, reduces but the effect is not obvious.
4 J. Eng.
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Arm inductance Sub-module capacitance
4 mH 6 mF
This is due to the small number of each phase arm modules of 5-
level MMC, so the effect of optimising the balancing control is not
easy to be reflected. As shown in Fig. 7, under the traditional
balancing control, the output voltage THD of the MMC's AC side
is 6.57%, and the data are 6.46% under the optimised balancing
control. It can be seen that these two different balancing controls
have little influence on the harmonic content of the MMC AC-side
output voltage.
4.2 21 Level
The simulation results of 21-level MMC are given in Figs. 8–10.
Fig. 8 is the sub-module capacitor voltage of the upper bridge arm
on phase a. Fig. 9 is the trigger pulse of IGBT that locate lower
side at the first sub-module (SM1) of upper bridge arm. Fig. 10 is
the spectrum analysis diagram of the AC-side output voltage.
From Fig. 8, the authors can see that the 21-level MMC can
keep voltage fluctuating near the rated voltage 250 V under both
the traditional control and optimised sub-module capacitor voltage
balancing control. Under the traditional balancing control, the
range of the sub-module capacitor voltage's fluctuation is (232,
260 V). Under the optimised balancing control, the range of the
voltage's fluctuation is (218, 270 V). Therefore, the authors can see
that the fluctuation of the voltage under optimised balancing
control is greater. This is due to the reduction of the times of IGBT
commutation between turning on and turning off under the
optimised balancing control that makes some sub-modules
continue to charge or discharge, thus increasing the voltage range
of the sub-module capacitor. From Fig. 9, the authors can see that
the optimised balancing control has obvious optimisation effect on
the trigger signal of IGBT. In the same period of time, the times of
IGBT commutation between turning on and turning off are
significantly decreased compared with the condition under
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 Fig. 8  Capacitor voltages of phase a up arm sub-modules in 21 level
Fig. 6  Trigger pulses of SM1's below switch in phase a upper arm for 5 MMC
level MMC (a) Traditional balancing control, (b) Optimised balancing control
(a) Traditional balancing control, (b) Optimised balancing control

Fig. 9  Trigger pulses of SM1's below switch in phase a up arm for 21 level
MMC
(a) Traditional balancing control, (b) Optimised balancing control
Fig. 7  THD value of AC output voltage in 5 level MMC
(a) Traditional balancing control, (b) Optimised balancing control frequency of electronic switching device IGBT can be significantly
reduced which gets more effective with the increase in the number
traditional balancing control. From Fig. 10, the authors know that of its level.
under the traditional balancing control, the output voltage THD of
the 21-level AC-side MMC is 1.81%, and the output voltage THD
6 Acknowledgments
is 1.54% when the optimised balancing control is applied. It can be
seen that under this two different balancing controls, the difference This work was supported by the National Key Research and
of harmonic content of AC-side MMC output voltage is small. Development Plan (Grant Nos. 2016YFB0900901). In addition, the
authors would like to thank National Natural Science Foundation
5 Conclusion of China (NSFC, No. 51707126) and China Scholarship Council
(CSC) for their funding.
Here, the MMC is taken as the research object, the balancing
control of the sub-module capacitor voltage is further studied, and
the sub-module capacitor voltage balancing control technique
based on sorting method is analysed in detail, and its optimisation
is carried out. The simulation results show that the sub-module
capacitor voltage balancing control can ensure the optimisation of
the sub-module capacitor voltage balance without increasing the
AC-side output voltage harmonics, and average switching

J. Eng. 5
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Fig. 10  THD value of ac output voltage in 21 level MMC

(a) Traditional balancing control, (b) Optimised balancing control

7 References
[1] Lesnicar, A., Marquardt, R.: ‘A new modular voltage source inverter
topology’. European Conf. on Power Electronics and Applications, Toulouse,
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