Lecture #5: Computer Architecture: From Nand To Tetris

Lecture #5:
Computer
Architecture
From Nand to Tetris
www.nand2tetris.org
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 2: Boolean Arithmetic slide 1
Babbage’s Analytical
Engine (1835)
“We may say most aptly that the Analytical Engine weaves
algebraic patterns just as the Jacquard-loom weaves
flowers and leaves”
(Ada Lovelace)
Charles Babbage (1791-1871)
Some early computers and
computer scientists
Blaise Pascal Gottfried Leibniz

1623-1662 1646-1716
“Stepped Reckoner” = Multiple and Divide!(gear
“Pascaline” = Mechanical Adding Machine driven). First to advocate binary num. system
(gear driven)
Mauchly & Eckert
• ENIAC (Electronic Numerical Integrator and Calculator
– 1946 = Developed for the military (firing tables WWII)
– Not “published” until
well after the war
• 17,468 vacuum tubes
• 70,000 resistors
• 10,000 capacitors
• 1,500 relays
• 6,000 manual switches
• 1,800 sq. feet of floor space, weighed 30 tons!
• UNIVAC (UNIVersal Automatic Computer)
– 1951 = Developed for the census bureau (baby boomers)
– 1952 = successfully predicted the outcome of the
Eisenhower-Stevenson election
– Used magnetic tape, much faster than IBMs punch cards
Von Neumann machine (circa 1940)
CPU
Input
device
Memory Arithmetic Logic
Unit (ALU)
(data
+ Registers
instructions)
Output
Control device
Stored
program
concept!
Keyboard
Andy Grove (and others) ...
John Von Neumann (and others) ... made it possible made it small and fast.
Processing logic:
fetch-execute cycle
CPU
Input
device
Memory Arithmetic Logic
Unit (ALU)
(data
+ Registers
instructions)
Output
Control device
Executing the current instruction involves one or more of

the following micro-tasks:
q Have the ALU compute some function out = f (register values)
q Write the ALU output to selected registers
q As a side-effect of this computation,
figure out which instruction to fetch and execute next.
Keyboard
The Hack chip-set and
hardware platform
Elementary logic gates Combinational chips Sequential chips Computer Architecture
§ Nand § HalfAdder § DFF § Memory

§ Not done § FullAdder § Bit § CPU
§ And § Add16 § Register § Computer
§ Or § Inc16 § RAM8
§ Xor § ALU § RAM64 this lecture
§ Mux § RAM512
§ Dmux done § RAM4K
§ Not16 § RAM16K
§ And16 § PC
§ Or16
§ Mux16 done
§ Or8Way
§ Mux4Way16
§ Mux8Way16
§ DMux4Way
§ DMux8Way
The Hack computer
§ A 16-bit Harvard architecture
§ The instruction memory and the data memory are physically separate
§ Screen: 512 columns by 256 rows, black and white
§ Keyboard: standard
§ Designed to execute programs written in the Hack machine language
§ Can be easily built from the chip-set that we built so far in the course
Main parts of the Hack computer:

q Instruction memory (ROM)
q Memory (RAM):
• Data memory
• Screen (memory map)
• Keyboard (memory map)
q CPU
q Computer (the logic that holds everything together).
Lecture / construction plan
• Instruction memory
• Memory:
q Data memory
q Screen
q Keyboard
• CPU
• Computer
Instruction memory
address out
ROM32K
15 16
Use built-in
ROM32K
chip for
Function: HW
• The ROM is pre-loaded with a program written in the
Hack machine language (manually by us in simulator)
• The ROM chip always emits a 16-bit number:
out = ROM32K[address]
• This number is interpreted as the current instruction.
Data memory
load
Low-level (hardware) read/write logic:

• To read RAM[k]: set address to k,
set load to 0, in out
probe out RAM16K
16 16
• To write RAM[k]=x: set address to k,
set in to x, address
set load to 1, 15
14
run the clock

High-level (OS) read/write logic:
• To read RAM[k]: use the OS command out = peek(k)
• To write RAM[k]=x: use the OS command poke(k,x)
• peek and poke are OS commands whose implementation
should effect the same behavior as the low-level commands
• More about peek and poke this later in the course, when we
write the OS.
P n Instruction memory
n Memory:
P q Data memory
q Screen
q Keyboard
n CPU
n Computer
Screen
The Screen chip has a basic RAM chip functionality:
q read logic: out = Screen[address]
Simulated screen:
q write logic: if load then Screen[address] = in
Side effect:
Continuously refreshes a 256 by 512 black-and-white screen device:
16,384 (SCREEN) to 24,575

The simulated
= 8,192 registers at 16 bits each 256 by 512
B&W screen
= 131,072 bits, each represents a pixel (= 512 * 256)
When loaded into the
load The bit contents of the hardware simulator, the
Screen chip is called the built-in Screen.hdl chip
in “screen memory map” opens up a screen window;
the simulator then
out refreshes this window
16 from the screen memory
Screen
16
map several times each
address second.
15
Physical
Screen
Screen memory map
0 0011000000000000
0 1 2 3 4 5 6 7 ... 511
1 0000000000000000
In the Hack platform, 0 ...
. row 0 1 ...
the screen is .
.
implemented as an 8K 31 0000000000000000
. .
32 0001110000000000
16-bit RAM chip. 33 0000000000000000 . .
. .
. row 1
.
.
63 0000000000000000
255 ...
Screen
8160
8129 0100100000000000
8161
8130 0000000000000000
. row
. 255
. refresh several times
8191 each second
8160 0000000000000000
How to set the (row,col) pixel of the screen to black or to white:

q Low-level (machine language): Set the col%16 bit of the word found at
Screen[row*32+col/16] to 1 or to 0
(col/16 is integer division)
q High-level: Use the OS command drawPixel(row,col)
q (effects the same operation, discussed later in the course, when we’ll write the OS).
Keyboard
out Simulated keyboard:
Keyboard
16
Keyboard
Keyboard chip: a single 16-bit register

Input: scan-code (16-bit ASCII value) of the currently
pressed key, or 0 if no key is pressed [hardware] The simulated
keyboard
Output: same enabler button
The keyboard is implemented as

Special keys: a built-in Keyboard.hdl chip.
When this java chip is loaded
into the simulator, it connects
Keyboard
to the regular keyboard and
pipes the scan-code of the
currently pressed key to the
keyboard memory map.
How to read the keyboard:

q Low-level (hardware): probe the contents of the Keyboard chip
q High-level: use the OS command keyPressed()
q (effects the same operation, discussed later in the course, when we’ll write the OS).
n Memory:
P q Data memory
P q Screen
P q Keyboard
n CPU
n Computer
Memory: conceptual / programmer’s view
Memory
Data
Use built-in
Screen +
Screen
Keyboard
memory chips for HW
map
Screen
Keyboard map
Keyboard
Using the memory:
q To record or recall values (e.g. variables, objects, arrays), use the first 16K words
of the memory
q To write to the screen (or read the screen), use the next 8K words of the
memory
q To read which key is currently pressed, use the next word of the memory.
Memory (Implementation)
• The Memory chip is essentially a package
load
Memory that integrates the three chip-parts
RAM16K, Screen, and Keyboard into a single,
0 contiguous address space.
in
• This packaging effects the programmer’s
16
RAM16K
out
view of the memory, as well as the
(16K mem. chip)
necessary I/O side-effects.
16383 16
address 16384 Screen

(8K mem. chip)
15
24575 Screen
Keyboard
24576 (one register)
Keyboard
Access logic:
q Access to any address from 0 to 16,383 (inclusive) results in accessing the
RAM16K chip-part
q Access to any address from 16,384 to 24,575 (inclusive) results in
accessing the Screen chip-part
q Access to address 24,576 results in accessing the Keyboard chip-part
q Access to any other address is invalid.
Memory Lab
Partner up!
P n Memory:
P q Data memory
P q Screen
Keyboard
P q
n CPU
n Computer
A pledge to patience ...
“At times … the fragments that I lay out for your inspection may seem not
to fit well together, as if they were stray pieces from separate puzzles. In
such cases, I would counsel patience. There are moments when a large
enough fragment can become a low wall, a second fragment another wall
to be raised at a right angle to the first. A few struts and beams later, and
we may made ourselves a rough foundation … But it can consume the
better part of a chapter to build such a foundation; and as we do so the
fragment that we are examining may seem unconnected to the larger
whole. Only when we step back can we see that we have been assembling
something that can stand in the wind.”
From: Sailing the Wind Dark Sea (Thomas Cahill)
The A-instruction revisited
Symbolic: @value // Where value is either a non-negative decimal number

// or a symbol referring to such number.
value (v = 0 or 1)
Binary: 0 v v v v v v v v v v v v v v v
Note: non-negative number

expressed in binary
(if it’s a symbol, you would use the
number symbol represents)
The C-instruction revisited
dest = comp; jump comp dest jump
binary: 1 1 1 a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3
CPU Lab
Partner up!
CPU from
data memory inM
16 outM
16
to data
writeM
CPU
from memory
instruction instruction 1
memory 16 addressM
15
pc to instruction
a Hack machine language reset 15
memory
instruction like M=D+M, 1
stated as a 16-bit value
CPU internal components (invisible in this chip diagram): ALU and 3 registers: A, D, PC
CPU fetch logic:
Recall that:
1. the instruction may include a jump directive (expressed as non-zero jump bits)
2. the ALU emits two control bits, indicating if the ALU output is zero or less than zero
If reset==0: the CPU uses this information (the jump bits and the ALU control bits) as:
If there should be a jump, the PC is set to the value of A; else, PC is set to PC+1
If reset==1: the PC is set to 0. (restarting the computer)
CPU from
data memory inM
16 outM
16
to data
writeM
CPU
from memory
memory 16 addressM
15
pc to instruction
memory
CPU decode logic:
Recall that: the instruction is either an A- or C-instruction (how can we tell them apart?)
If A-instruction:
• Set A register to value
If C-Instruction:
• Break down into dest, comp, jump parts (how do you know what needs to be done?)
CPU
from
data memory inM
16 outM
16
to data
writeM
CPU
from memory
memory 16 addressM
15
pc to instruction
memory
CPU execute logic:

The CPU executes the instruction according to Hack language specification:
q The D and A values, if they appear in the instruction, are read from
(or written to) the respective CPU-resident registers
q The M value, if there is one in the instruction’s RHS, is read from inM
q If the instruction’s LHS includes M, then the ALU output is placed in outM,
the value of the CPU-resident A register is placed in addressM, and
writeM is asserted (set to 1).
CPU dest = comp; jump
binary: 1 1 1
comp dest jump
implementation a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3
Chip diagram:
ALU output
q Includes most of the CPU’s
execution logic
q The CPU’s control logic is C
C C
hinted: each circled “c”

represents one or more D
D
control bits, taken from the decode

C C
instruction outM
ALU
C
q The “decode” A
Mux
A
bar does not instruction A/M
C
represent a
Mux
chip, but M
inM
rather indicates C writeM
that the A
instruction bits addressM
are decoded reset C
somehow.
Cycle: A
PC pc
q Decode
q Execute Decode logic: Execute logic: Resetting the
Fetch logic:
q Execute based If there’s a jump, computer:
q Fetch q Breakdown on decoded A- set PC to A
instruction or C- Set reset to 1,
instruction else set PC to PC+1
into parts then set PC to 0.
P n Memory:
q Data memory
q Screen
q Keyboard
P n CPU
n Computer
Computer-on-a-chip interface
reset Screen
Computer
Keyboard
Keyboard
Computer-on-a-chip implementation
inM
writeM
Instruction outM Data
Memory instruction Memory
CPU
addressM
(ROM32K) (Memory)
pc
reset
CHIP Computer {
IN reset;
PARTS: Implementation:
// implementation missing
Simple, the chip-parts do all the hard work.
}
The spirit of things
We ascribe beauty to that which is

simple; which has no superfluous parts;
which exactly answers its end;
which stands related to all things;
which is the mean of many extremes.
(Ralph Waldo Emerson,
1803-1882)
“Ya, right,
Lecture plan but what about
the software?”
P n Memory:
q Data memory
q Screen
q Keyboard
P n CPU
Computer
P n
Perspective: from here to a
“real” computer
• Caching
• More I/O units
• Special-purpose processors (I/O, graphics, communications, …)
• Multi-core / parallelism
• Efficiency
• Energy consumption considerations
• And more ...
Perspective: some issues we
haven’t discussed (among many)
• CISC / RISC (hardware / software trade-off)
– Complex/Reduced Instruction Set Computing
• Hardware diversity: desktop, laptop, hand-held, game machines, …
• General-purpose vs. embedded computers
• Silicon compilers
• And more ...

Lecture #5: Computer Architecture: From Nand To Tetris

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Lecture #5:

Charles Babbage (1791-1871)

Blaise Pascal Gottfried Leibniz

Executing the current instruction involves one or more of

§ Nand § HalfAdder § DFF § Memory

Main parts of the Hack computer:

• This number is interpreted as the current instruction.

Low-level (hardware) read/write logic:

run the clock

Continuously refreshes a 256 by 512 black-and-white screen device:

16,384 (SCREEN) to 24,575

How to set the (row,col) pixel of the screen to black or to white:

Keyboard chip: a single 16-bit register

The keyboard is implemented as

How to read the keyboard:

address 16384 Screen

From: Sailing the Wind Dark Sea (Thomas Cahill)

Symbolic: @value // Where value is either a non-negative decimal number

Note: non-negative number

CPU execute logic:

hinted: each circled “c”

control bits, taken from the decode

We ascribe beauty to that which is

• More I/O units

• Special-purpose processors (I/O, graphics, communications, …)

• Energy consumption considerations

• And more ...

– Complex/Reduced Instruction Set Computing

• Hardware diversity: desktop, laptop, hand-held, game machines, …

• General-purpose vs. embedded computers

• And more ...

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