Electronic Circuits & Logic Design Lab Manual

Electronic Circuits & Logic Design
Department of
Information Science and
Engineering
3rd Semester
Electronic Circuits & Logic

Design Laboratory
(10CSL38)
Lab Manual
Vaidehi M & Rashmi N
DEPT. INFORMATION SCIENCE and ENGINEERING Page 1

Electronic Circuits & Logic Design Laboratory

(Common to CSE & ISE)
Subject Code: 10CSL38 IA Marks: 25
Hrs/Week: 03 Exam Hours: 03
Total Hours: 42 Exam Marks: 50
Part A
1. a. Design and construct a suitable circuit and demonstrate the working of positive clipper,
double ended clipper and positive clamper using diodes.
b. Demonstrate the working of the above circuits using a simulation package
2. a. Design and construct a suitable circuit and determine the frequency response, input
Impedance, output impedance and bandwidth of a CE amplifier.
b. Design and build the CE amplifier circuit using a simulation package and determine
the voltage gain for two different values of supply voltage and for two different values
of emitter resistance.
3. a. Design and construct a suitable circuit and determine the drain characteristics and
transconductance characteristics of an enhancement mode MOSFET.
b. Design and build CMOS inverter using a simulation package and verify its truth table.
4. a. Design and construct a Schmitt trigger circuit using op-amp for the given UTP
and LTP values and demonstrate its working.
b. Design and implement a Schmitt trigger using Op-Amp using a simulation package for
two sets of UTP and LTP values and demonstrate its working.
5. a. Design and construct a rectangular waveform generator (op-amp relaxation
Oscillator) for a given frequency and demonstrate its working..
b. Design and implement a rectangular waveform generator (Op-Amp relaxation
Oscillator) using simulation package and demonstrate the changes in frequency when
all resistor values are doubled.
6. Design and implement an Astable Multivibrator using 555 Timer for a given frequency
and duty cycle.
Part B
7. a. Given a four variable expression, simplify using Entered Variable Map (EVM) and
realize the simplified logic using 8:1 MUX.
b. Design and develop the verilog/VHDL code for 8:1 MUX. Simulate and verify its
working.
8. a. Realize a J-K Master/Slave FF using NAND gates and verify its truth table.
b. Design and develop the verilog/VHDL code for DFF with positive edge triggering.
Simulate and verify it’s working.
9. a. Design and implement a mod n (a<8)synchronous up counter using JK FF IC’s and
demonstrate its working.
b. Design and develop the verilog/VHDL code for mod 8 up counter simulate and verify
it’s working.
10 a. Design and implement ring counter using 4-bit shift register and demonstrate its
working.
b. Design and develop the verilog /VHDL code for switched tail counter. Simulate and
verify it’s working.
11 Design and implement asynchronous counter using decade counter IC to count up from
0 to n (n≤9) and demonstrate its working.
12 Design a 4-bit R-2R ladder D/A converter using Op-Amp. Determine its accuracy and
resolution.

Electronic Circuits Laboratory

1. CLIPPING AND CLAMPING CIRCUITS
Aim: To Design and construct a suitable circuit and demonstrate the working of
positive clipper, double ended clipper and positive clamper using diodes.
Apparatus required: Diode (BY-127 / IN4007), Resistors-10 K & 3.3k, DC regulated

power supply (for Vref), Signal generator (for Vi) and CRO.
Positive Clipping Circuit
Fig.1 a Positive clipper Circuit b. Transfer Characteristics

Theory: Circuits that transfers a selected portion of input waveform to the output are called
clipping circuits. These circuits are also known as voltage or current limiters/slicers or
amplitude selectors. Clippers are used in digital and other electronic systems. Diode clippers
can remove signal voltages above or below specified level. A clipping circuit consists of
linear elements line resistors and non linear elements link junction diodes or transistors.
There are two types of clippers namely series and parallel. The series configuration is defined
as one where a diode is in series with load while the parallel clipper has the diode in parallel
to load.
Design:
Let the output voltage to be clipped to say +2V
Therefore Vo (max) = Vref = 2V
The value of resistor R is chosen to be
R = √Rf x Rr = √10 x 10 x 106 = 10KΩ
When Vi < VR , diode ‘D’ is OFF and V0 =VR

When Vi > VR , diode ‘D’ is ON and V0 = Vi
Procedure:
1. Connect the circuit as shown in fig.

2. Switch on the VRPS and adjust the supply voltage VRef = 2V
3. Apply a sine wave input(Vi) at frequency say 1KHZ from the signal generator and
adjust the peak amplitude to say 6V(P-P)(peak amplitude should be greater than
clipping level).
4. Observe the input waveform, output waveform and clipping level on CRO.
5. Apply Vi and V0 to the X and Y channels of CRO respectively and obtain the
transfer characteristics using X-Y mode in CRO.
WAVEFORMS
Fig. 2. Input and output waveform for Positive Clipper
DOUBLE ENDED CLIPPER
Fig.3 Double ended clipper Circuit b. Transfer Characteristics

Design :
To generate a symmetrical square wave of amplitude ±4V(i.e. output to be

clipped below 4V and above 4V)
Since Vo(max) = 4V
We have Vo(max) = VRef 1 + Vr
Where Vr is diode drop ≈ 0.6V
Therefore VRef 1 = Vo(max) - Vr
VRef 1 = 4 – 0.6 = 3.4V
Also Vo(min) = -4V
We have Vo(min) = VRef2 - Vr
Therefore VRef2 = Vo(min) + Vr
VRef2 = -4 + 0.6 = -3.4V
The value of resistor R is chosen to be
R = √Rf x Rr = √10 x 10 x 106 =

10KΩ
When VR1 > Vi >-VR2 , diode ‘D1’ is ON and diode ‘D2’ is OFF and V0 = VR1
When VR1 > Vi < -VR2 , diode ‘D1’ is OFF and diode ‘D2’ is ON and V0 = VR2
When VR1 < Vi < VR2 , diode ‘D1’ is OFF and diode ‘D2’ is OFF and V0 = Vi
Procedure :
2. Switch on the VRPS and adjust the supply voltage VRef 1 = 3.4V and
VRef 2 = -3.4V

3. Apply a sine wave input (Vi) at frequency say 1KHZ from the signal generator
and adjust the peak amplitude to say 12V(P-P)(peak amplitude should be
greater than clipping level).
5. Apply Vi and V0 to the X and Y channels of CRO respectively and obtain the
transfer characteristics using X-Y mode in CRO.
Fig. 4. Input and output waveform for double-ended clipping circuit
POSITIVE CLAMPER
Apparatus required: Diode (BY-127), Resistor of 10K, Capacitor -1 F, DC regulated

power supply, Signal generator, CRO
Fig. 5 Positive Clamper
In certain applications, a periodic waveform has to be shifted above or below a certain

voltage level called reference voltage. These circuits are referred as clamping circuit. The
clamper adds the dc component and pushes the signal upwards so that the negative peak falls
on the zero level. The shape of the signal will not change, only there will be shift in the
signal. Such a clamper is called as positive clamper.

DESIGN:
Vo(max) = VRef + Vr
VRef = Vo(max) - Vr = 3 – 0.6 = 2.4V
Given frequency = 1KHZ, therefore T = 1msec
Choose R > T
Let RC = 10T
RC = 10 x 1msec = 10msec
Let R = √Rf x Rr = 10KΩ
C =10msec/10KΩ = 1F
Procedure:

2. Switch on the VRPS and adjust the supply voltage VRef = 2.4V
3. Apply a sine wave input (Vi) at frequency say 1KHZ from the signal generator and
adjust the peak amplitude to say 8V(P-P)(peak amplitude should be greater than
clamping level).
5. Make VRef = 0V and observe the positive peaks being clamped to almost 0V.

Fig. 6 Input and output waveform for positive clamper without reference voltage.
Fig. 7 Input and output waveform for positive clamper circuit with reference voltage = 2V
Result: Positive Clamping Circuits have been tested and output waveforms
match with the expected waveforms.

Electronics Circuits with Multisim

1. b. Demonstrate the working of the above circuits using a simulation package
Instructions
To design:
1. Place parts, connect wire.

2. Assign the proper values as per the design to each component placed in circuit.
3. Simulate the design and verify the output for different values of parameter.
To Design the circuit diagram:
Select Place Component :( Ctrl w)
Sources: Power Sources:

AC Power, set the values (Voltage (RMS) =6V, voltage Offset = 0
Frequency (F) =1K)
DC Power = 2V
Diodes: IN4001
Basic: Resistors:10k
Sources: Power Sources: Ground

To simulate
1. Select Grapher/Analysis List(simulate-Analyses)

Select Transient Analysis
First select Reset to Default
Parameters:
Start Time(TSTART) = 0sec
End Time (TSTOP) = 0.005sec
Output: AddV(1) and V(2)
Simulate

Select: Place Component:( Ctrl w)

AC Power, set the values (Voltage(RMS) =6V, voltage Offset = 0 Frequency
(F) =1K)
DC Power = 3.4V(Vref1 & Vref2)
Diodes: IN4001(D1 & D2)


To simulate

Parameters:
Simulate

Select: Place Component :( Ctrl w)
Sources: Signal Voltage Sources:

Pulse Voltage, Set the values (Initial Voltage = 4V, Pulsed Value = -4V,
Delay Time = 0.01msec, Rise Time =0.01msec, Fall time =0.01usec, Pulse
width =0.5msec, Period = 1msec)
AC Power, set the values (Voltage(RMS) =6V, voltage Offset = 0 Frequency
(F) =1K)
DC Power = 2.4V(Vref)
Diodes: IN4001(D1 & D2)

Capacitor 1μF
WITHOUT
REFERENCE
VOLTAGE
C1
0.1uF
V1 = 2.5v V
V2 = -2.5v V1 R6V
TD = 0.01ms D7
200K
TR = 0.01us D1N4002
TF = 0.01us
PW = 0.5ms
PER = 1ms
0
POSITIVE CLAMPER WITHOUT REFERENCE

To simulate

Parameters:
Simulate

POSITIVE CLAMPER WITH REFERENCE

2. CE AMPLIFIER
AIM: Design and construct a suitable circuit and determine the frequency response,
input impedance, output impedance and bandwidth of a CE amplifier..
COMPONENTS REQUIRED: Transistor SL-100, Resistors -22K, 6.8 K, 1K, 470 ,
Capacitors - 0.1 F( 2 numbers) , 0.47 F, DC regulated power supply, Signal generator,
CRO
Theory
In the CE amplifier the output of the first stage is coupled with the input of the next stage
through the coupling capacitor Cc. The resistances R1, R2 and RE form the biasing and
stabilization network. The emitter bypass capacitor CE offers low reactance path to the signal.
The coupling capacitor CC2 transmits ac signal but blocks dc thus preventing dc interference
between various stages.
When ac signal is applied to base of the first transistor, it appears in amplified form across its
collector load RC.
RC coupled amplifiers have excellent audio fidelity over a wide range of frequency. They are
widely used as voltage amplifiers. It has excellent frequency response. The RC network is
broadband in nature therefore, it gives a wide band frequency response without peak at any
frequency and hence used to complete AF amplifier bands. Cutoff frequencies (f1 & f2 in
Fig. 3) are the frequencies at which the voltage gain equals 0.707 of its maximum value. It is
also referred to as the half power frequencies because the load power is half of its maximum
value at these frequencies.
Frequency Response:
The frequency response is the plot of the gain of an amplifier as a function of frequency. It
defines the frequency of operation or bandwidth of the amplifier.
At low frequencies (< 50 Hz) (Lower cut off frequency)
The reactance of coupling capacitor CC is high and hence small part of signal will pass from
one stage to the next stage.
CE cannot shunt RE because of large reactance at low frequencies. These causes voltage gain
increase with increase in frequency. In this region, the amplifier can be modeled as a high pas
filter. Frequency at which the gain raises to 1/√2 times mid band gain A0 is called lower cut-
off frequency, denoted by fL
At high frequencies (>20Khz) (Upper cut-of frequency)

The reactance of CC is small and it behaves as short circuit. This increases the loading effect
of next stage. Capacitance reactance of base emitter junction is low with increase in base
current. This reduces amplification factor and due to these reasons, the amplifier can be
modeled as a low pass filter. The frequency at which gain falls to 1/√2 times the mid band
gain A0 is called upper cut – off frequency denoted by fH.
Bandwidth is defined by BW = fH - fL
At mid frequencies (%0Hz to 20 Khz):
Voltage gain of an amplifier is constant. The effect of coupling capacitor in this frequency
range is such as to maintain a uniform voltage gain. As frequency increases, reactance of C C
decreases which increases the gain. However at the same time, lower reactance means higher
loading of first stage and hence gain decreases. These two factors cancel each other, resulting
in uniform gain at mid frequencies.
Figure 1- Circuit diagram of Single Stage RC Coupled Amplifier
Lead details of the transistor SL100 :- C-Collector, B-Base, E-Emitter

DESIGN:
Given: VCC  10V , I C  5mA &   100

1
To find RE, let VRE  I E RE  VCC  1V , and I E  I C
10
V V 1
Hence RE  RE  RE   200 . Choose RE = 220Ω.
IE IC 5m
To find RC, RC determines the Q-point. Choose RC such that VCE = VCC/2 = 5V
Applying KVL to the CE loop (in Fig. 1), VCC  I C RC  VCE  VRE  0 .
Substituting all the values we get RC = 800Ω. Choose RC = 820Ω (standard resistor value)
I 5m
To find R1: We have VB  VBE  VRE  0.7  1  1.7V and I B  C   50A
 100
Assuming that the biasing network (R1 & R2) is designed such that 10IB flows through R1, we
have VR1  10 I B R1  VCC  VB . Substituting the values of Vcc, VB & IB, R1 = 16.6k Ω.
VB 1.7
Next to find R2, we have VR2 = 9IBR2 =VB. Hence R2    3.7 K . Choose
9I B 9  50A
R1= 18kΩ and choose R2 =3.9kΩ
To find the bypass capacitor CE: Let XCE = RE/10 at f = 100 Hz (remember CE & RE are in
1 R
parallel). Hence X CE   E . Substituting all the values, CE = 72.3 µF.
2fCE 10
Choose CE =100 µF and the coupling capacitors CC1 = CC2 = 0.47 µF.
PROCEDURE:
1. Before making the connections check all components using multimeter.

2. Make the connections as shown in Figure 1.
3. Using a signal generator apply a sinusoidal input waveform of peak-to-peak
amplitude 50mV ( = Vin) to the circuit and observe the output signal on the CRO.
4. Vary the frequency of input from 50Hz to 1MHz range and note down corresponding
output voltage VO in the tabular column.
Note: When the input frequency is being changed the input amplitude (i.e., around 50
mV) should remain constant.
Adjust the amplitude of Vin (in mV) such that the output Vo does not get clipped (i.e.,
saturated) when the frequency is in the mid range say 1kHz.

5. After the frequency has been changed from 500 Hz to 1MHz and the readings are
tabulated in a tabular column, calculate gain of the amplifier (in dB) using the
formula,
Gain in dB = 20 log 10 (Vo/Vin)
6. Plot the graph of gain versus frequency on a semilog sheet and hence determine the
bandwidth as shown in Fig. 3. Bandwidth = B = f2-f1
To find input impedance, set the input DRBI to a minimum value and DRBO to a
maximum value (say, 10k) as shown in figure 2. Now apply an input signal using signal
generator, say a sine wave whose peak-to-peak amplitude is 50mV with a frequency of 10
KHz. Observe the output on CRO. Note this value of output with DRBI = 0 as Vx.
Now increase the input DRBI value till the output voltage Vo = (1/2) Vx. The
corresponding DRBI value gives input impedance.
To measure input Impedance Ri
To find output impedance, set DRBO which is connected across the output to a
maximum value as shown in figure 2, with the corresponding DRBI at the minimum
position. Apply the input signal using signal generator, say a sine wave whose peak-to-
peak amplitude is 50mV with a frequency of 10 KHz. Observe the output on CRO. Note
this value of output with DRBI = 0 as Vx. Now decrease the DRBO value till the output
voltage Vo = (1/2) Vx. The corresponding DRBO value gives output impedance.
To measure output Impedance R0

Note: DRBI is connected between the signal generator and the input coupling capacitor.
DRBO is connected across the output (across the CRO terminals).
The ground symbol in the circuit diagram implies a common point. In some of the power
supplies, there will be three terminals - +(plus), -(minus) and GND (ground). Never
connect this GND terminal to the circuit.
TABULAR COLUMN
Vi = 50 mV (P-P)
f V0 P-P V Power Gain = 20 log10 Av
in Hz volts AV = 0 in dB
V i
50 Hz
--
--
1 MHz
Values
R1 = 22kΩ
R2 = 4.7kΩ
RC = 1KΩ
RE = 270Ω
RL = 10k Ω
CC1 = CC2 =0.47μF
CE=47μF
Fig. 1 : Transistor as a CE amplifier circuit diagram and actual connections (does not show
RL)

Fig. 2: CE Amplifier with DRBs connected at both input and output
WAVEFORMS:
FREQUENCY RESPONSE:
Fig. 3 Frequency response plotted on semilog graph (X-axis is log scale)
RESULT:
1. BANDWIDTH = ……………Hz
2. INPUT IMPEDANCE = ……….. Ω
3. OUTPUT IMPEDANCE = ……….. Ω
Note: Maximum gain occurs in mid frequency region. This is also called mid band gain.
Gain-bandwidth product = Midband gain x Bandwidth

2b. Design and build the CE amplifier circuit using a simulation package and determine
the voltage gain for two different values of supply voltage and for two different values of
emitter resistance.
To design circuit diagram

Select: Place Component (Ctrl w)
AC Power, Set the values (Voltage(RMS)=50mV Voltage Offset = 0, Frequency (F) = 1K)
DC Power = 12V
Basic: Resistors: 16K, 3.9K, 220Ω, 820Ω
Capacitors: 0.47nF, 100μF
Transistors: 2N2222
To Simulate
1. Select Grapher/Analysis list
Select AC Analysis
Parameters:
Start Frequency (FSTART) = 10Hz
End Frequency (FSTOP) = 100 MHz
Sweep Type: Decade
Number points Per Decade = 10
Vertical Scale = Decibel
Output: Add V (6)
Simulate

3. CHARACTERISTICS OF AN ENHANCEMENT MODE MOSFET

Aim: To Design and construct a suitable circuit and determine the drain characteristics
and transconductance characteristics of an enhancement mode MOSFET.
Apparatus required: MOSFET (1RF 740), Resistor (1kΩ), Voltmeters (0-30V range and 0-
10V range), Ammeter (0- 25mA range) and Regulated power supply (2 nos. – variable power
supply)
Theory
Metal oxide semiconductor field effect transistor is widely used in many circuit
applications. The current in this device is controlled by gate to source voltage rather than
negative voltages used in n-channel JFET and it is also referred as voltage controlled device.
The transistor has very high input impedance, consumes less power and of small size.
Construction Details
Drain Drain
Substrate
Gate Gate
Substrate
D S Source
G Symbol
Source
There is only one P-region and is called substrate. A thin layer of metal oxide is deposited
over left side of the channel. A metallic gate is deposited over oxide layer, as silicon dioxide
is an insulator. MOSFET has three terminals namely Source, Gate and Drain.
CIRCUIT DIAGRAM
Figure 1. Enhancement mode (positive gate voltage)

Drain Characteristics: Enhancement Mode

Procedure:
1. Connect the circuit as shown in figure 1.
2. Set the gate voltage to a positive value say V GS = +0.5V. Vary VDD in steps and note
down VDS and ID at each step and record the readings as shown in the tabular
column1.
3. Plot the graph of VDS (X-axis) versus ID (Y-axis) for constant VGS.
Mutual or Transfer Characteristics: Enhancement Mode
Procedure:
1. Connect the circuit as shown in figure 1.
2. Set VDD = 5V (drain to source voltage) so that VDS = 5V. Vary VGG (gate supply) in
steps and note down VGS and ID at each step and record the readings as shown in the
tabular column-2.
3. Repeat the above step (step 2) for VDS = 15V and tabulate the readings as shown in
tabular column -3.
4. Plot the graph of VGS (X-axis) versus ID (Y-axis) for constant VDS .
Drain Characteristics Mutual Characteristics
Enhancement Mode Enhancement Mode

VGS = +0.5V VDS = +0.5V VDS = +15V
VDS (V) ID(mA) VDS (V) ID(mA) VGS (V) ID(mA)
0 +0.1
0.1 +0.2
0.2 +0.3
0.3 .
0.4 .
0.5 .
. .
. .
15V +1.0V

Sample Characteristics to be obtained
Figure 2 . Drain Characteristics and b. Transconductance (or mutual/transfer)

characteristics
Note:
From Mutual Characteristics, transconductance is given by gm = Δ ID / Δ VGS = …………..
Amplification Factor μ = rd x gm
Results:
Drain Resistance rd :…………………
Mutual Conductance gm : …………………
Amplification Factor μ : …………………..

3b. Design and build CMOS inverter using a simulation package and verify its truth
table.
Sources: Signal Voltage Sources:

Pulse Voltage, Set the values (Initial Voltage = 5V, Pulsed Value = -5V,
Delay Time = 0.001usec, Rise Time =1nsec, Fall time =1nsec, Pulse
width =20usec, Period = 40usec)

DC Power = 5V
Transistors:MOS 3TEN:2N7000.
MOS 3TEP:BST100
To simulate

Parameters:
Output: Add V(5) for input waveform
Add V(4) for output waveform
Add V(4) and V(5) for both waveform
Simulate


4. SCHMITT TRIGGER
Aim : Design and construct a Schmitt trigger circuit using op-amp for the given UTP
and LTP values and demonstrate its working.
Components Required: Op-amp μA 741, Resistor of 10KΩ, 90KΩ, DC regulated power

supply (VPRS 0-30 dc), Signal generator, CRO
THEORY:
A comparator with positive feedback is called a regenerative comparator or Schmitt trigger.
This circuit converts an arbitrary waveform to a square wave or pulse. Hence it is also called
as squaring circuit.
In inverting Schmitt trigger, input voltage Vi is applied to the inverting input terminal of the
Op-Amp. The input voltage Vi switches the output voltage V0 to change state each time it
exceeds certain voltage levels called upper threshold voltage VUT and lower threshold voltage
VLT. These voltages are called upper and lower trigger points.
The output switches from positive to negative when input voltage reaches the upper trigger
point and from negative to positive when input falls to lower trigger point.
Threshold voltages are derived using resistive network comprising of R1 and R2 and reference
source VRef. This network provides the feedback voltage which is applied to non-inverting
terminal.
The voltage across R1 is feedback to input of Op=amp, depends on value and polarity of
output voltage V0. When V0=+Vsat, the voltage at the non-inverting terminal is called upper
threshold voltage VUT.
The output voltage switches from +Vsat to –Vsat once Vi exceeds VUT and remains there until
the input falls below VLT where VLT<VUT. So the reverse transition from –Vsat to +Vsat does
not occur at the same value of input voltage as the transition from +Vsat to –Vsat. This is called
as Hysteresis.

Figure 1 Circuit Diagram and actual connections of Schmitt Trigger Circuit

DESIGN:
From theory of Schmitt trigger circuit using op-amp, we have the trip points,
R2 (V sat ) R Vref
UTP   1 where V sat is the positive saturation of the opamp  90% of Vcc
R1  R2 R1  R2
R2 (V sat ) R1Vref
LTP  
R1  R2 R1  R2
Hence given the LTP & UTP values to find the R1 , R2 & Vref values, the following design is used.
2 R1Vref
UTP  LTP  - - - - - -(1)
R1  R2
The Hysterisis voltage VH  UTP - LTP :
2 R2V sat
UTP  LTP  - - - - - -(2)
R1  R2
Case :-1
To design Schmitt trigger circuit for the following specification UTP=2.5V and LTP=1.0V
For the Schmitt trigger, the upper threshold voltage VUT or the upper trip point UTP is given
by
R 2(Vsat ) R1Vref
UTP  
R1  R2 R1  R2
And lower threshold voltage VLT or the lower trip point (LTP) is given by
R2 (Vsat ) R1Vref
LTP  
R1  R2 R1  R2
Where Vsat =12V (if supply voltage = +12 V dc) and the hysteresis width (voltage) VH is
given by
2R2Vsat
VH= UTP  LTP 
R1  R2
2 R1Vref
UTP  LTP 
R1  R2
i.e.
R1
3.5  2 * * Vref ...................(1)
R1  R 2
R2
1.5  2 * * Vsat......................(2)
R1  R 2

From equation -2
R2 1 .5 R2
2* = or = 0.0625
R1  R 2 12 R1  R 2
Therefore
R2
R1+R2=  16 R 2
0.0625
R1=15R2
Choose
R2= 1KΩ Therefore R1= 15 KΩ
From equation- (1)

3.5( R1  R 2) 3.5(16)
Vref =   1.87V  1.9V
2 R1 30
Choose Vref= 1.9V
Procedure:
1. Before doing the connections, check all the components using multimeter.
2. Make the connection as shown in figure 1.
3. Using a signal generator apply the sinusoidal input waveform of peak-to-peak
amplitude of 12V (approx 10V), frequency 1kHz.
4. Keep the CRO in dual mode; apply input (Vin) signal to the channel 1 and observe the
output (Vo) on channel 2 which is as shown in the waveform below. Note the
amplitude levels from the waveforms.
5. Now keep CRO in X-Y mode and observe the hysteresis curve.
Waveforms:
CRO in DUAL mode

CRO in X-Y mode showing the Hysteresis curve

4b. Design and implement a Schmitt trigger using Op-Amp using a simulation package
for two sets of UTP and LTP values and demonstrate its working..

AC Power, Set the values (Voltage(RMS) = 5V, Voltage Offset =0,
Frequency(F) =500Hz)

DC Power = 12 V & 1.9V
Basic: Resistors:15K, 1K
Analog: OPAMP: 741

To simulate

Parameters:
Output: Add V(1) and V(4)
Simulate


5. OP-AMP AS A RELAXATION OSCILLATOR

AIM : Design and construct a rectangular waveform generator (op-amp relaxation
oscillator) for a given frequency and demonstrate its working...
COMPONENTS REQUIRED:
Op-amp μA 741, Resistor of 1KΩ, 10KΩ, 20 kΩ Potentiometer, Capacitor of 0.1 μF,
Regulated DC power supply, CRO
THEORY:
Op-Amp Relaxation Oscillator is a simple Square wave generator which is also called
as a Free running oscillator or Astable multivibrator or Relaxation oscillator. In this figure
the op-amp operates in the saturation region. Here, a fraction (R2/ (R1+R2)) of output is fed
back to the non-inverting input terminal. Thus reference voltage is (R2/(R1+R2)) Vo. And
may take values as + (R2/ (R1+R2)) Vsat or - (R2/(R1+R2)) Vsat. The output is also fed back
to the inverting input terminal after integrating by means of a low-pass RC combination.
Thus whenever the voltage at inverting input terminal just exceeds reference voltage,
switching takes place resulting in a square wave output.
Values
Figure 1Circuit Diagram of Symmetrical Square Wave generator C=0.1μF
(Relaxation Oscillator) R1 = 10kΩ, R2 = 11.6 kΩ,R = 4.7k/5.1kΩ
DESIGN :
1  
The period of the output rectangular wave is given as T  2RC ln   -------(1)
1  
R1
Where,   is the feedback fraction
R1  R2
If R1 = R2, then from equation (1) we have T = 2RC ln(3)
Another example, if R2=1.16 R1, then T = 2RC ----------(2)

1 1
Example: Design for a frequency of 1 KHz (implies T   3  10 3  1ms )
f 10
Use R2=1.16 R1, for equation (2) to be applied.
Let R1 = 10kΩ, then R2 = 11.6kΩ (use 20kΩ potentiometer as shown in circuit figure)
Choose next a value of C and then calculate value of R from equation (2).

T 10 3
Let C=0.1µF (i.e., 10-7), then R    5K
2C 2  10 7
R1
The voltage across the capacitor has a peak voltage of Vc  Vsat
R1  R2
PROCEDURE:
1. Before making the connections check all the components using multimeter.
2. Make the connections as shown in figure and switch on the power supply.
3. Observe the voltage waveform across the capacitor on CRO.
4. Measure the amplitude and frequency of output waveform on CRO.
5. Compare theoretical and practical values
Output Waveform of Relaxation Oscillator
Result:
A rectangular wave generator has been designed and verified for a given frequency
The frequency of the oscillations = ___ Hz.

5b. Design and implement a rectangular waveform generator (Op-Amp relaxation

oscillator) using a simulation package and demonstrate the changes in frequency
when all resistor values are doubled.

DC Power = 12 V
Basic: Resistors:10K, 5K
Capacitor: 100 nF
Analog: OPAMP: 741
To simulate

Parameters:
Output: Add V(1) and V(4)
Simulate


6. ASTABLE MULTIVIBRATOR USING 555 TIMER
AIM : Design and implement an astable multivibrator using 555 Timer for a given
frequency and duty cycle.
COMPONENTS REQUIRED: 555 Timer IC, Resistors of 3.3KΩ, 6.8KΩ, Capacitors of

0.1 μF, 0.01 μF, Regulated power supply, CRO
DESIGN : Given frequency (f) = 1KHz and duty cycle = 60% (=0.6)
The time period T =1/f = 1ms = tH + tL
Where tH is the time the output is high and tL is the time the output is low.
From the theory of astable multivibrator using 555 Timer(refer Malvino), we have
tH = 0.693 RB C ------(1)
tL = 0.693 (RA + RB)C ------(2)
T = tH + tL = 0.693 (RA +2 RB) C
Duty cycle = tH / T = 0.6. Hence tH = 0.6T = 0.6ms and tL = T – tH = 0.4ms.
Let C=0.1μF and substituting in the above equations,
RB = 5.8KΩ (from equation 1) and RA = 2.9KΩ (from equation 2 & RB values).
The Vcc determines the upper and lower threshold voltages (observed from the capacitor
2 1
voltage waveform) as VUT  VCC & VLT  VCC .
3 3
Note: The duty cycle determined by RA & RB can vary only between 50 & 100%. If RA is
much smaller than RB, the duty cycle approaches 50%.
Example 2: frequency = 1kHz and duty cycle =75%, RA = 7.2kΩ & RB =3.6kΩ, choose RA =
6.8kΩ and RB = 3.3kΩ.
Circuit Diagram and actual connections

PROCEDURE :
1. Before making the connections, check the components using multimeter.
2. Make the connections as shown in figure and switch on the power supply.
3. Observe the capacitor voltage waveform at 6th pin of 555 timer on CRO.
4. Observe the output waveform at 3rd pin of 555 timer on CRO (shown below).
5. Note down the amplitude levels, time period and hence calculate duty cycle.
RESULT:
The frequency of the oscillations = ___ Hz.
WAVEFORMS
THEORY:
Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output
waveform is rectangular. The multivibrators are classified as: Astable or free running
multivibrator: It alternates automatically between two states (low and high for a rectangular
output) and remains in each state for a time dependent upon the circuit constants. It is just an
oscillator as it requires no external pulse for its operation. Monostable or one shot
multivibrator: It has one stable state and one quasi stable. The application of an input pulse
triggers the circuit time constants. After a period of time determined by the time constant, the
circuit returns to its initial stable state. The process is repeated upon the application of each
trigger pulse. Bistable Multivibrators: It has both stable states. It requires the application of
an external triggering pulse to change the output from one state to other. After the output has
changed its state, it remains in that state until the application of next trigger pulse. Flip flop is
an example.

LOGIC DESIGN LABORATORY

7. a) Given a four variable expression, simplify using Entered Variable Map (EVM) and
realize the simplified logic using 8:1 MUX.
Aim: Design a circuit diagram to realize simplified logic expression using 8:1 multiplexer IC
Apparatus required: Digital IC trainer kit, patch chords, 74151 IC and 7404IC
Theory:
A multiplexer routes one among the many input 2n to the output based on addressing or
selection it is called many to one logic circuit. An 8:1 multiplexer has 8 inputs and one
output, for addressing it has three selection lines a,b,c pin number(9,10,11), active low enable
lines which can be used independently output lines(5,6)
Entered Variable Map(Map Entered Variable (MEV))

Is an alternative to K-maps where a variable is placed as ouput or one of the input variable is
placed inside K-map. This is done separately how it is related with output.
This reduces the K-map size by one degree i. e four variable problem that requires 24 = 16
cells in the k-maps will require 2(4-1) = 23 =8 cell in entered variable map. This technique is
particularly useful for mapping problems with more input variables.
In MEV method there are nine rules as shown below. Entry in MEV map done by
considering MEV and functional value of the logical expression.

E.g.,
Simplify the function using MEV technique
f(a,b,c,d)=∑m(2,3,4,5,13,15) + dc(8,9,10,11)
Decimal LSB f MEV map entry
0}0 0000 0 0------Do
1 0001 0
1}2 0010 1 1------D1
9 0011 1
0100 1 1-----D2
2}4 0101 1
5
0110 0 0-----D3
3}6 0111 0
7
1000 X X-----D4
4}8 1001 X
9
1010 X X-----D5
5}10 1011 X
11
1100 0 d----D6
6}12 1101 1
13
1110 0 d----D7
7}14 1111 1
15

Pin Diagram of Ics Used:
Design:
Let the given Boolean expression be f(a,b,c,d) = Σm(2,3,4,5,13,15) + dc(8,9,10,11)
By taking tha values and mapping with MEV according to the rules of MEV techniques,
number of variables can be reduces 24 to 24-1 from 16 variables to just 8 variables. These
new variables can be considered as d0, .......d7.
As there are only three selection lines and four variable expression cannot be realized
directly therefore along with three selection lines a,b,c the fourth variable d or d’ becomes
the input to the MUX as decided by the table.


Logic Design with Xilinx Software (VHDL)
7b. Design and develop the verilog/VHDL code for 8:1 MUX. Simulate and verify its
working.
MULTIPLEXER
I 8:1 Zout
8
3
TruthTable SEL
INPUTS OUTPUTS
SEL (2) SEL (1) SEL (0) Zout
0 0 0 I(0)
0 0 1 I(1)
0 1 0 I(2)
0 1 1 I(3)
1 0 0 I(4)
1 0 1 I(5)
0 1 1 I(6)
1 1 1 I(7)
-- VHDL code for 8 to 1 mux (Behavioral modeling).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux1 is
Port ( I : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(2 downto 0);
zout : out std_logic);
end mux1;
architecture behavioral of mux1 is

begin
zout <= I(0) when sel="000" else
I(1) when sel="001" else
I(7);
end behavioral;

8:1 Mux Simulation Results
Output

8 Realize a J-K Master/Slave FF using NAND gates and verify its truth
table.
Aim: To realize a JK Master/Slave flip flop using NAND gates and verify its
truth table.
Components used: IC 74LS00, IC 74LS10, IC 74LS20, Power chords, Patch chords, Trainer
kit.
Pin Details of the ICs: 7400
IC-7410

IC-7420
Theory:
The circuit below shows the solution. To the RS flip-flop we have added two new
connections from the Q and Q' outputs back to the original input gates. Remember that a
NAND gate may have any number of inputs, so this causes no trouble. To show that we have
done this, we change the designations of the logic inputs and of the flip-flop itself. The inputs
are now designated J (instead of S) and K (instead of R). The entire circuit is known as a JK
flip-flop.
In most ways, the JK flip-flop behaves just like the RS flip-flop. The Q and Q'
outputs will only change state on the falling edge of the CLK signal, and the J and
K inputs will control the future output state pretty much as before. However, there
are some important differences.
Since one of the two logic inputs is always disabled according to the output state
of the overall flip-flop, the master latch cannot change state back and forth while
the CLK input is at logic 1. Instead, the enabled input can change the state of the

master latch once, after which this latch will not change again. This was not true of
the RS flip-flop.
If both the J and K inputs are held at logic 1 and the CLK signal continues to
change, the Q and Q' outputs will simply change state with each falling edge of the
CLK signal. (The master latch circuit will change state with each rising edge of
CLK.) We can use this characteristic to advantage in a number of ways. A flip-flop
built specifically to operate this way is typically designated as a T (for Toggle) flip-
flop. The lone T input is in fact the CLK input for other types of flip-flops.
The JK flip-flop must be edge triggered in this manner. Any level-triggered JK

latch circuit will oscillate rapidly if all three inputs are held at logic 1. This is not
very useful. For the same reason, the T flip-flop must also be edge triggered. For
both types, this is the only way to ensure that the flip-flop will change state only
once on any given clock pulse.
Because the behavior of the JK flip-flop is completely predictable under all

conditions, this is the preferred type of flip-flop for most logic circuit designs. The
RS flip-flop is only used in applications where it can be guaranteed that both R and
S cannot be logic 1 at the same time.
At the same time, there are some additional useful configurations of both latches
and flip-flops. In the next pages, we will look first at the major configurations and
note their properties. Then we will see how multiple flip-flops or latches can be
combined to perform useful functions and operations.
Master Slave Flip Flop:

The control inputs to a clocked flip flop will be making a transition at approximately the
same times as triggering edge of the clock input occurs. This can lead to unpredictable
triggering.
A JK master flip flop is positive edge triggered, where as slave is negative edge
triggered. Therefore master first responds to J and K inputs and then slave. If J=0 and K=1,
master resets on arrival of positive clock edge. High output of the master drives the K input
of the slave. For the trailing edge of the clock pulse the slave is forced to reset. If both the
inputs are high, it changes the state or toggles on the arrival of the positive clock edge and the
slave toggles on the negative clock edge. The slave does exactly what the master does.
Function Table:

Clk J K Q --- comment

Q
0 0 Q0 ---- No change
Q0
0 1 0 1 Reset
1 0 1 0 Set
1 1 Q0 Q0 toggle

8b. Design and develop the verilog/VHDL code for DFF with positive edge triggering.
Simulate and verify its working.
--VHDL code for D Flip Flop Counter.
library IEEE;
entity d_ff is
Port ( D,Clk : in std_logic;
Q : inout std_logic;
Qbar : out std_logic);
end d_ff;
architecture behavioral of d_ff is

begin
process(clk)
begin
if rising_edge(clk) then
Q<= D;
end if;
end process;
Qbar<= not Q;
end behavioral;

D-flip flop Simulation Results

9a) Design and implement a mod n (a<8) synchronous up counter using JK FF IC’s and
demonstrate its working.
Aim: To design and implement a mod-n (n<8) synchronous up counter
Components used: IC 74LS76, IC 74LS08, Patch chords, power chords, and Trainer kit.
Pin diagram of 7476
IC:7408

Theory:
A counter is probably one of the most useful and versatile subsystems in digital system. A
counter driven by a clock can be used to count number of clock cycles.
In synchronous counter every flip-flop is triggered in synchronous with the clock i.e. clock
inputs are applied simultaneously to all flip-flops. The up-counter counts the numbers from
000 to 111 for mod 8
Circuit Diagram: QC QB
Input =1 QA
1
3
2
Preset input =1
2’
4’ 9
JC 4
15’ JB 7 11 JA 2 15
QC QB QA
1’ 6 1
KC KB KA
14’ 10 14
16’ 12 16
Clear input
=1
CLK

Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
QBQA
QBQA
00 01 11 10 00 01 11 10
QC QC
0 0 0 1 0 0 X X X X
X X X X 0 0 1 0
1 1
JC = QBQA
KC = QBQA
QBQA
QBQA 00 01 11 10
QC
00 01 11 10 0 X X 1 0
QC X X 1 0
0 0 1 X X 1
0 1 X X
1
KB = QA
JB = QA
QBQA
QBQA
00 01 11 10
00 01 11 10 QC
QC 0 X 1 1 X
1 X X 1
0 1 X 1 1 X
1 X X 1
1
JA = 1 KA = 1

Transition Table:
Present State Next State Jc Kc Jb Kb Ja Ka
Qc Qb Qa Qc+1 Qb+1 Qa+1
0 0 0 0 0 1 0 x 0 x 1 x
0 0 1 0 1 0 0 x 1 x x 1
0 1 0 0 1 1 0 x x 0 1 x
0 1 1 1 0 0 1 x x 1 x 1
1 0 0 1 0 1 x 0 0 x 1 x
1 0 1 1 1 0 x 0 1 x x 1
1 1 0 1 1 1 x 0 x 0 1 x
1 1 1 0 0 0 x 1 x 1 x 1

9b. Design and develop the verilog/VHDL code for mod 8 up counter simulate and
verify its working.
Truth Table
--VHDL code for Mod-8 Counter.
library IEEE;
entity mod_8 is
Port ( rst, clk, en: in std_logic;
q : inout std_logic_vector(3 downto 0));
end mod_8;
architecture behavioral of mod_8 is

begin
process(clk,rst) is
begin
if rst='1' then q<="0000";
elsif rising_edge(clk) then
if en='1' then
Q<=Q+1;
end if;
if Q="0111" then
Q<= "0000";
end if;
end if;
end process;
end behavioral;

Mod-8 Counter Simulation Results
Output

10a) Design and implement ring counter using 4-bit shift register and demonstrate its
working.
Components of used: IC 74LS95, Patch chords, Power chords, Trainer Kit.
Pin Diagram of ICs:
IC-7495
Theory:
Ring Counter is a basic register with direct feedback such that contents of the register simply
circulate around the register when the clock is running. Here last output Qd in a shift register
is connected back to the serial input.
Function Table:
Clk Qa Qb Qc Qd
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1

Circuit Diagram:
Inputs Outputs
Operating M Clk1 Clk2 SD P QA QB QC QD
Mode
Shift(Serial) 0 X D X D qA qB qC
SD = Serial Input Data;
To achieve the serial transfer mode control is connected to “0”. It requires four clock pulses
to clock the data and another three clock pulses to take out the data serially.
Procedure:
1) Verify all components and patch chords whether they are in good condition r not.
2) Make connection as shown in the circuit diagram.
3) Set MC =0
4) Set required data at SD (with LSB)and then apply clock.
5) Repeat step 4 three more times, this clocks the data.
6) Applying clock three more times retrieves the stored data serially out.
7) Verify the truth table.

10b. Design and develop the verilog /VHDL code for switched tail counter. Simulate and
verify its working.
Truth Table
--VHDL code for Johnson counter.
library IEEE;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jc is
Port ( clk, en, rst : in std_logic;
q : inout std_logic_vector(3 downto 0));
end jc;
architecture behavioral of jc is
begin
Process(clk,rst)
begin
if rst='1' then q<="0001";
elsif rising_edge (clk) then
if en='1' then
q<=(not q(0)) & q(3 downto 1);
end if;
end if;
end process;
end behavioral;

Johnson Counter Simulation Results
Output

11. Design and implement asynchronous counter using decade counter IC to count up
from 0 to n (n≤9) and demonstrate its working.
Components used: IC 74LS90, Patch chords, Power chords and Trainer kit.
Pin Diagram of 7490
Theory:
Asynchronous counter is a counter in which the clock signal is connected to the clock input
of only first stage flip flop. The clock input of the second stage flip flop is triggered by the
output of the first stage flip flop and so on. This introduces an inherent propagation delay
time through a flip flop. A transition of input clock pulse and a transition of the output of a
flip flop can never occur exactly at the same time. Therefore, the two flip flops are never
simultaneously triggered, which results in asynchronous counter operation.

Circuit Diagram:
Mod -10 Asynchronous counter
Function Table:
Clock Qa Qb Qc Qd
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
8 1 0 0 0
9 1 0 0 1

12. Design a 4-bit R-2R ladder D/A converter using Op-Amp. Determine its accuracy
and resolution.
Aim: To study the operation of 4-bit DAC using R-2R ladder network.
Components required: Resistors 1KΩ,2.2 KΩ, DMM, OP-741, Connecting wires, IC

Trainer kit.
Circuit diagram:
Theory:
A digital to analog converter (DAC) converts digital data into analog data. That is binary
input data is converted to analog voltage or current. R-2R ladder is the method by which
binary data is translated to suitable analog data.
Resolution (step size): The smallest analog voltage the circuit can provide when
only the LSB is 1. If ‘V’ represents the binary state ‘1’. The step size = V/2 n where’n’ is the
number of bits of input data. For an 8-bit DAC, with V=5; step size ≈ 20mV.
Voltage corresponding to MSB = V/2, irrespective of the size of DAC. Full scale
voltage VFS = V – Step size.

Accuracy: The difference between expected and measured output voltage of the DAC
is called the accuracy. As per design, accuracy should be within ±1/2 of LSB.
Design:
Output Voltage V0 = V (D3 23 + D2 22 + D1 21 + D0 20 )
But V = VR / 24 x 2R/3R
Resolution (step size) = VR/24 = 5/24 = 0.2083V
When D3 = D2 = D1 = D0 =1, V0 (max) = 5 x 15/24 = 3.125V
When D3 = D2 = D1 = D0 =1, V0 (min) = 5 x 1/24 = 0.2083V
Digital Multimeter (DMM)to check output voltage
D0, D1, D2, D3 are digital input.
When inputs are ‘0’ sitches are open therefore no voltage flows.
When inputs are ‘1’ switches are closed therefore voltage flows.
Procedure:
1. Rig up the circuit as per the diagram.
2. Energize the Op-amp pin no. 4 with -12V and pin no. 7 with +12V.
3. Set the input to required state and measure the output voltage with a digital
multimeter.
4. Draw staright line graph of output voltage (Y-axis) and the digital input(X-axis) of
expected and measured values.
5. Verify theoretical values with practical values and observe outputs.

Tabular column:
Decimal Equivalent Input Analog Output Voltage V(V)

D3 D2 D1 D0 Theoretical Practical
0 0 0 0 0 0
1 0 0 0 1 1V = 0.20833
2 0 0 1 0 2V = 0.4166
3 0 0 1 1 3V = 0.625
4 0 1 0 0 4V = 0.833
5 0 1 0 1 5V = 0.10416
6 0 1 1 0 6V = 1.25
7 0 1 1 1 7V = 1.45
8 1 0 0 0 8V = 1.66
9 1 0 0 1 9V = 1.875
10 1 0 1 0 10V = 2.08
11 1 0 1 1 11V = 2.29
12 1 0 1 1 12V = 2.5
13 1 1 0 1 13V = 2.708
14 1 1 1 0 14V = 2.916
15 1 1 1 1 15V = 3.125
Result : 4-bit ladder DAC has been designed and verified.

ELECTRONIC CIRCUITS AND LOGIC DESIGN LABORATORY
Laboratory Questions ( VIVA)
1. What is the difference between the passive and the active electronic components?
Ans. The electronic components are classified into two

 Passive electronic components
 Active electronic components
Passive electronic components

The passive components do not have the capability to amplify or process an electric signal.
They conduct current in both directions.
Examples of passive components

1. Resistors
2. Capacitors
3. Inductors
2. What are the classification of resistors

Ans. Resistors are classified as Fixed ( ) and Variable ( ) type
 Fixed resistors
A fixed resistor is one whose value does not change at all.
Types of fixed resistors

1. Carbon composition resistor
2. Wire wound resistors
3. Metal film resistors
4. Carbon film resistors
 Variable resistors
Variable resistors are usually used in electronic circuits to adjust values of currents
and voltages.
Types of variable resistors

1. Potentiometers
2. Presets
3. What is a capacitor (condenser)? What are the different types of capacitors?

Ans. A capacitor consists of two metal plates kept apart by an insulating material between the
plates.
 It is used to store and release the charge when desired
 When a battery is connected across the terminals of the capacitor, the energy stored in
it will discharge through the resistor
 A capacitor offers a low impedance to ac and high impedance to dc
Due to this reason they are used for coupling ac signal from one circuit to another
 They are also used to block dc components
C= єA/d where C is the capacitance in farads
4. What are the types of capacitors?
Ans. Capacitors are classified as fixed and variable.
Types of capacitors
1. Paper capacitors
2. Mica capacitors
3. Ceramic capacitors
4. Electrolytic capacitor
5. What are inductors?

Ans: Inductance is the property of inductance which opposes any change in the current
flowing
through it.When the current flows through a coiled wire, an electromotive force will be
generated, this force will opposes the flow of current.
6. What are the types of inductors? ( )

Ans : Fixed and variable type of inductors
Examples of fixed type inductors

1. Air core inductor
2. Iron core inductor
3. Ferrite core inductor
Example of variable type inductors
Filter chokes
Radio frequency choke
Audio frequency choke
7. What are active electronic components?

Ans: Devices which are capable of amplifying or processing electrical signals are called
active components.
Examples of active devices
 Semiconductor diode
 Vacuum tube devices
 Gas tube devices
8. What is a semiconductor?
Ans: The name semiconductor is derived from the fact that its conductivity lies between
that
of an insulator and a conductor. Silicon and germanium are some of the popular
semiconductors.

9. How are P-type and N-type semiconductors formed?

Ans: P-type is formed by adding trivalent atoms, N-type is formed by adding pentavalent
atoms to a pure semiconductor.
10. What is doping?
Ans: The process of adding atoms to pure semiconductors to form P-type or N-type
semiconductor is called as doping.
11. What is a semiconductor diode (or P-N junction diode)?
Ans: A semiconductor diode is also called as a P-N diode. A diode is fabricated by joining
together a P-type and N-type semiconductor. It conducts current in one direction
only.
12. Explain positive bias and negative bias.

Ans: The diodes are operated in two modes viz, forward bias and reverse bias.
Forward bias:
The diode is said to be forward bias when a positive voltage is applied at the anode
with
respect to the cathode.
Reverse biased:
When a negative voltage is applied at the anode, the diode becomes reverse biased.
13. Give some examples of diodes
 Signal diode
 Power diode
 Zener diode
 Light emitting diode
 Photo diode
14. Give some application of different types of diodes.

a. The Zener diodes are used as voltage regulators

b. LEDs are employed in seven segment LED displays which are widely used in
electronic displays.
c. The Photo diodes are used to detect the presence of light. It is used in automatic
lighting application burglar alarm, receivers of optical communication, etc.
d. Signal diodes are used in low voltage and low power applications.
15. What are transistors?
Ans: It is basically a silicon or germanium crystal containing three separate layers
(Emitter, Base and Collector). It is also considered as two diodes connected back to back.
16. What are the types of the transistors

Ans: Transistors are of two types NPN and PNP. It has 3 layers, the middle layer is called
as the Base (B) and the others are Emitter (E) and Collector (C).
NPN PNP
17. What are bipolar junction transistors (BJT)?

Ans: BJT’s are transistors in which the current is established by positive and negative
charge carriers.
18. What are the applications of transistors

Ans: Transistors are widely used for amplification and oscillation.
19. What is β? Give its typical value.
Ans: β is the current amplification factor of CE amplifier. It’s typical value is 200.
20. Which are the regions of operation of a transistor and how it can be driven into these
regions?
Ans: The regions of operation are Cut- off, Saturation and Active.
If E-B and C-B junctions are reverse biased, then transistor will go to Cut –off state.
If E-B and C-B junctions are forward biased, then transistor is in Saturation region.
If E-B is forward biased, C-B junction is reverse biased, then the transistor is in Active
region.

21. What are the uses of these regions?

Ans: If a transistor is in the Cut-off or Saturation region it acts as a Switch
If a transistor is in Active region then it functions as an Amplifier.
22. What is the use of a CC amplifier stage?

Ans:It is used as buffer to prevent loading of a signal source. Suppose if a signal source of
5V
with internal impedance of 100 Ω is connected to a 100 Ω load, then the voltage
across
the load will be half of the source voltage i.e., 2.5V. This means a low resistance loads
the
signal source. But if the load is of high impedance about 10K, the voltage across the
load
will be 5V itself. Therefore a CC amplifier stage can be connected in between a
source
and a low impedance load since it has high input impedance and low output
impedance.
23. Why common collector (CC) stage is called as an Emitter follower?
Ans: Because a change in base voltage appears as an equal change across the load at
emitter.
In other words, emitter follows the base voltage.
24. What is the significance of hFE? How it is different from hfe?
Ans: hFE is the DC forward current transfer ratio in CE stage and is given by the
expression
hFE= IC / IB = βDC. It is also called dc current gain of CE transistor.
hfe is ac current gain which equals the ac collector current divided by the ac base
current. Both values do not differ by large amount.
25. Why transistor CE configuration is preferred as switch?
Ans: It needs low current and voltage at the input.
26. What is early effect?
Ans: When the reverse bias voltage at collector increases, the depletion region at the C-B
junction gets widened. The depletion region penetrates deep into base region than the
collector region because of the less number of carriers in Base. This effect is called
early

effect or base-width modulation.
27. What is a clipping circuit ( or a slicer) ?

Ans: They are linear wave shaping circuits. They are useful to clip off the positive or the
negative portions of an input waveform.
28. What is a clamping circuit?
Ans: The clamper shifts the a signal positively or negatively by adding a dc voltage to the
signal.
29. What are the applications of the clampers?
Ans: Clampers are used in analog television receiver.
30. What do you mean by bandwidth?

Ans: The range of frequency over which the gain is equal to or greater than 70.7% of max
gain.
31. What is Gain?
Ans: The ratio of output quantity to the input of the amplifier is called gain.
32. What is frequency response?
Ans: The voltage gain of an amplifier varies with signal frequency because of reactance of
the
capacitors in the circuit changes with signal frequency and hence affects the output
voltage. The curve between voltage gain and signal frequency of an amplifier is
known
as frequency response.
33. What is decibel gain?
Ans: The common logarithm of power gain is known as bel power gain.
Pout
Power gain= log10 Pin bel
34. Which are the other names for clamping circuit?

Ans: DC restoring or inserting circuits.
35. Wht is meant by Q point ?
Ans: Q point means quiescent operating point. It is an operating point selected on the load
line
along which the output voltage swings.
36. What is the difference between oscillator and an amplifier ?

Ans: An oscillator is the basic element of all ac signal sources. It generates a sinusoidal
signal
of known frequency and amplitude.
Application of an Oscillator
 An oscillator is mostly used in electronic communication equipments.
 “Local” oscillators are used to assist the reduction of the incoming radio frequency
(RF) to a lower intermediate frequency in different modulations like AM (amplitude
modulation) and FM (frequency modulation) super heterodyne receivers.
 Oscillator circuits are also used to generate the RF carrier in the “exciter” section of a
transmitter.
 They are also used as “clocks” in digital systems such as microcomputers, in the sweep
circuits found in TV sets and oscilloscopes.
An Amplifier
 An amplifier strengthens the input signal without any change in its waveform and
frequency. The additional power required comes from the external dc source. Thus an
amplifier can be called as an energy converter that draws energy from a dc supply and
converts it into ac energy at signal frequency, the energy conversion process being
controlled by the input signal. The main difference with an oscillator is that an
oscillator does not need any external signal either to start or maintain the process of
energy conversion. Apart from this, the energy conversion process is controlled by the
oscillator circuit itself, above. In an oscillator, the passive components that are used for
the circuit decides the output signal frequency. In order to bring a change in the output
signal a change in the passive components is enough. Oscillator may provide fixed or
variable frequency.
37. What is a RC phase shift oscillator?
Ans: An oscillator is an electronic circuit for generating an ac signal voltage with a dc
supply
as the only input requirement. The frequency of the generated signal is decided by the
circuit constants. An oscillator requires an amplifier, a frequency selective network,
and
a positive feedback from the output to the input.
38. What is the Barkhausen criterion for sustained oscillation?
Ans: The Barkhausen criteria for sustained oscillation is Aβ=1 where A is the gain of the

amplifier and β is the feedback factor.

Unity gain means signal is in phase.
If the signal is 1800 out of phase, then the gain will be = -1
39. Classify the sinusoidal oscillators?
Ans: Sinusoidal oscillators can be classified as RC and LC oscillators. The LC oscillators
are used for high frequency generation while RC oscillators are used for audio
frequency oscillators.
40. How many types of multivibrators are there?

Ans: Basically there are three types of multivibrators, Astable multivibrator, Monostable
multivibrator and Bistable multivibrators.
41. What is the difference between the astable multivibrator and monostable
multivibrator?
Ans: Astable multivibrator is also known as free running oscillator. It does not have a
stable state. This circuit transits from one quasi-stable state to the other and back
automatically.
A monostable multivibrator has only one stable state. It has quasi-stable state also. An
external trigger forces this circuit to go to quasi-stable state from its stable state and
remain in that state for an amount of time
42. What is the application of an astable multivibrator?
Ans: It is a square wave generator which supplies square wave with required amplitude
and frequency. This circuit can be used as a voltage to frequency convertor with
necessary changes in the circuit.
43. What is a bistable multivibratior?
Ans: A bistable multivibratior circuit has two stable states. An external trigger switches
this circuit from one stable state to the other. Another trigger is needed to switch this
circuit back to the old stable state. Bistable multivibratior is also called a flip flop or
binary circuit.
44. What are the applications of the of multivibrator?
Ans:
1. Frequency divider
2. Pulse stretcher
3. Square wave generator
4. Free running Ramp generator

45. What is a Schmitt trigger circuit?

Ans: Schmitt trigger is a comparator circuit that converts a periodical random analog
waveform to a good quality square pulse having the same frequency as that of the
analog waveform. Due to this Schmitt trigger is called a squaring circuit.
46. What is Duty cycle?
Ans: Duty cycle is a measure of the waveform how symmetrical it is. It is given by
D=Ton/T
47. What Is a rectifier? Name types of rectifier.

Ans: Rectifier is device which converts ac to dc. Different types of rectifier are
1. Half wave rectifier
2. Full wave rectifier
3. Bridge rectifier
48. What is ripple factor?
Ans: The ratio of RMS value of ac component to the dc component in the rectifier output
is known as ripple factor.
49. What is a filter?
Ans: A filter circuit is a device which removes ac component of rectifier output but allows
the dc component to reach the load.
50. What is an op-amp?
Ans: An operational amplifier is a circuit that can perform mathematical operations, and
are widely used in computer as video and audio amplifiers.
51. What are the properties of Op-amp?
Ans: An op-amp is a multistage amplifier
1. It has inverting and non-inverting input
2. It has high input impedance
3. It has low output impedance
4. It has large open loop voltage gain
5. It has very large CMRR
.
52. What are UTP and LTP?
Ans: The input voltage Vi switches the output voltage Vo to change state each time it
exceeds certain voltage levels called VUT and VLT. These voltage levels are also called
as upper and lower trigger points (UTP and LTP).

53. What is hysteresis?

Ans: The output voltage switches from +Vsat to –Vsat once Vi exceeds VUT and remains
until the input falls below VLT. Reverse transition from –Vsat to +Vsat does not occur at the
same value of input voltage as the transition from +Vsat to _Vsat. VH=VUT-VLT
54. When does Schmitt trigger exhibit hysteresis?
Ans: A Schmitt trigger exhibits hysteresis when lop gain is greater than one
55. What are logic gates?
Ans: In digital electronics, a gate is a logic circuit with one output and with one or more
inputs.
56. What are the basic gates?
Ans: The basic gates are
Sl. Num Gates Symbols Function
1. The AND gate performs logical

1 AND gate multiplication, commonly known
as AND operation.
( IC number 7408)
2. The AND gate output will be in
High state (1) only when all the
inputs are high
2. OR gate 1. The OR gate performs logical

addition.
( IC number 7432) 2.The output will be high if any

one of the input is logical high
3. NOT gate 1.The NOT gate performs a

function called Inversion or
( IC number 7404) Complementation
2. The purpose of this NOT gate is

it changes from one logic level to
another.

57. What are the universal gates? Why are they called so?
Ans: NAND and NOR gates are known as universal gates. Using any one type of these
gates, any kind of Boolean expression or the basic logic gates can be realized.
NAND gate (IC number 7400)
NOR gate (IC number 7402)
58. Differentiate between positive and negative logic
Ans: In positive logic, high voltage is considered as logic high and low voltage is
considered
as logic low.
In negative logic the high voltage is considered as logic low and the low voltage is
considered as logic high.
59. What is a flip flop (FF)?

Ans: A flip flop is a basic building block in any memory system since it output always
remains in its state until it is forced to change it by some means.
60. Name few popular flip flops.
Ans:
o Clocked SR FF
o JK FF
o Master Slave JK FF
o D FF
o T FF
61. What is a shift register?
Ans: A register is simply a group of FFs that can be used to store a binary number. A shift
register accepts a binary number and shifts it. The data can be entered in the shift
register either in serial or parallel.
62. What are Ring counter and Johnson counter?

Ans: Ring counter and Johnson counter are basically shift registers.
63. Differentiate between Sequential circuit and Combinational circuit.

Ans: A combinational circuit can be defined as a circuit whose output is dependent only on
the inputs at the same instant of time where as a sequential circuit can be defined as a
circuit whose output depends not only on the present inputs but also on the past
history of inputs.
64. Explain the terms resolution (R), linearity, and accuracy as applied to a DAC ( Digital
to Analog Converter)
Ans: The resolution of DAC which can accept N bits is expressed as
1
R= 100%
2N -1
Linearity :
It is defined as the variation of analog output from the curve plotted between digital
input and analog output for ideal DAC.
Accuracy:
It is a measure of difference between the actual output voltage and ideal output
voltage.
65. What is the difference between Clear and Preset?
Ans: Generally Clear and Preset are active low inputs. Logic ‘0’ at the Preset terminal
will make Q output ‘1’ and logic ‘0’ at Clear pin will make Q output ‘0’.
66. Mention the application of Ring Counter?
Ans:
 To produce time Delay: The Serial In serial Out (SISO) shift register can be used
as a time delay device. The amount of delay can be controlled by
a. Number of stages in the register
b. The clock frequency
 To simplify combinational logic:
a. The ring counter technique can be effectively utilized to implement
synchronous sequential circuit.
67. What is VHDL?
Ans: VHDL (Very high speed Integrated circuit Hardware Description Language).
A hardware description language is inherently parallel, i.e. the commands, which
correspond to logic gates, are executed (computed) in parallel as soon as new input
arrives. A HDL program mimics the behavior of a physical, usually a digital system. It

allows incorporation of timing specifications (gate delays) as well as to describe a

system as an interconnection of different components.
68. What are the advantages of VHDL?
Asn: VHDL offers the following advantages for digital design
1. Standard:
VHDL is an IEEE standard, just like any other standard it reduces confusion and
makes interfaces between tools, companies, and products easier. Any development to
the standard would have better chances of lasting longer and have less chance of
becoming obsolete due to incompatibility with other.
2. Portability:
The same VHDL code can be simulated and used in many design tools and at different
stages of the design process. This reduces dependency on a set of design tools whose
limited capability may not be competitive in later markets. The VHDL standard also
transforms design data much easier than a design database of a proprietary desigm tool.
3. Modeling Capability:
VHDL was developed to model all levels of designs, from electronic boxes to
transistors. VHDL can accommodate behavioral constructs and mathematical routines
that describe complex models, such as queuing network and analog circuits. It allows
the use of multiple architectures and associates with the same design during various
stages of the design process.
4. Reusability:
Certain common designs can be described, verified, and modified slightly in VHDL for
future use. This eliminates reading and marking changes to schematic pages, which is
time consuming and subject to error.
For example, a parameterized multiplier VHDL code can be reused easily by changing
the width parameter so that the same VHDL code can do either 16 by 16 0r 12 by 8
multiplications.
69. Briefly explain the structure of a VHDL file
Ans:

VHDL Entity
Ports Interface
(Entity declaration)
Body
(Architecture)
Sequential,
Combinational
process
Sub
programs
Figure1. A VHDL entity consisting of an interface (entity declaration) and a body

(architectural description)
A digital subsystem in VHDL consists of a design entity that can contain other entities that
are then considered components of the top-level entity. Each entity is modeled by an entity
declaration and an architecture body. One can consider an entity declaration as an interface to
an outside world that defines the input and the output signals, while the architecture body
contains the description of the entity and is composed of interconnected entities, processes,
components, all operating concurrently, as schematically shown in above figure 1. In typical
design there will be many such entities connected together to perform the desired function.
VHDL uses keywords that cannot be used as signal names or identifiers. Key words and
user-defined identifiers are case insensitive. Lines with comments start with two adjacent
hyphens(--)
and will be ignored by the compiler. VHDL also ignores line brakes and extra spaces. VHDL
is strongly typed language which implies that one has always to declare the type of every
object that can have a value, such as signals, constants and variables.

70. What is the general structure a VHDL code?

Ans: It comprises of
I. Primary design unit Model structure
a. Entity declaration format
b. Architechture
II. Packages
a. Declaration libraries
b. Identifiers, Numbers, Strings and Expressions
c. Data types
d. Objects: Signals, Constants, and Variables
e. Concurrent Statements
1. Signal assignment
2. Process statement
3. Block Statement
4. Procedure Statement
5. Component Instantiation
6. Concurrent assertion
7. Generate Statement
f. Sequential Statements
1. Wait statement
2. Signal Assignment
3. Variable Assignment
4. Procedure Call
5. Conditional Statements
6. Loop statements
7. Procedure Statements
8. Function Statements
g. Other IEEE “std.logic” functions
h. Object Attributes
i. The TEXTIP Package

Colour Code for Resistors
First-band Second-band Third-band Fourth-band

Color
Digit Digit Multiplier Tolerance
Black 0 0 100 = 1
Brown 1 1 101 = 10 1%
Red 2 2 102 = 100 2%
Orange 3 3 103 = 1000 3%
Yellow 4 4 104 = 10000 4%
Green 5 5 105 = 100000
Blue 6 6 106 = 1000000
Violet 7 7 107 = 10000000
Gray 8 8 108 = 100000000
White 9 9 109 = 1000000000
Gold 5%
Silver 10%
None 20%

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Electronic Circuits & Logic Design

Electronic Circuits & Logic

Vaidehi M & Rashmi N

DEPT. INFORMATION SCIENCE and ENGINEERING Page 1

Electronic Circuits & Logic Design Laboratory

DEPT. INFORMATION SCIENCE and ENGINEERING Page 2

Electronic Circuits Laboratory

Apparatus required: Diode (BY-127 / IN4007), Resistors-10 K & 3.3k, DC regulated

Positive Clipping Circuit

Fig.1 a Positive clipper Circuit b. Transfer Characteristics

Let the output voltage to be clipped to say +2V

Therefore Vo (max) = Vref = 2V

The value of resistor R is chosen to be

R = √Rf x Rr = √10 x 10 x 106 = 10KΩ

When Vi < VR , diode ‘D’ is OFF and V0 =VR

DEPT. INFORMATION SCIENCE and ENGINEERING Page 1

When Vi > VR , diode ‘D’ is ON and V0 = Vi

1. Connect the circuit as shown in fig.

Fig. 2. Input and output waveform for Positive Clipper

DOUBLE ENDED CLIPPER

Fig.3 Double ended clipper Circuit b. Transfer Characteristics

DEPT. INFORMATION SCIENCE and ENGINEERING Page 2

To generate a symmetrical square wave of amplitude ±4V(i.e. output to be

We have Vo(max) = VRef 1 + Vr

Where Vr is diode drop ≈ 0.6V

Therefore VRef 1 = Vo(max) - Vr

VRef 1 = 4 – 0.6 = 3.4V

Also Vo(min) = -4V

We have Vo(min) = VRef2 - Vr

Therefore VRef2 = Vo(min) + Vr

VRef2 = -4 + 0.6 = -3.4V

The value of resistor R is chosen to be

R = √Rf x Rr = √10 x 10 x 106 =

1. Connect the circuit as shown in fig.

DEPT. INFORMATION SCIENCE and ENGINEERING Page 3

Fig. 4. Input and output waveform for double-ended clipping circuit

Apparatus required: Diode (BY-127), Resistor of 10K, Capacitor -1 F, DC regulated

Fig. 5 Positive Clamper

In certain applications, a periodic waveform has to be shifted above or below a certain

DEPT. INFORMATION SCIENCE and ENGINEERING Page 4

VRef = Vo(max) - Vr = 3 – 0.6 = 2.4V

Given frequency = 1KHZ, therefore T = 1msec

Let R = √Rf x Rr = 10KΩ

1. Connect the circuit as shown in fig.

DEPT. INFORMATION SCIENCE and ENGINEERING Page 5

DEPT. INFORMATION SCIENCE and ENGINEERING Page 6

Electronics Circuits with Multisim

1. Place parts, connect wire.

To Design the circuit diagram:

Select Place Component :( Ctrl w)

Sources: Power Sources:

Sources: Power Sources:

DEPT. INFORMATION SCIENCE and ENGINEERING Page 7

1. Select Grapher/Analysis List(simulate-Analyses)

DEPT. INFORMATION SCIENCE and ENGINEERING Page 8

To Design the circuit diagram:

Select: Place Component:( Ctrl w)

Sources: Power Sources:

Sources: Power Sources:

DC Power = 3.4V(Vref1 & Vref2)

Diodes: IN4001(D1 & D2)

DEPT. INFORMATION SCIENCE and ENGINEERING Page 9