Device Structure Enhancement

Shreejita Chaudhuri
Ishan Lakhwani
Dept of. Electronics and
Dept of. Electronics and
Communication
Communication
Nirma University
Nirma University
Ahmedabad,India
Ahmedabad,India
16bec045@nirmauni.ac.in
16bec046@nirmauni.ac.in
 Abstract—This paper covers different methods that can be
used to enhance the structure of a MOSFET device. The
various techniques used are Strained-SI/SI-Ge On Insulator
(Strained-SOI), Reverse Embedded Side (Rev. e-Side)
Structure, Subband Structure Engineering and Annular
Transistor Design.
Keywords— SOI, Strained SOI, SIMOX, Reverse
embedded-SiGe (Rev. e-SiGe), SiGe, Sub-band
structure, Annular Transistor, Annular MOSFET,
edgeless MOSFET, enclosed
MOSFET
I.INTRODUCTION
MOSFETs with a high quality channel are a key interest
as advanced CMOS device structures, which improve
several physical limitations. From this viewpoint,
MOSFETs with strained-Si/ SiGe structures are
promising for high performance and low power CMOS
applications, because of the high electron and hole
mobility caused by strain-induced hand splitting.
Also, the optimum design of the subband structure in the
inversion layer can allow the channel to significantly
improve the MOSFET performance.
By designing the enclosed transistor in an annular shape,
the channel electric field will be changed by the
curvature of the gate compared to a conventional
MOSFET with an equivalent MOSFET reliability due to
hot carrier generation at the drain.
II.SILICON ON INSULATOR TECNOLOGY
A] SOI
Silicon on insulator (SOI) technology refers to the
employment of a layered silicon–insulator–silicon
substrate in place of standard silicon substrates in
semiconductor producing, particularly microelectronics,
to cut back parasitic device capacitance, thereby
improving performance.
Silicon on Insulator (SOI) technology has been researched
for decades. SOI is attractive because it offers potential for
higher performance and lower power consumption. SOI
MOSFET performance depends on the silicon film
thickness. SOI devices with a film thickness greater than the
depletion region is commonly referred to as partially
depleted. A fully depleted SOI device has an active silicon
film thinner than depletion region and hence the whole body
region is depleted.
The Processing techniques for the fabrication transistors in
bulk and SOI CMOS are very similar. The basic difference
between SOI and bulk CMOS technology is that the
transistor source, drain and body are surrounded by
insulating oxide rather than the semi-conductive substrate or
well. In SOI technology the circuit elements are isolated
dielectrically, which significantly reduce the junction
capacitances and Bulk CMOS Silicon On Insulator (SOI)
CSB CDB n+ n+ p-substrate n+ n+ Silicon substrate SiO2 p
Active region Gate 6 allow the circuits to operate at high
speed or substantially lower power at the same speed. The
insulator layer in the SiMOX SOI devices is known as the
buried oxide or BOX layer. This BOX layer provides
isolation of transistors from silicon substrate underneath it.
B] STRAINED SOI
To satisfy requirements of both high current drive
and low supply voltage, we can introduce high mobility
channel such as strained Si. Strained-SOI MOSFETs are
successfully fabricated by combining SIMOX technology
with re-growth of strained Si and that n- and p-MOSFETs
have mobility of 1.6 and 1.3 times higher than the universal
one, respectively.[1]
C] SIMOX
SIMOX technology has been developed for fabricating
SOI-type devices. In this technology, buried silicon
oxide is employed for the vertical isolation of
semiconductor devices. The buried oxide is made by
oxygen-ion implantation into silicon, followed by
epitaxial growth of silicon onto the surface of the
residual silicon on top of the buried oxide.
III.STRAINED-SI/SI-GE ON INSULATOR (STRAINED-SOI)
MOSFETS
Electron and hole mobility is almost twice in strained
silicon as compared to unstrained ones.
strained-SO1 MOSFETs become more attractive, because of
(1)maximized mobility due to low impurity scattering and
low ECw,
(2) low junction capacitance and leakage current and
(3)reduction in statistical variation of V.
Challenges:
1.Downscaling of strained MOSFETs:
Degradation of carrier mobility occurs in strained-Si
n-MOSFETs for less than 25 nm channel length.
2. Self-heating effects in advanced strained SOI devices:
Extremely Thin Body SOI (ETSOI) MOSFET suffers from
the self-heating especially in strained channel devices since
SiGe layer have 15 times lesser thermal conductivity than
the Si. Self-heating raises a serious issue for using strained
SOI MOSFET in analog applications where constant power
is required. However, this problem has lesser impact on
conventional digital applications because most of the power
dissipation occurs at the time of switching only.[2]
IV. REVERSE EMBEDDED SIDE (REV. E-SIDE) STRUCTURE
Strain engineering has become a critical tool for enhancing
the performance of sub-100-nm MOSFETs, and a great
variety of strain techniques have been developed. However,
each of these techniques has limitations; for example, the
magnitude of strain is often not as large as desired, and for
many of the techniques the channel strain decreases as the
device is scaled down. It has proven to be especially
difficult to maintain strain and strain-related current
enhancement in ultrascaled NMOSFETs.

There is therefore a great need for novel strain techniques

that induce large magnitudes of strain in the channel, that do
not lose effectiveness with scaling, and that can be applied
to NMOSFETs. A new reverse embedded-SiGe (Rev. e-
SiGe) strained-silicon technique was demonstrated by
Donaton et al. in that may meet these criteria. This
technique uses elastic relaxation of a buried, compressively
strained SiGe layer to induce tensile strain in the overlying
silicon channel.[3]

V. SUBBAND STRUCTURE ENGINEERING

A]
It is found that SO1 MOSFETs with SO1
thickness thinner than the inversion layer of bulk
MOSFETs can provide higher current drive than bulk
MOSFETs, because of the significant modulation of the
subband structure. This performance enhancement is
attributed to the increase in both the inversion-layer
mobility and the inversion-layer capacitance.

Enhancement of inversion-layer mobility becomes more

First, a standard CMOS fabrication process is completed
through the STI step. Next, the NMOSFET active areas are
etched to create a small recess and thin compressed SiGe
and relaxed silicon layers are epitaxially grown on the active
areas.
important in scaled CMOS from the viewpoints of both
higher performance and lower power consumption. The
severe influence of inversion-layer capacitance prevents
MOSFETs with ultra-thin gate oxides from operating at
low supply voltage. This paper presents an engineering
scenario of the subband structure in the inversion layer
for the enhancement of electron mobility in n-MOSFETs.
[4]
B]PRINCIPLE OF SUBBAND ENGINEERING

The SiGe layer is compressively strained because its lattice
constant is larger than the lattice constant of silicon. Then,
the process is continued through a standard gate stack
process including gate oxide growth, gate and silicon nitride
cap deposition, gate etch, extension, and halo implant, and
spacer definition. The source/drain areas are then etched.
This is the most important step in the process, as it creates a
lateral free surface allowing the compressed buried SiGe
layer to elastically expand, reducing the compressive stress
in the SiGe and inducing tensile stress in the silicon above.
Silicon is then regrown in the recessed source/drain areas
and the CMOS fabrication process is continued to
completion.
Gm, in the triode region, which is still a good indicator of
thecurrent drive in short-channel MOSFETs in terms of
velocity overshoot is described by:
Thus, higher p and larger Cinv, which increases the
gatechannel capacitance, C,, are required for higher current
drive of MOSFETs. Frlom this viewpoint, the 2-fold valleys
in the subband structure of 2D electrons on a (100) surface
are the optimum e1ectronic system.
A new scenario of the subband structure engineering was
proposed to obtain higher current drive of Si MOSFETs.
It was demonstrated that the current drive of SO1 MOSFETs
with Tsol thinner than 5 nm can be higher than that of bulk
MOSFETs, because of the increase in both p and Cinv.

VI. ANNULAR TRANSISTOR DESIGN


In order to build radiation hardened devices enclosed
transistors are built.[5] These transistors eliminate the edges
which are known to create leakage paths in NMOS
transistors. These edgeless, radiation hardened transistors
are also called annular transistors.[6]
VII.REFERENCES
[1] R. Sharma and A. K. Rana, “Strained Si:
Opportunities and challenges in nanoscale
MOSFET,” 2015 IEEE 2nd Int. Conf. Recent Trends
Inf. Syst. ReTIS 2015 - Proc., pp. 475–480, 2015.
[2] S. Takagi et al., “Channel structure design,
fabrication and carrier transport properties of
strained-Si/SiGe-on-insulator (strained-SOI)
MOSFETs,” vol. 1, pp. 3.3.1-3.3.4, 2004.
[3] J. G. Fiorenza, J. S. Park, and A. Lochtefeld,
“Detailed simulation study of a reverse embedded-
SiGe strained-silicon MOSFET,” IEEE Trans.
Electron Devices, vol. 55, no. 2, pp. 640–648, 2008.
[4] S. Takagi, J. Koga, and A. Toriumi, “Subband
structure engineering for performance enhancement
of Si MOSFETs,” vol. 410, pp. 219–222, 2002.
[5] “Study of Soi Annular,” 2009.
[6] D. C. Mayer, R. C. Lacoe, E. E. King, and J. V.
Osborn, “Reliability enhancement in high-
performance MOSFETs by annular transistor
design,” IEEE Trans. Nucl. Sci., vol. 51, no. 6 II, pp.
3615–3620, 2004.
.