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What is Timing Analysis??

We want to verify whether our circuit meet all


of its timing requirements (Timing Constraints)
There are 3 types of design constraints- timing,
power, area.
During designing there is a trade-offs between
speed, area, power, and runtime according to
the constraints set by the designer.
However, a chip must meet the timing
constraints in order to operate at the intended
clock rate
Reasons for performing Timing Analysis
• We want to make sure that circuit is properly
designed and can work properly for all
combinations of components over the entire
specified operating environment. "Every Time".
• Timing analysis can also help with component
selection.
– An example is when you are trying to determine what
memory device speed, you should use with a
microprocessor. Using a memory device that is too
slow may not work in the circuit (or would degrade
performance by introducing wait states), and using
one that is too fast will likely cost more than it needs
to.
• Timing analysis is the methodical analysis of a
digital circuit to determine if the timing
constraints imposed by components or
interfaces are met.
• Typically, this means that you are trying to
prove that all set-up, hold, and pulse-width
times are being met.
• Note: Timing analysis is integral part of
ASIC/VLSI design flow. Anything else can be
compromised but not timing!
Types of Timing Analysis
• There are 2 types of Timing Analysis-
• Static Timing Analysis:
– Checks static delay requirements of the circuit
without any input or output vectors.
• Dynamic Timing Analysis:
– verifies functionality of the design by applying
input vectors and checking for correct output
vectors.
Basic Of Timing Analysis
• The basis of all timing analysis is the clock and
the sequential component (here we will
discuss with the help of Flip-flop).
Clock related
• Timing analysis must ensure that any clocks that are
generated by the logic are clean, are of bounded
period and duty cycle, and of a known phase
relationship to other clock signals of interest.
• Certain circuits, such as PLLs, may have other
requirements such as maximum jitter. As the clock
speeds increase, jitter becomes an increasingly
important parameter.
• Jitter- Jitter is the short-term variations of a signal with
respect to its ideal position in time
• When "passing" data from one clock edge to the other,
ensure that the worst-case duty cycle is used for the
calculation.
Flip-Flop related:
• All of the flip-flops parameters are always met.
The only exception to this is when synchronizers
are used to synchronize asynchronous signals
• For asynchronous presets and clears, there are
two basic parameters that must be met.
• All setup and hold times are met for the
earliest/latest arrival times for the clock.
• When passing data from one clock domain to
another, ensure that there is either known phase
relationships which will guarantee meeting setup
and hold times or that the circuits are properly
synchronized.
Static Timing Analysis
• Static timing analysis is a method of validating
the timing performance of a design by
checking all possible paths for timing
violations under worst-case conditions.
• It considers the worst possible delay through
each logic element, but not the logical
operation of the circuit.
In comparison to circuit simulation, static
timing analysis is
• Faster - It is faster because it does not need to
simulate multiple test vectors.
• More Thorough - It is more thorough because
it checks the worst-case timing for all possible
logic conditions, not just those sensitized by a
particular set of test vectors.
• Once again Note this thing : Static timing
analysis checks the design only for proper
timing, not for correct logical functionality.
The Way STA is performed on a given Circuit:

• To check a design for violations or say to


perform STA there are 3 main steps:
• Design is broken down into sets of timing
paths
• Calculates the signal propagation delay along
each path
• And checks for violations of timing constraints
inside the design and at the input/output
interface.
Timing Paths:
• Timing paths can be divided as per the type of signals (e.g clock signal,
data signal etc).
Types of Paths for Timing analysis:
• Data Path
• Clock Path
• Clock Gating Path
• Asynchronous Path

• Each Timing path has a "Start Point" and an "End Point". Definition of Start

Point and End Point vary as per the type of the timing path. E.g for the

Data path- The start point is a place in the design where data is launched

by a clock edge. The data is propagated through combinational logic in the

path and then captured at the endpoint by another clock edge.


Data path
• Start Point
– Input port of the design (because the input data
can be launched from some external source).
– Clock pin of the flip-flop/latch/memory
(sequential cell)
• End Point
– Data input pin of the flip-flop/latch/memory
(sequential cell)
– Output port of the design (because the output
data can be captured by some external sink)
If we use all the combination of 2 types of Starting Point and 2 types of End Point, we
can say that there are 4 types of Timing Paths on the basis of Start and End point.
Input pin/port to Register(flip-flop).
Register (flip-flop) to Register (flip-flop)
Register (flip-flop) to Output pin/port
Input pin/port to Output pin/port.

Timing Path- 4 types of Data Path

PATH1- starts at an input port and ends at the data input of a sequential element.
(Input port to Register)
PATH2- starts at the clock pin of a sequential element and ends at the data input of a
sequential element. (Register to Register)
PATH3- starts at the clock pin of a sequential element and ends at an output
port.(Register to Output port).
PATH4- starts at an input port and ends at an output port. (Input port to Output port)
Clock Path
• Start Point
– Clock input port
• End Point
– Clock pin of the flip-flop/latch/memory
(sequential cell)
•clock path the starts from the input port/pin of
the design which is specific for the Clock input
and the end point is the clock pin of a sequential
element. In between the Start point and the end
point there may be lots of Buffers/Inverters/clock
divider.
Clock Gating Path
• Start Point
– Input port of the design
• End Point
– Input port of clock-gating element
• Clock path may be passed trough a “gated element” to
achieve additional advantages. In this case, characteristics and
definitions of the clock change accordingly. We call this type
of clock path as “gated clock path”.
• LD pin is not a part of any clock but it is using for gating the
original CLK signal. Such type of paths are neither a part of
Clock path nor of Data Path because as per the Start Point and
End Point definition of these paths, its different. So such type
of paths are part of Clock gating path.
Asynchronous path
• Start Point
– Input Port of the design
• End Point
– Set/Reset/Clear pin of the flip-flop/latch/memory
(sequential cell)
• A path from an input port to an asynchronous set or
clear pin of a sequential element.
• the functionality of set/reset pin is independent from
the clock edge. Its level triggered pins and can start
functioning at any time of data. So in other way we
can say that this path is not in synchronous with the
rest of the circuit and that's the reason we are saying
such type of path an Asynchronous path.
Other types of Paths
• There are few more types of path which we usually use during
timing analysis reports. Those are subset of above mention
paths with some specific characteristics
• Critical path
• False Path
• Multi-cycle path
• Single Cycle path
• Launch Path
• Capture Path
• Longest Path ( also know as Worst Path , Late Path , Max Path ,
Maximum Delay Path )
• Shortest Path ( Also Know as Best Path , Early Path
Critical Path
• The path which creates Longest delay is the
critical path.
False path
• Physically exist in the design but those are
logically/functionally incorrect path. Means no
data is transferred from Start Point to End
Point.
Multi Cycle Path
• A multi cycle path is a timing path that is
designed to take more than one clock cycle for
the data to propagate from the start point to
the endpoint.
• When you are doing clock crossing from two closely
related clocks; ie. from a 30MHz clock to a 60MHz
clock,
– Assuming the two clocks are from the same clock source
(i.e. one is the divided clock of the other), and the two
clocks are in phase.
– The normal constraint in this case is from the rising edge of
the 30MHz clock to the nearest edge of the 60MHz clock,
which is 16ns later. However, if you have a signal in the
60MHz domain that indicates the phase of the 30MHz
clock, you can design a circuit that allows for the full 33ns
for the clock crossing, then the path from flop30 -> to
flop60 is a MCP .
– The generation of the signal 30MHZ_is_low is not trivial,
since it must come from a flop which is clocked by the
60MHz clock, but show the phase of the 30MHz clock.
Single Cycle Path:
• A Single-cycle path is a timing path that is
designed to take only one clock cycle for the
data to propagate from the start point to the
endpoint.
Launch Path and Capture Path
• When a flip flop to filp-
flop path such as UFF1
to UFF3 is considered,
one of the flip-flop
launches the data and
other captures the data.
So here UFF1 is referred
to "launch Flip-flop"
and UFF3 referred to
"capture flip-flop".
• The Name "Launch path"
referred to a part of clock
path. Launch path is launch
clock path which is
responsible for launching
the data at launch flip flop.
And Similarly Capture
path is also a part of clock
path. Capture path is
capture clock path which is
responsible for capturing
the data at capture flip
flop.
Arrival Time, Required time
•Launch path and data path together
constitute Arrival time of data at the input of
capture flip-flop.
•Capture clock period and its path delay
together constitute Required time of data at
the input of capture register.
Same clock path behave like Capture and Launch
path for different Data path
• Its very clear that
capture and launch
paths are correspond
to Data path. Means
same clock path can
be a launch path for
one data path and be
a capture path for
another data path.
Longest And Shortest Path
• Longest path is the one
that takes longest time,
this is also called worst
path or late path or a
max path.
• The shortest path is the
one that takes the
shortest time; this is
also called the best path
or early path or a min
path
SETUP & HOLD TIME
• An Input DIN and external
clock CLK are buffered and
passes through
combinational logic
before they reach a
synchronous input and a
clock input of a D flipflop
(positive edge triggered)
• Now to capture the data
correctly at D flip flop,
data should be present at
the time of positive edge
of clock signal at the C pin.
Setup time
• Tpd DIN > Tpd Clk
– For capture the data at the
same time when Clock
signal (positive clock edge)
reaches at pin C, you have to
apply the input Data at pin
DIN "Ts(in)=(Tpd DIN) - (Tpd
Clk)" time before the positive
clock edge at pin CLK.
– In other word, at DIN pin,
Data should be stable "Ts(in)"
time before the positive clock
edge at CLK pin.
– This Time "Ts(in)" is know as
Setup time of the System.
Hold Time
• Tpd DIN < Tpd Clk
– For capture the data at the
same time when clock signal
(positive clock edge)
reaches at pin C, input Data at
pin DIN should not change
before "Th(in)= (Tpd Clk) -
(Tpd DIN)" time. If it will
change, positive clock edge at
pin C will capture the next
data.
– In other word, at DIN
pin, Data should be stable
"Th(in)" time after the
positive clock edge at CLK pin.
– This time "Th(in)" is know as
Hold Time of the System.
•Worst case and best case (Max delay and min delay)
Because of environment condition or because of PVT, we
can do this analysis for the worst case ( max delay) and best
case ( min delay) also.

•Shortest Path or Longest path ( Min Delay and Max


delay)
If combinational logic has multiple paths, the we have to do
this analysis for the shortest path ( min delay) and longest
path ( max delay) also.
Equations for set up & Hold time

Tpd DIN (max) > Tpd Clk (min)


SetUp time == Tpd DIN (max) - Tpd Clk (min)
Tpd DIN (min) < Tpd Clk (max)
Hold time == Tpd Clk (max) - Tpd DIN (min)
For example: for combinational logic delays are
Data path (max, min) = (5ns, 4 ns)
Clock path (max, min) = (4.5ns, 4.1ns)
Then Setup time= 5-4.1=0.9ns
Hold time is = 4.5-4=0.5ns
Definitions for Setup & Hold time
Definition For setup time
• Setup Time:
• Setup time is the minimum amount of time the data
signal should be held steady before the clock event so
that the data are reliably sampled by the clock. This
applies to synchronous circuits such as the flip-flop.
• Or the amount of time the Synchronous input (D) must
be stable before the active edge of the Clock.
• The Time when input data is available and
stable before the clock pulse is applied is called Setup
time.
Definition for Hold time
• Hold time:
• Hold time is the minimum amount of time the
data signal should be held steady after the clock
event so that the data are reliably sampled. This
applies to synchronous circuits such as the flip-
flop.
• Or in short I can say that the amount of time the
synchronous input (D) must be stable after the
active edge of clock.
• The Time after clock pulse where data input is
held stable is called hold time.
Setup Violation
• If Setup time is Ts for a
flip-flop and if data is not
stable before Ts time from
active edge of the clock,
there is a Setup violation
at that flip flop. So if data
is changing in the non-
shaded area ( in the
figure) before active clock
edge, then it's a Setup
violation.
Hold Violation
• Hold time is Th for a flip
flop and if data is not
stable after Th time from
active edge of the clock ,
there is a hold violation at
that flip flop. So if data is
changing in the non-
shaded area ( in the
figure) after active clock
edge, then it's a Hold
violation.
Setup & hold violations w.r.t two flops
• Data is launching from FF1/D to FF1/Q at
the positive clock edge at FF1/C.

• At FF2/D , input data is coming from FF1/Q


through a combinational logic.

• Data is capturing at FF2/D, at the positive


clock edge at FF2/C.

• So I can say that Launching Flip-Flop is FF1


and Capturing Flip-Flop is FF2.

• So Data path is FF1/C --> FF1/Q --> FF2/D

• For a single cycle circuit- Signal has to be


propagate through Data path in one clock
cycle. Means if data is launched
at time=0ns from FF1 then it should be
captured at time=10ns by FF2.
Setup Analysis
• Setup analysis at FF2, Data should be
stable "Ts" time before the positive edge
at FF2/C. Where "Ts" is the Setup time of
FF2.
• If Ts=0ns, then , data launched from FF1
at time=0ns should arrive at D of FF2
before or at time=10ns. If data takes too
long ( greater then 10ns) to arrive (means
it is not stable before clock edge at FF2) ,
it is reported as Setup Violation.
• If Ts=1ns, then, data launched from FF1 at
time=0ns should arrive at D of FF2 before
or at time=(10ns-1ns)=9ns. If data takes
too long (greater then 9ns) to arrive
(means it is not stable before 1ns of clock
edge at FF2), it is reported as Setup
Violation.
Hold Analysis
• For Hold Analysis at FF2, Data should be stable
"Th" time after the positive edge at FF2/C.
Where "Th" is the Hold time of FF2. Means
there should not be any change in the Input
data at FF2/D between positive edge of clock at
FF2 at Time=10ns and Time=10ns+Th.
• To satisfy the Hold Condition at FF2 for the Data
launched by FF1 at 0ns, the data launched by
FF1 at 10ns should not reach at FF2/D before
10ns+Th time.
• If Th=0.5ns, then we can say that the data
launched from FF1 at time 10ns does not get
propagated so soon that it reaches at FF2
before time (10+0.5)=10.5ns ( Or say it should
reach from FF1 to FF2 with in 0.5ns). If data
arrive so soon (means with in 0.5ns from FF1 to
FF2, data can't be stable at FF2 for time=0.5ns
after the clock edge at FF2), its reported Hold
violation.
2Important points

• Setup is checked at next


clock edge.

• Hold is checked at same


clock edge.
Problem1: In the following Circuit, Find out whether there
is any Setup Or Hold Violation?
Hold Analysis
•When a hold check is performed, we
have to consider two things-
•Minimum Delay along the data path.
•Maximum Delay along the clock path.
•If the difference between the data
path and the clock path is negative,
then a timing violation has occurred.
Data Path
• Data path is: CLK->FF1/CLK -
>FF1/Q ->Inverter ->FF2/D

• Delay in Data path


• = min(wire delay to the
clock input of FF1) +
min(Clk-to-Q delay of FF1)
+min(cell delay of inverter)
+ min(2 wire delay- "Qof
FF1-to-inverter" and
"inverter-to-D of FF2")
• =Td = 1+9+6+(1+1)=18ns
Clock path Delay

• Clock path Delay= max(wire


delay from CLK to Buffer input)
+ max(cell delay of Buffer) +
max(wire delay from Buffer
output to FF2/CLK pin) + (hold
time of FF2)
• =Tclk = 3+9+3+2 = 17 ns
Hold violation
Hold Slack = Td - Tclk = 18ns -17ns = 1ns
Since Hold Slack is positive-> No hold
Violation.
Note: If the hold time had been 4 ns instead of 2 ns, then
there would have been a hold violation.
Td=18ns and Tclk = 3+9+3+4=19ns
So Hold Slack=Td - Tclk = 18ns - 19ns = -1ns
(Violation)
Setup Analysis
• When a setup check is performed, we have to
consider two things-
• Maximum Delay along the data path.
• Minimum Delay along the clock path.
• If the difference between the clock path and
the data path is negative, then a timing
violation has occurred.
Setup violation
• Data path is: CLK->FF1/CLK -
>FF1/Q ->Inverter ->FF2/D

• Delay in Data path


• = max(wire delay to the
clock input of FF1) +
max(Clk-to-Q delay of FF1)
+max(cell delay of inverter)
+ max(2 wire delay- "Qof
FF1-to-inverter" and
"inverter-to-D of FF2")
• =Td = 2+11+9+(2+2) = 26ns
• Note: The first part of the clock path delay
(during setup calculation) is the clock period,
which has been set to 15 ns. Setup is checked
at the next clock cycle. That's the reason for
clock path delay we have to include clock
period also.

Clock path delay
• Clock path Delay
• = (Clock period) +
min(wire delay from CLK
to Buffer input) + min(cell
delay of Buffer) + min(wire
delay from Buffer output
to FF2/CLK pin) - (Setup
time of FF2)
• =Tclk = 15+2+5+2-4=20ns
Setup violation
• Setup Slack = Tclk - Td = 20ns -
26ns = -6ns.
• Since Setup Slack is negative ->
Setup violation.
• Note: A bigger clock period or
a less maximum delay of the
inverter solve this setup
violations in the circuit.
• E.g
• If Clock period is 22ns then
• Tclk = 22+2+5+2-4=31-
4=27ns AND Td = 26ns
• Setup Slack = Tclk - Td = 27-
26=1ns (No Violation)
Problem2: In order to work correctly, what should be the Setup and Hold
time at Input A in the following Circuit. Also find out the maximum
operating frequency for this circuit. (Note: Ignore Wire delay).
Where Tsu- Setup time; Thd-Hold Time; Tc2q- Clock-to-Q delay
Maximum register to register delay
• Step1: Find out the maximum
Register to register Delay.

• Max Register to Register Delay


• = (clk-to-Q delay of U2) + (cell delay
of U3) + (all wire delay) + (setup
time of U1)
• = 5 + 8 + 3 = 16 ns.
• Note:
• There are 2 register to register
paths
– U2 -> U3 ->U1 (Delay=5+8+3=16ns)
– U1 -> U4 -> U2 ( Delay=5+7+3=15ns)
• We have to pick maximum one.

Setup time
Step2: Find Out Setup Time:A setup time = Setup time of
Flipflop + Max (Data path Delay) - min(Clock path Delay)
• = (Setup time of Flipflop + A2D max delay) - (Clk path min
delay)
• = Tsu + (Tpd U7 + Tpd U3 + wire delay) - Tpd U8
• = 3 + (1+8 ) - 2 = 10 ns
• Note:
• Here we are not using the Clock period. Because we are
not suppose to calculate the Setup violation. We are
calculating Setup time.
• All the wire dealy is neglected. If Wire delay present, we
have to consider those one.
• There are 2 Data path
– A -> U7 -> U4 -> D of U2 (Data path Delay = 1+7
=8ns )
– A -> U7 -> U3 -> D of U1 ( Data path Delay = 1+8
=9ns )
• Since for Setup calculation we need maximum Data path
delay, we have chosen 2nd for our calculation.
Hold time
• Step3: Find Out Hold Time:
• A hold time = Hold time of
Flipflop + max(Clock path
Delay) - min( Data path delay)
• =( Hold time of Flipflop + Clk
path max delay) - (A2D max
delay)
• = Thd + Tpd U8 - (Tpd U7 + Tpd
U4+wire delay)
• = 4 + 2 - (1+7 ) = -2 ns
• Note: Same explanation as for
Setup time. For hold time we
need minimum data path , so
we have picked first Data path.
Clk to out time
• Step4: Find out Clock to Out Time:
• Clock to Out
• = Cell delay of U8 + Clk-to-Q delay of
FlipFlop+ Cell delay of U5+ Cell delay
of U6+ (all wire delay)
• = Tpd U8+ U2 Tc2q + U5 Tpd + U6 Tpd
• = 2 + 5 + 9 + 6 = 22 ns
• Note:

• There are 2 Clock to Out path- one


from Flip flop U1 and other from U2.
• Since in this case the Clk-to-Q path for
both Flipflop is same, we can consider
any path. But in some other Circuit
where the delay is different for both
the paths, we should consider Max
delay path.
Pin to pin combinational delay
• Step5: Find Pin to Pine
Combinational Delay (A
to Y delay)

• Pin to Pin
Combinational Delay (A
to Y)
• = U7 Tpd + U5 Tpd + U6
Tpd
• = 1 + 9 + 6 = 16 ns
Max clock frequency
• Step5: Find Out Max
Clock Frequency:
• Max Clock Freq = 1/
Max (Reg2reg, Clk2Out,
Pin2Pin)
• = 1/ Max (16, 22, 16)
• = 45.5 Mhz
Points to remember
Setup is checked at next clock edge.
Hold is checked at same clock edge.
For Hold Check ( Checking of hold Violation)
Minimum Delay along the data path.
Maximum Delay along the clock path.
For SetUp Check ( Checking of Setup Violation)
Maximum Delay along the data path.
Minimum Delay along the clock path.
Setup Slack = Required time - Arrival time (since we want
data to arrive before it is required)
Hold Slack = Arrival Time - Required time (since we want
data to arrive after it is required)