S.

No Title of theProject Year LD/PD

1 Low Delay single symbol Error Correction code based on reed Solomon codes 2015 LD

2 An Efficient constant multiplier Architecture based on vertical-Horizontal binary common sub- 2015 LD
expression elimination algorithm for reconfigurable fir filter synthesis
3 Securing the Architecture of the JPEG Compression by an Dynamic Encryption 2015 LD

4 Reliable low-power multiplier design using fixed -width replica redundancy block 2015 LD

5 Low-power, serial interface for power-constrained devices 2015 LD

6 Aging- aware reliable multiplier design with adaptive hold logic 2015 LD

7 Scan test bandwidth management for ultra-large-scale system-on-chip architecture 2015 LD

8 Low-power and area-efficient shift register using pulsed latches 2015 LD

9 Fault tolerant parallel filter based on error correction codes 2015 LD

10 Efficient coding schemes for fault-tolerant parallel filters 2015 LD

11 Design and Verification of the AXI to OCP bridge 2015 LD

12 Design and Verification of OCP to AHB bridge 2015 LD

13 Design and verification of a PCI interface. 2015 LD

14 Design and verification of APB to OPB bridge. 2015 LD

15 Design and verification of APB to I2C interface 2015 LD

16 Design and Verification of APB to SPI interface 2015 LD

17 Design and Verification of 32 bit RISC processor based on ARM7 TDMI 2015 LD

18 Design and Verification of MAC unit based on VLIW architecture. 2014 LD

19 Design and verification of pipelined architecture of a RISC processor based on MIPS architecture. 2015 LD
20 FPGA based Implementation of Power Optimization of 32 Bit RISC Core using DLX Architecture 2015 LD

21 Design & Analysis of 16 bit RISC Processor Using low Power Pipelining 2015 LD

22 Advanced Low Power RISC Processor Design using MIPS Instruction Set 2015 LD

23 Design and Simulation of 32-Bit RISC Architecture Based on MIPS using VHDL 2015 LD
S.NO Title of the Project Year PD,LD

24 RTL implementation of ASB to APB bridge 2015 LD

25 Fast Sign Detection Algorithm for the RNS Module Set {2n+1 − 1, 2n − 1, 2n} 2015 LD

26 Fully Reused VLSI Architecture of FM0/ Manchester Encoding Using SOLS Technique for DSRC 2015 LD
Applications
27 FPGA Implementation of Efficient AES Encryption 2015 LD

28 A Review: Hardware Implementation of AES Using Minimal Resources on FPGA 2015 LD

29 High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC 2015 LD
implementations
30 Low-Power Programmable PRPG With Test Compression Capabilities 2015 LD

31 Median Filter Architecture by Accumulative Parallel Counters 2015 LD

32 Pre-Encoded Multipliers Based on Non-Redundant Radix-4Signed-Digit Encoding 2015 LD

33 A High-Performance On-Chip Bus (MSBUS) Design and Verification 2015 LD

34 A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable 2015 LD
Orthogonal Approximation of DCT
35 Optimized built in self repair for multiple memories 2015 LD

36 Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure 2015 PD

37 Detailed-Routing-Driven Analytical Standard-Cell Placement 2015 PD

38 Fast Synthesis of Low Power Clock Trees Based on Register Clustering 2015 PD

39 Power Efficient High Level Synthesis by Centralized and Fine-Grained Clock Gating 2015 PD

40 A Survey on VLSI Floor planning: Its Representation and Modern Approaches of Optimization 2015 PD

41 Data Encoding Techniques for Reduction Energy Consumption in Network-on -chip 2014 LD
42 An Optimized Modified Booth Re coder for Efficient Design of the Add-Multiply Operator 2014 LD
43 Design and estimation of delay, power and area for Parallel prefix adders 2014 LD
44 Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter 2014 LD
Implementation
45 An approach for efficient FIR filter design for hearing aid application 2014 LD
46 Area–Delay–Power Efficient Carry-Select Adder 2014 LD
47 Design of High Performance 64 bit MAC Unit 2014 LD
48 Implementation of on chip permutation network for Multiprocessor System on a Chip 2013 LD

49 Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check 2013 LD
(EG-LDPC) Codes
50 An Area Efficient Carry select Adder Design by Sharing the Common Boolean logic Term 2013 LD
51 New modified Reconfigurable Architectures for Implementing FIR Filters with Low Complexity 2013 LD
52 A Configurable Bus-Tracer for Error Reproduction in Post Silicon Validation 2013 LD
53 An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write- 2013 LD
Through Policy
54 A Configurable Bus-Tracer for Error Reproduction in Post-Silicon Validation 2013 LD
55 Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast 2013 LD
FIR Algorithm