Beruflich Dokumente
Kultur Dokumente
17ECL38
Dept. OF ECE
CITY ENGINEERING COLLEGE
IC Pin Configurations 2
4. Comparator circuits 16
7. Flip-Flop verification 26
8. Shift Registers 29
A B ̅̅̅̅̅̅̅̅
𝐴 + 𝐵 𝐴. ̅ 𝐵̅
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0
A B ̅̅̅̅̅
𝐴. 𝐵 𝐴̅ + 𝐵̅
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0
Aim: – To Simplify and Realize Boolean expressions using logic gates/Universal gates.
Components Required: - IC 7408 (AND), IC 7404 (NOT), IC 7432 (OR),IC 7400 (NAND), IC
7402 (NOR),IC 7486 (EX-OR)
Procedure :
C 1
7408 3
2 1
3
B 7432 Y=BC+BD
4 2
7408 6
D 5
B 1
7408 3 Y=B(C+D)
1
C 7432
3 2
D 2
Realization using only NAND gates: Realization using only NOR gates:
2
C 1
B 7402 1 5
7400 3
3 7402 4 Y=B(C+D)
2 9 6
8
B 7400 Y=BC+BD
8
4
6
10 C 7402 10
7400
D 5 D 9
11 1
B 7400
13
7400' 3 Y=B(C+D)
1 2
12
C 7400 3 9
8
2 7400
10
4
6
D 7400
5
Aim: – To realize half/full adder and half/full subtractor using Logic gates
Procedure: -
1. Verify that the gates are working.
2. Make the connections as per the circuit diagram for the half adder circuit, on the trainer kit.
3. Switch on the VCC power supply and apply the various combinations of the inputs according
to the respective truth tables.
4. Note down the output readings for the half adder circuit for the corresponding combination of
inputs.
5. Verify that the outputs are according to the expected results.
6. Repeat the procedure for the full adder circuit, the half subtractor and full subtractor circuits.
7. Verify that the sum/difference and carry/borrow bits are according to the expected values.
TRUTH TABLE
C
A B Cn-1 S
0
0 0 0 0
0
0 0 1 1
0
0 1 0 1
1
0 1 1 0
0
1 0 0 1
1
1 0 1 0
1
1 1 0 0
1
1 1 1 1
A B D B
0 0 0 0
0 1 1 1
C 1 0 1 0
1 1 0 0
B
A B Cn-1 D
0
0 0 0 0
1
0 0 1 1
1
0 1 0 1
1
0 1 1 0
0
1 0 0 1
0
1 0 1 0
0
1 1 0 0
1
1 1 1 1
Experiment No. 3
Aim: –i. To realize Parallel Adder and Subtractor Circuits using IC 7483
ii. BCD to Excess-3 Code conversion and Vice Versa using IC7483
Procedure: -
1. Connect one set of inputs from A0 to A3 pins and the other set from B0 to B3, on the IC
7483.
3. Connect the pins from S0 to S3 to output terminals. Connect C4 to the Carry Output pin.
4. In order to implement the IC 7483 as a subtractor, first connect C0 to VCC, Apply the B
5. Apply the inputs to the adder/ subtractor circuits as shown in the truth tables.
6. Check the outputs and note them down in the table for the corresponding inputs.
7483
Truth Table:-
A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 S3 S2 S1
1 0 0 0 0 0 1 0 0 1 0 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0
1 0 1 0 1 0 1 1 1 0 1 0 1
Truth Table:
Subtraction
Input Data A Input Data B
A4 A3 A2 A1 B4 B3 B2 B1 S4 S3 S2 S1
1 0 0 0 0 0 1 0 0 1 1 0
1 0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 0 1 0
0 0 0 1 0 1 1 1 1 0 1 0
1 0 1 0 1 0 1 1 1 1 1 1
0 1 1 0 0 0 1 1 0 0 1 1
1 1 1 0 1 1 1 1 1 1 1 1
1 0 1 0 1 1 0 1 1 1 0 1
Example
Difference, S4 S3 S2 S1 = 0110
2's complement method of subtraction can be performed,if S=1(i.e. C0=1).
.
_A4 _A3 _A2_A1= 1001
2’s Complement
B4 B3 B2 B1= 1100→(1's complement) of +3 = 0011
of
+1 ←C0=1(S&C0 shorted) B input = -B
+1 ← C0=1(S&C0 shorted)
Experiment No. 4
Aim: – To verify the truth tables for5 bit comparator usingIC 7485.
Procedure –
A. Comparators Using Logic Gates:
1.Verify the working of the logic gates.
2.Make the connections as per the respective circuit diagrams.
3.Switch on Vcc.
4.Apply the inputs as per the truth tables.
5.Check the outputs and verify that they are according to the truth tables.
B. Study of IC 7485:
1.Write the truth table for an 5-bit comparator.
2. Connect pin 16 to Vcc and pin 8 to GND for the ICs.
3.Apply the two inputs as shown; making sure that the MSB and LSB is correctly connected.
4. Outputs are recorded at pin 2 (A<B), pin 4 (A>B), pin 3 (A=B) pins and are verified as
being according to the truth table.
A. One-Bit Comparator:
Circuit : Truth Table: 1bit Comparator
Inputs Outputs
A B A>B A=B A<B
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
X=B
X4 X3 X2 X1 X0 Y4 Y3 Y2 Y1 Y0 X>Y X<Y
0 0 0
0 0 0 0 0 0 0 1 0 1
0 0 0
0 1 0 1 0 0 1 1 1 0
0 0 1
1 0 1 0 1 0 1 0 0 0
0 1 0
0 0 1 1 0 1 1 0 0 1
Experiment No. 5
MULTIPLEXER
Aim: To study a 4:1multiplexer ,also realize the function using IC 74151(8:1mux)
Components required :7411,7432,7404,IC 74151
A: Half Adder Using 74153 Half Subtractor using 74153
Truth Table:
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 0 1 0
1 1 0 1 0 0
B.3 VARIABLE FUNCTION USING IC 74151(8:1 MUX)- Full adder using IC 74151
Procedure:
1. Test all IC’s .Set up the circuit and give a 4 bit binary combination at D0 through D3
2. Feed all eight combinations at A,B,C one by one, observe corresponding output and verify that it
functions as a multiplexer.
Experiment No. 6
DEMULTIPLEXER
Aim: To study and implement the function using decoder IC 74139
Components required :,IC 74139,IC 7420
1. The Pin [16] is connected to + Vcc and Pin [8] is connected to ground.
2. The inputs are applied either to ‘A’ input or ‘B’ input.
3. If DEMUX ‘A’ has to be initialized, EA is made low and if DEMUX ‘B’ has to be
initialized, EB is made low.
4. Based on the selection lines one of the inputs will be selected at the set of
outputs, and thus the truth table is verified.
5. In case of half adder using DEMUX,Ea is set to 0, the corresponding values of
select input lines, A and B (S1a and S0a) are changed as per table and the output
is taken at Sum and Carry. Verify outputs.
6. In case of Half Subtractor, connections are made according to the circuit,
Inputs are applied at A and B as shown, and outputs are taken at
Differenceand Borrow. Verify outputs.
7. In full adder using DEMUX, the inputs are applied at Cn-1, An and Bn according
to the truth table. The corresponding outputs are taken at Sum and Carry, and
are verified according to the truth table.
8. In full subtractor using DEMUX, the inputs are applied at Cn-1, An and Bn
according to the truth table. The corresponding outputs are taken at Difference
and Borrow as shown, and are verified according to the truth table.
Truth Tables:
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 0 1 0
1 1 0 1 0 0
Experiment No.7
S R Qn+1
0 X X Qn
1 0 0 Qn
1 0 1 0(reset)
1 1 0 1(set)
1 1 1 indeterminate
Circuit:
Truth Table :
0 1 X X X 1 0 Set
1 0 X X X 0 1 Reset
1 1 0 0 𝑸𝒏 ̅̅̅̅
𝑸𝒏 No Change
1 1 0 1 0 1 Reset
1 1 1 0 1 0 Set
1 1 1 1 ̅̅̅̅
𝑸 𝑸𝒏 Toggle
𝒏
Circuit:
Truth Table :
̅̅̅̅̅̅̅
𝑸𝒏+𝟏
Preset Clear T Clock 𝑸𝒏+𝟏
̅̅̅̅
𝑸𝒏
1 1 0 𝑸𝒏
̅̅̅̅
𝑸𝒏 𝑸𝒏
1 1 1
Circuit:
Truth Table:
̅̅̅̅̅̅̅
𝑸𝒏+𝟏
Preset Clear D Clock 𝑸𝒏+𝟏
1
1 1 0 0
0
1 1 1 1
Experiment No.8
SHIFT REGISTERS
Aim: – To study IC 74S95, and the realization of Shift left, Shift right, SIPO, SISO, PISO, PIPO,
ring counter and a Johnson Counter operations using the same.
Procedure: -
A. Serial In-Parallel Out (Left Shift):
1. Make the connections as shown in the respective circuit diagram.
2. Make sure the 7495 is operating in Parallel mode by ensuring Pin 6 (Mode M) is set to
HIGH, and connect clock input to Pin 8 (Clk 2).
3. Apply the first data at pin 5 (D) and apply one clock pulse. We observe that this data
appears at pin 10 (QD).
4. Now, apply the second data at D. Apply a clock pulse. We now observe that the earlier
data is shifted from QD to QC, and the new data appears at QD.
5. Repeat the earlier step to enter data, until all bits are entered one by one.
6. At the end of the 4th clock pulse, we notice that all 4 bits are available at the parallel
output pins QA (MSB), QB, QC, QD (LSB).
7. Enter more bits to see there is a left shifting of bits with each succeeding clock pulse.
B. Serial In-Parallel Out (Right Shift):
1. Make the connections as shown in the respective circuit diagram.
2. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode M) is set to
LOW, and connect clock input to Pin 9 (Clk 1).
3. Apply the first data at pin 1 (SD1) and apply one clock pulse. We observe that this data
appears at pin 13 (QA).
4. Now, apply the second data at SD1. Apply a clock pulse. We now observe that the earlier
data is shifted from QA to QB, and the new data appears at QA.
5. Repeat the earlier step to enter data, until all bits are entered one by one.
6. At the end of the 4th clock pulse, we notice that all 4 bits are available at the parallel
output pins QA through QD.
7. Enter more bits to see there is a right shifting of bits with each succeeding clock pulse.
C. Serial In-Serial Out Mode:
1. Connections are made as shown in the SISO circuit diagram.
Serial D
Clock QA QB QC QD
I/P
1 1 X X X 1 1
1
VCC 2 0 X X 1 0 0
Clock I/P
3 1 X 1 0 1 1
1
4 1 1 0 1 1 1
Serial QD
Clock SDI QA QB QC
I/P
1 1 1 1 X X X
Clock 2 0 0 1 X X
0
I/P
VCC 3 1 1 0 1 X
0 1
4 1 1 1 0 1
1
Serial
Clock SDI QA QB QC QD
I/P
1 d0=0 0 0 X X X
2 d1=1 1 1 0 X X
Clock 3 d2=1 1 1 1 0 X
I/P 4 d3=1 0
VCC 1 1 1 1
5 X X X 1 1 1
00
6 X X X X 1 1
7 X X X X X 1
D. PISO Mode
A B C D QA QB QC QD
1 1 1 0 1 1 1 0 1 1
Clock
I/P 1
0 2 X X X X X 1 0
0 3 X X X X X X 1 0
0 4 X X X X X X X 1
A B C D QA QB QC QD
1 1 0 1 1 1 0 1 1
Mode Clock QA QB QC QD
1 1 1 0 0 0
0 2 0 1 0 0
0 3 0 0 1 0
0 4 0 0 0 1
0 5 1 0 0 0
0 6 0 1 0 0
F.Johnson Counter
Mode Clock QA QB QC QD
1 1 1 0 0 0
0 2 1 1 0 0
Parallel I/P 0 3 1 1 1 0
Data
0 4 1 1 1 1
0 5 0 1 1 1
0 6 0 0 1 1
0 7 0 0 0 1
0 8 0 0 0 0
0 9 1 0 0 0
0 10 1 1 0 0
USING IC 7474
SISO
SIPO
PISO
Experiment No.09
A.MOD –N COUNTER USING IC 7490
Aim: – Realization of mod N counter using IC 7490
Components Required: IC 7490,IC 7408
Procedure: -
1. Make the connections as shown in the respective circuit diagrams.
2. Clock inputs are applied one by one at the clock I/P, and the outputs are observed at
QA, QB, QC and QD pins of the 7490 ICs.
3. Verify that the circuit outputs match those indicated by the truth tables.
a. Decade Counter
Truth Table:
Clock QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0
b. Mod-8 Counter
Circuit:
Truth Table:
Clock QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 0 0 0 0
9 0 0 0 1
Truth Table:
Clock QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 0 0 0
0 Q0
0 Q1
1 Q2
1 Q3
3 1
5
4 2
0
6
Truth Table:
QD QC QB QA Decimal
Clock
0 1 1 0 0 12
1 1 0 1 1 11
2 1 0 1 0 10
3 1 0 0 1 9
4 1 0 0 0 8
5 0 1 1 1 7
6 0 1 1 0 6
7 0 1 0 1 5
8 1 1 0 0 12
9 1 0 1 1 11
Experiment No. 10
SEQUENCE GENERATOR
Theory: -
In order to generate a sequence of length ‘S’, it is necessary to use at least‘N’ number of Flip-flops,
in order to satisfy the condition 𝑆 ≤ 2𝑁 − 1.
Note: There is no guarantee that the given sequence can be generated by 4 flip-flops. If the sequence
is not realizable by 4 flip-flops, we need to use 5 flip-flops, and so on.
Procedure:-
1. Truth table is constructed for the given sequence, and Karnaugh maps are drawn in order to
obtain a simplified Boolean expression for the circuit.
2. Connections are made as shown in the circuit diagram.
3. Mode M is set to LOW (0), and clock pulses are fed through Clk 1 (pin 9).
4. Clock pulses are applied at CLK 1 and the output values are noted, and checked against the
expected values from the truth table.
5. The functioning of the circuit as a sequence generator is verified.
Not
Connected
Clock I/P
VCC
O/p
Map
Clock QA QB QC QD
Value
D
15 1 1 1 1 1 0
7 2 0 1 1 1 0
3 3 0 0 1 1 0
1 4 0 0 0 1 1
8 5 1 0 0 0 0
4 6 0 1 0 0 0 𝐷 = 𝑄𝐶 𝑄𝐷 + 𝑄𝐶 𝑄𝐷
2 7 0 0 1 0 1
9 8 1 0 0 1 1
12 9 1 1 0 0 0
6 10 0 1 1 0 1
11 11 1 0 1 1 0
5 12 0 1 0 1 1
10 13 1 0 1 0 1
13 14 1 1 0 1 1
14 15 1 1 1 0 1
1 1 1
1 1
1
PART B
Experiment No.11
FULL ADDER
Aim: – Simulate full adder using simulation tool
Tool used: Modelsim
Circuit:
TRUTH TABLE
C
A B Cn-1 S
0
0 0 0 0
0
0 0 1 1
0
0 1 0 1
1
0 1 1 0
0
1 0 0 1
1
1 0 1 0
1
1 1 0 0
1
1 1 1 1
Counter States
Present state Next state JK FF input
M Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 1 0 x 0 x 1 x
0 0 0 1 0 1 0 0 x 1 x x 1
0 0 1 0 0 1 1 0 x x 0 1 x
0 0 1 1 1 0 0 1 x x 1 x 1
0 1 0 0 1 0 1 x 0 0 x 1 x
0 1 0 1 1 1 0 x 0 1 x x 1
0 1 1 0 1 1 1 x 0 x 0 1 x
0 1 1 1 1 1 1 x 1 x 1 x 1
1 1 1 1 1 1 0 x 0 x 0 x 1
1 1 1 0 1 0 1 x 0 x 1 1 x
1 1 0 1 1 0 0 x 0 0 x x 1
1 1 0 0 0 1 1 x 1 1 x 1 x
1 0 1 1 0 1 0 1 x x 0 x 1
1 0 1 0 0 0 1 1 x x 1 1 x
1 0 0 1 0 0 0 1 x 0 x x 1
1 0 0 0 1 1 1 1 x 1 x 1 x
From the direct inspection of the truth table ,we get J0=K0=1