CS/EE 260 - Homework 4 Solutions

Spring 1999

1. (MK 3-1) Determine the Boolean functions for outputs X and Y as a function
of the four inputs in the circuit in Figure 3-52.

D T1
T4
X
C T5
B T2
Y
A T3

T1 = D’ T2= BC T3 = (T1+A)’= A’D

T4 = (T1⋅T3)’= T1’+T3’= D + (A’D)’= D + A + D’= 1
T5 = T1 + T2 = D’+ BC

X = T4T5 = T5= D’+ BC Y = T3 ⋅T5 = A’D(D’+BC) = A’BCD

2. (MK 3-2) Obtain the truth table for the circuit shown in Figure 3-53. Draw an
equivalent circuit for F with fewer NAND gates.

X T2
T1 T4
T3
Y F

T5
Z

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 XYZ T1=(XY)’ T2=(XT1)’ T3=(T1Y)’ T4=(T2T3Z)’ T5=(T3Z)’ F=(T4T5)’
000 1 1 1 1 1 0
001 1 1 1 0 0 1
010 1 1 0 1 1 0
011 1 1 0 1 1 0
100 1 0 1 1 1 0
101 1 0 1 1 0 1
110 0 1 1 1 1 0
111 0 1 1 0 0 1

Equivalent X
Circuit Z

3. (MK 3-4) Find the simplified Boolean functions for outputs F and G of the
circuit in Figure 3-55.

A
F
B T4
T1
G
T2 T5
C T6
T3
D
T1 = (ABD)’ T2= (AC)’ T3 = (BCD)’
T4 = (AT1T2)’= A’+ABD +AC = A’+ BD+C = F
T5 = (T1BT3)’= AD +B’+CD T6 = (T2T3C)’= A+BD +C’
G = (T4T5T6)’= A(B’+D’)C’ + (A’+D’)B(C’+D’) + A’(B’+D’)C
= AB’C’+A’BC’+A’B’C + BD

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4. (MK 3-5) Find the truth table for F and G of the circuit in Figure 3-55 by using
logic simulation.

inputs outputs
ABCD FG
0000 10
0001 10
0010 11
0011 11
0100 11
0101 11
0110 11
0111 10
1000 01
1001 01
1010 10
1011 10
1100 01
1101 10
1110 11
1111 10

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5. (MK 3-7) Find the truth table for the outputs F and G of the hierarchical
circuit in Figure 3-57. The symbol shown is for the decoder block in Figure 3-
14.

XYZ F G
0000 1 1
0001 1 1
0010 1 0
0011 1 0
0100 1 1
0101 1 1
0110 1 0
0111 1 0
1000 0 0
1001 0 1
1010 0 0
1011 0 1
1100 0 0
1101 0 1
1110 0 0
1111 0 1

6. (MK 3-10) A majority function is generated in a combinational circuit when

the output is equal to 1 if the input variables have more 1’s than 0’s. The
output is 0 otherwise. Design a 3-input majority function. What circuit that
you are familiar with does this circuit correspond to?

A
B

C M=AB+AC+BC

This is the same function implemented by the carry output of the full adder.

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7. (MK 3-12) Complete the design of the BCD-to-seven-segment decoder by
performing the following steps.
(a) Plot the seven maps for the outputs, specified in Table 3-3.
(b) Simplify the seven output functions in sum of products form, and
determine the total number of gates that will be needed to implement the
decoder.
(c) Verify that the seven output functions listed in the text give a valid
simplification. Compare the number of gates with that obtained in (b).

CD
00 01 11 10
a 00 1 0 1 1
01 0 1 1 1 a = AB′
C′+ B′
C′D’+ A′
BD + A′
C
AB
11 0 0 0 0
10 1 1 0 0

CD
00 01 11 10
b 00 1 1 1 1
01 1 0 1 0 b = A′
B′+ B′
C′+ A′
C′D′+ A′
CD
AB
11 0 0 0 0
10 1 1 0 0

CD
00 01 11 10
c 00 1 1 1 0
01 1 1 1 1 c = A′
B + B′
C′+ A′
D
AB
11 0 0 0 0
10 1 1 0 0

CD
00 01 11 10
d 00 1 0 1 1
01 0 1 0 1 d = B′
C′D′+AB′
C′+A′
BC′
D + A′
B′C + A′
CD′
AB
11 0 0 0 0
10 1 1 0 0

CD
00 01 11 10
e 00 1 0 0 1
01 0 0 0 1 e = B′
C′D′+ A′
CD′
AB
11 0 0 0 0
10 1 0 0 0

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 CD
00 01 11 10
f 00 1 0 0 0
01 1 1 0 1 f = B′
C′D′+AB′
C′+A′
BD′+ A′
BC′
AB
11 0 0 0 0
10 1 1 0 0

CD
00 01 11 10
g 00 0 0 1 1
01 1 1 0 1 g = A′ C ′+A′
BC′+AB′ B′C + A′
CD′
AB
11 0 0 0 0
10 1 1 0 0

(b) The sum of products expressions are given with the maps above.

If each expression is implemented separately, then

for a we have 4 ANDs plus 1 OR

for b we have 4 ANDs plus 1 OR
for c we have 3 ANDs plus 1 OR
for d we have 5 ANDs plus 1 OR
for e we have 2 ANDs plus 1 OR
for f we have 4 ANDs plus 1 OR
for g we have 4 ANDs plus 1 OR
this gives a total of 26 ANDs and 7 ORs

By sharing gates for common product terms, we can save some gates.

C′ appears 2 times, save 1 AND

AB′
B′
C′D′ appears 4 times, save 3 ANDs
BD appears 1 time, save 0 ANDs
A′
A′
C appears 1 time, save 0 ANDs
B′ appears 2 times, save 1 AND
A′
C′ appears 2 times, save 1 AND
B′
A′
C′D′ appears 1 time, save 0 ANDs
CD appears 1 time, save 0 ANDs
A′
A′
D appears 1 time, save 0 ANDs
A′
BC′D appears 1 time, save 0 ANDs
A′
B′C appears 2 times, save 1 AND
CD′ appears 3 times, save 2 ANDs
A′
BD′ appears 1 time, save 0 ANDs
A′
BC ′ appears 2 times, save 1 AND
A′

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So, we get an overall savings of 16 AND gates and 7 OR gates, of 23 altogether.

(c) The number of gates obtained in (b) is two more than in the textbook design.
Even though the book uses more product terms for some expressions, there
appears to be more overlap in the terms they use, allowing for an overall
savings of two gates.

Verification of textbook vs. solution here.

textbook derived above

a: A′
C ’+ A′BD + B′C′D + AB′C′ AB′
C′+ B′ C′D’+ A′BD + A′
C
b: A′
B′+ A′C′ D′+ A′CD + AB′C′ A′
B′+ B′C′+ A′ C′D′+ A′
CD
c: A′
B + A′D + B′C′D′+ AB′C′ A′
B + B′C′+ A′D
d: A′
CD′+ A′ B′C+B′C′D′+AB′C′+A′
BC′
D
B′ C′
D′+AB′C′ +A′BC′D+A′ B′
C+A′CD′
CD′+ B′
e: A′ C′D′ B′
C′D′+ A′
CD′
BC′+A′
f: A′ C′D′+A′ BD′+ AB′C′ B′
C′D′+AB′
C′+A′BD′+ A′ BC′
g: A′
CD′+ A′ B′C+ A′BC′+AB′ C′ A′
BC′+AB′C ′+A′
B′C + A′
CD′

We can see that in most cases (a,d,e,g) the expressions are identical, except for
the order of the terms. For b, the textbook expression has the term AB′ C′
while the solution derived above has the term B′ C′ . Since the term A′ C′is
B′
covered by the term A′ B′in the textbook expression, the two expressions are
equivalent. This can also be verified by examining the Karnaugh map for b,
above. For c, we can see that each term in the textbook expression is covered
by a term in the expression derived above. The term B′ C′on the right, does
not appear in the textbook expression, but it’s easy to see that all four
minterms covered by B′ C′are covered by the textbook expression. For f, the
difference between the two solutions is that the textbook expression includes
the term A′C′ D′where the expression derived above has B′ C′ D′. Since both
minterms covered by A′ C′D′are also covered by terms on the right, and since
both minterms covered by B′ C′D′are covered by terms on the left, the two
expressions are equivalent. This can also be seen by inspection of the
Karnaugh map for f.

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8. (MK 3-16) Design an excess 3 to BCD code converter, requiring that all
invalid input combinations give 0000 as the output code.
CD
inputs outputs 00 01 11 10
ABCD WXYZ W 00 0 0 0 0
0000 0000 01 0 0 0 0 W = ABC′
D′+ AB′
CD
AB
0001 0000 11 1 0 0 0
0010 0000 10 0 0 1 0
0011 0000
0100 0001 CD
0101 0010 00 01 11 10
0110 0011 X 00 0 0 0 0
0111 0100 01 0 0 1 0 X = A′ C ′+ AB′
BCD + AB′ D′
1000 0101 AB
11 0 0 0 0
1001 0110 10 1 1 0 1
1010 0111
1011 1000 CD
1100 1001 00 01 11 10
1101 0000 Y 00 0 0 0 0
1110 0000 C′
Y = AB′ D +AB′
CD′+
01 0 1 0 1 BC ′
A′ D +A′
BCD′
1111 0000 AB
11 0 0 0 0
10 0 1 0 1

CD
00 01 11 10
Z 00 0 0 0 0
01 1 0 0 1 Z = AB′
D′+A′ +AC ′
BD′ D′
AB
11 1 0 0 0
10 1 0 0 1

There are 12 product terms, only one of which is a repeat. So, the
implementation requires 11 AND gates and 4 OR gates, plus 4 inverters.

The schematic and simulation output are shown below.

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-9-
9. (MK 3-17) A combinational circuit is defined by the folloowing three
Boolean functions.

F1 = (X+Y)′+ XYZ′
F2 = (X+Y)′+ X′
YZ
F3 = XYZ + (X+Y)′

Design the circuit with a decoder and external OR gates.

XYZ F1 F2 F3
000
001
1
1
1
1
1
1
0
1
. F1
010 0 0 0 X
Y
4
2 3→ 8
2
3 . F2
011 0 1 0 Z 1
4
5
100 0 0 0 6
F3
101 0 0 0 7
110 1 0 0
111 0 0 1

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