Computer Organization and Architecture

Prasun Ghosal

€ Operational code / opcode € Instruction fetch € Running state

€ Instruction decode € Halt state
€ Opcode + operand / address € Operand fetch ƒ Software halt
€ Execute ƒ Halt input
ƒ Auto shutdown
€ Opcode + I operand / address +II operand / € Store the result
address
€ Accumulator (AC) € Frequency € Every instruction specifies a macro operation
€ Program Counter (PC) € Time period to be performed by the CPU
€ Memory address register (MAR) € Duty cycle € Opcode

€ Memory buffer register (MBR) € Instruction set

€ Instruction register (IR) €A clock signal has a frequency of 5 GHz with

€ General purpose register (GPR)
€ I/O data register (IODR)
€ I/O address register (IOAR)
a duty cycle of 40%. Calculate its period and € Toexecute an instruction CPU has to perform
pulse width. several micro operations.
ƒ Clearing a register, incrementing a counter etc.

€ Anevent inside a computer system requiring € External € Nested interrupts

some urgent action by the CPU ƒ External hardware error € Interrupt priority
ƒ CPU suspends the current program execution ƒ IO interrupt € Interrupt masking
ƒ Branches to an ISR ƒ NMI
€ Non-maskable interrupt
€ Common types | Data transfer
ƒ Power fail
| End of I/O
ƒ I/O completion ƒ Memory parity error
ƒ Data transfer € Internal
ƒ Bus cycle malfunction
ƒ Overflow ƒ Hardware
| Error in CPU hardware
| Program exceptions (overflow, illegal opcode etc.)
ƒ Software (INT instruction)
€ Data transfer € Instructionfrom memory to CPU €A single CPU multiplexes among multiple
ƒ Through CPU (SW) € Data from memory to CPU programs executing them concurrently; all
| Programmed mode
€ Data from CPU to memory
programs stay in a common memory
| Interrupt mode
€ Memory address from CPU to memory
ƒ Bypassing CPU (HW)
| DMA mode € Port address from CPU to I/O controllers
€ Command from CPU to I/O controllers
€ Status from I/O controllers to CPU

€ Morethan one CPU in a single system with

each CPU executing a different program;
each CPU may have a separate memory or all
CPUs may share a common memory