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##OnMainBoard
Block Diagram SYSTEM DC/DC
INPUTS
TPS51461
OUTPUTS
48
CPU DC/DC
TPS51640RSLR
INPUTS OUTPUTS
42~44

(UMA/Optimus co-lay) DCBATOUT

SYSTEM DC/DC
VCCSA DCBATOUT

SYSTEM DC/DC
VCC_CORE

VRAM TPS51211 45 G977F 45

D
2GB/1GB/512MB 4 Project code : 91.4SG01.001 INPUTS OUTPUTS INPUTS OUTPUTS D
88,89,90,91
PCB P/N : DCBATOUT 1D05V_S0 DCBATOUT 1D0V_S0

DDR3 Revision : SYSTEM DC/DC


TPS51123 41
900MHz Intel CPU INPUTS OUTPUTS
5V_AUX_S5
3D3V_AUX_S5
DCBATOUT 5V_S5
IVY Bridge DDRIII 1600/1333/1066 Channel A DDRIII Slot 0 3D3V_S5
NVIDIA PCIe x 16 1600/1333/1066 14
N13P-GL (Discrete only) SYSTEM DC/DC
DDRIII 1600/1333/1066 Channel B DDRIII Slot 1 RT8207 46
N13M-GE
1600/1333/1066 15 INPUTS OUTPUTS
1D5V_S3
4,5,6,7,8,9,10 DCBATOUT 0D75V_S0
83.84,85,86,87 DDR_VREF_S3

GFX DC/DC
HDMI 1.451 FDI x 4 x 2 TPS51640RSLR 42~44
(UMA only) DMI x 4
C
INPUTS OUTPUTS C

HDMI
10/100/1000M LAN DCBATOUT VCC_GFXCORE
LCD 14"/15"
49 RJ45
LVDS
PCIE x 1
AR8161/AR8162 CONN 59 VGA
31 92
Intel ISL62882C
CRT 50 RGB CRT INPUTS OUTPUTS
PCH PCIE x 1/USB2.0 x 1 Mini-Card DCBATOUT VGA_CORE

Bluetooth 63
USB2.0 x 2 Panther Point WLAN/WiMAX 65 CHARGER
BQ24745 40
USB 3.0/2.0 ports (14) USB3_TX/USB3_RX x 2 USB3_TX/RX x 2 INPUTS OUTPUTS
CAMERA 49
USB3 controller AD+
ETHERNET (10/100/1000Mb)
UPD720202K8 BT+ DCBATOUT
High Definition Audio
USB3.0 x 2
26
SATA ports (6) USB 2.0 x 2 USB 2.0 x 2 35 SYSTEM DC/DC
RT9025 47
PCIE ports (8)
INPUTS OUTPUTS
CardReader LPC I/F
USB 2.0 x 1 PCIE x 1
B SD/MMC+ AU6435 ACPI 1.1 3D3V_S5 1D8V_S0 B

74
VGA switchs 93
USB 2.0 x 2 USB2.0 x 2
INPUTS OUTPUTS
17,18,19,20,21,22,23,24,25 26
AZALIA 1D5V_S3 1D5V_VGA_S0
SATA x 2 HDD 3D3V_S0 3D3V_VGA_S0
56 1D05V_VTT 1D05V_VGA_S0
Switches
SPI

ODD INPUTS OUTPUTS


LPC Bus

Internal AMIC Azalia 56 1D5V_S3 1D5V_S0


CODEC 5V_S5 5V_S0
3D3V_S5 3D3V_S0
Combo Jack Flash ROM LPC debug port
Codec_ALC269Q
8MB 60 71
PCB LAYER
29
L1:Top L4:Signal
KBC SMBus
L2:VCC L5:GND
Fan NUVOTON L3:Signal L6:Bottom
A BOM A
28
NPCE885P 27
2CH SPEAKER Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

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Title
Touch Int. Thermal Block Diagram
Size Document Number Rev
PAD KB EMC1423 A3 LG4858_UMA
69 69 2528
-1
Date: Friday, March 16, 2012 Sheet 2 of 103
5 4 3 2 1
5 4 3 2 1

PCH Strapping Huron River Schematic Checklist Rev.0_7 Processor Strapping Huron River Schematic Checklist Rev.0_7
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ CFG[2] PCI-Express Static 1: Normal Operation.
- 10-kΩ weak pull-up resistor. Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
Lane Reversal 0:
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
Disabled - No Physical Display Port attached to
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. CFG[4] 1: Embedded DisplayPort.
D GNT2#/GPIO53 Mobile: Used as GPIO only 0 D

GNT1#/GPIO51 Pull-up resistors are not required on these signals. Enabled - An external Display Port device is
0: connectd to the EMBEDDED display Port
If pull-ups are used, they should be tied to the Vcc3_3power rail.
CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Port Bifurcation 10 : x8, x8 - Device 1 function 1 enabled ;
SPI_MOSI function 2 disabled
Straps 11
Disable Danbury:Left floating, no pull-down required. 01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm enabled
weak pull-up resistor [CRB has it pulled up
NV_ALE with 1-kohm no-stuff resistor] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
1
0: PEG Wait for BIOS for training
Disable Danbury:Leave floating (internal pull-down)

NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also, All Not update
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. Voltage Rails
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. POWER PLANE VOLTAGE DESCRIPTION
Platform design should provide appropriate pull-up or pull-down depending on ACTIVE IN
C
/GPIO[33] 5V_S0 5V C
the desired settings. If a jumper option is used to tie this signal to GND as 3D3V_S0 3.3V
required by the functional strap, the signal should be pulled low through a weak 1D8V_S0 1.8V
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. 1D5V_S0 1.5V
1D05V_VTT 1.05V
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal 0D85V_S0 0.95 - 0.85V
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for 0D75V_S0 0.75V
strapping functions. VCC_CORE 0.35V to 1.5V
VCC_GFXCORE 0.4 to 1.25V S0
1D8V_VGA_S0 1.8V
3D3V_VGA_S0 3.3V CPU Core Rail
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 1V_VGA_S0 1V Graphics Core Rail

HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no 5V_USBX_S3 5V
GPIO15 1D5V_S3 1.5V S3
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher DDR_VREF_S3 0.75V
suite with confidentiality
Note : This is an un-muxed signal.
BT+ 6V-14.1V AC Brick Mode only
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. DCBATOUT 6V-14.1V
Sampled at rising edge of RSMRST#. 5V_S5 5V All S states
CRB has a 1-kohm pull-up on this signal to +3.3VA rail. 5V_AUX_S5 5V
3D3V_S5 3.3V
3D3V_AUX_S5 3.3V
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of 3D3V_LAN_S5 3.3V WOL_EN Legacy WOL
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
B B

Default = Do not connect (floating) 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states
High(1) = Enables the internal VccVRM to have a clean supply for
GPIO27 analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter Powered by Li Coin Cell in G3
circuits for analog rails. 3D3V_AUX_S5 3.3V G3, Sx and +V3ALW in Sx

USB Table
Pair Device SMBus ADDRESSES
PCIE Routing 0 X
I 2 C / SMBus Addresses
1 USB3.0 ext port 1 HURON RIVER ORB
Device Ref Des Address Hex Bus
LANE1 Mini Card2(WWAN) 2 USB2.0 ext port 4
3 USB3.0 ext port 2 EC SMBus 1 BAT_SCL/BAT_SDA
LANE2 Onboard LAN SATA Table Battery BAT_SCL/BAT_SDA
CHARGER BAT_SCL/BAT_SDA
4 BLUETOOTH
LANE3 Card Reader SATA 5 CARD READER EC SMBus 2 SML1_CLK/SML1_DATA
PCH SML1_CLK/SML1_DATA
LANE4 Mini Card1(WLAN) Pair Device 6 X eDP
SML1_CLK/SML1_DATA
A BOM A
7 X
LANE5 USB3.0 0 N/A
8 X Wistron Corporation
1 HDD1 PCH SMBus
9 USB2.0 ext port 3 SO-DIMMA (SPD) PCH_SMBDATA/PCH_SMBCLK 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
LANE6 Intel GBE LAN 2 N/A SO-DIMMB (SPD) PCH_SMBDATA/PCH_SMBCLK Taipei Hsien 221, Taiwan, R.O.C.
X Digital Pot PCH_SMBDATA/PCH_SMBCLK
10

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G-Sensor PCH_SMBDATA/PCH_SMBCLK Title
LANE7 Dock 3 N/A
11 WLAN(Bluetooth) MINI PCH_SMBDATA/PCH_SMBCLK mTable of Content
4 ODD PCH_SMBDATA/PCH_SMBCLK
12 CAMERA Size Document Number Rev
LANE8 New Card 5 N/A A3 LG4858_UMA -1
13 X
Date: Friday, March 16, 2012 Sheet 3 of 103
5 4 3 2 1
5 4 3 2 1

SSID = CPU Note: Signal Routing Guideline:


Intel DMI supports both Lane PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
Reversal and polarity inversion PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
but only at PCH side. This is
enabled via a soft strap.
1D0V_S0
NOTE.
D CPU1A 1 OF 9 D
PEG_IRCOMP_R R401 1
If PEG is not implemented, the RX&TX pairs can be left as No Connect
PEG_ICOMPI J22 2 24D9R2F-L-GP
IVY-BRIDGE J21
19 DMI_TXN[3:0] PEG_ICOMPO
DMI_TXN0 B27 H22
DMI_TXN1 DMI_RX#0 PEG_RCOMPO
B25 DMI_RX#1
DMI_TXN2 A25 DMI_RX#2
DMI_TXN3 1 R410 2 DMI_TXN3_R B24 DMI_RX#3 PEG_RX#0 K33
19 DMI_TXP[3:0] Do Not Stuff PEG_RX#1 M35
DMI_TXP0 B28 L34
DMI_TXP1 DMI_RX0 PEG_RX#2
B26 DMI_RX1 PEG_RX#3 J35

DMI
DMI_TXP2 A24 J32
DMI_RX2 PEG_RX#4
DMI_TXN3 R404 1 DY 2Do Not Stuff
DMI_TXP3 Do Not Stuff 1 R405 2 DMI_TXP3_R B23 DMI_RX3 PEG_RX#5 H34
19 DMI_RXN[3:0] PEG_RX#6 H31
DMI_RXN0 G21 G33
DMI_TXP3 R406 1 2Do Not Stuff DMI_TX#0 PEG_RX#7
DMI_RXN1 E22 G30
DMI_TX#1 PEG_RX#8
DY DMI_RXN2
DMI_RXN3
F21 DMI_TX#2 PEG_RX#9 F35
D21 DMI_TX#3 PEG_RX#10 E34
E32
Note: 19 DMI_RXP[3:0] DMI_RXP0 G22
PEG_RX#11
D33
DMI_TX0 PEG_RX#12
Form DMI R410, R405, R403 and R404 DMI_RXP1 D22 DMI_TX1 PEG_RX#13 D31
are for SIV debug and validation purposes DMI_RXP2

PCI EXPRESS* - GRAPHICS


F20 DMI_TX2 PEG_RX#14 B33
DMI_RXP3 C21 C32
DMI_TX3 PEG_RX#15

PEG_RX0 J33
PEG_RX1 L35
19 FDI_TXN[7:0] PEG_RX2 K34
FDI_TXN0 A21 H35
FDI_TXN1 FDI0_TX#0 PEG_RX3
H19 FDI0_TX#1 PEG_RX4 H32
FDI_TXN2 E19 G34
C FDI_TXN3 FDI0_TX#2 PEG_RX5 C
F18 G31

Intel(R) FDI
Note: FDI_TXN4 B21
FDI0_TX#3 PEG_RX6
F33
Intel FDI supports both Lane FDI_TXN5 FDI1_TX#0 PEG_RX7
C20 FDI1_TX#1 PEG_RX8 F30
Reversal and polarity inversion FDI_TXN6 D18 FDI1_TX#2 PEG_RX9 E35
but only at PCH side. This is FDI_TXN7 E17 E33
FDI1_TX#3 PEG_RX10
F32
enabled via a soft strap. PEG_RX11
D34
19 FDI_TXP[7:0] FDI_TXP0 PEG_RX12
A22 FDI0_TX0 PEG_RX13 E31
FDI_TXP1 G19 C33
FDI_TXP2 FDI0_TX1 PEG_RX14
E20 FDI0_TX2 PEG_RX15 B32
FDI_TXP3 G18
FDI_TXP4 FDI0_TX3
B20 FDI1_TX0 PEG_TX#0 M29
FDI_TXP5 C19 M32
FDI_TXP6 FDI1_TX1 PEG_TX#1
D19 FDI1_TX2 PEG_TX#2 M31
FDI_TXP7 F17 L32
FDI1_TX3 PEG_TX#3
PEG_TX#4 L29
19 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#5 K31
J17 K28
Note: 19 FDI_FSYNC1 FDI1_FSYNC PEG_TX#6
J30
Lane reversal does not apply to PEG_TX#7
19 FDI_INT H20 FDI_INT PEG_TX#8 J28
FDI sideband signals. PEG_TX#9 H29
19 FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#10 G27
19 FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#11 E29
PEG_TX#12 F27
PEG_TX#13 D28
PEG_TX#14 F26
PEG_TX#15 E25
1D0V_S0 R402 1 2 24D9R2F-L-GP DP_COMP A18 EDP_COMPIO
A17 EDP_ICOMPO PEG_TX0 M28
B R403 1 eDP_HPD B
2 B16 EDP_HPD PEG_TX1 M33
Do Not Stuff
Note: DY PEG_TX2 M30
PEG_TX3 L31
EDP_ICOMPO and EDP_COMPIO should not be left C15 L28
EDP_AUX PEG_TX4
floating. D15 EDP_AUX# PEG_TX5 K30
eDP
PEG_TX6 K27
J29
Signal Routing Guideline: C17
PEG_TX7
J27
EDP_ICOMPO keep W/S=12/15 mils and routing EDP_TX0 PEG_TX8
F16 EDP_TX1 PEG_TX9 H28
length less than 500 mils. C16 EDP_TX2 PEG_TX10 G28
EDP_COMPIO keep W/S=4/15 mils and routing G15 EDP_TX3 PEG_TX11 E28
F28
length less than 500 mils. C18
PEG_TX12
D27
EDP_TX#0 PEG_TX13
E16 EDP_TX#1 PEG_TX14 E26
D16 EDP_TX#2 PEG_TX15 D25
F15 EDP_TX#3
NOTE:
Select a Fast FET similar to 2N7002E whose rise/ IVY-1
fall time is less than 6 ns. If HPD on eDP interface is
disabled, connect it to CPU VCCIO via a 10-kΩ pull-Up 62.10040.821 BOM_CTRL
resistor on the motherboard.
1st = 22.10252.171

2nd = 62.10040.821

A NOTE. 3rd = 62.10055.551 BOM A


Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

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Title
CPU (PCIE/DMI/FDI)
Size Document Number Rev
A3 LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 4 of 103
5 4 3 2 1
5 4 3 2 1

1 TP518 Do Not Stuff


Disabling Guidelines:
SSID = CPU CPU1B 2 OF 9
1 TP519 Do Not Stuff If motherboard only supports external graphics:
Connect DPLL_REF_SSCLK on Processor to GND through
IVY-BRIDGE 1K +/- 5% resistor.
Connect DPLL_REF_SSCLK# on Processor to VCCP
BCLK A28 CLK_EXP_P 20 through 1K +/- 5% resistorpower (~15 mW) may be

MISC

CLOCKS
22 H_SNB_IVB# C26 A27
PROC_SELECT# BCLK# CLK_EXP_N 20 wasted.

Do Not Stuff TP501 1 SKTOCC#_R AN34 SKTOCC#


D A16 CLK_DP_P_R CLK_DP_P_R 20 D
DPLL_REF_CLK CLK_DP_N_R
1D0V_S0 DPLL_REF_CLK# A15 CLK_DP_N_R 20

62R2J-GP 1 TP523 Do Not Stuff


1 H_CATERR# AL33
R501 Do Not Stuff TP502 CATERR# SM_DRAMRST# 37 1D05V_VTT
CLK_DP_P_R
1 2 H_PROCHOT#

THERMAL
20110728 for intel check list
AN33 R8 SM_DRAMRST# 2 1
1

22,27 H_PECI PECI SM_DRAMRST#

2
R502 4K99R2F-L-GP
C502

DDR3
MISC
SC43P50V2JN-GP R518 R520
SIV R513
2

1KR2J-1-GP 1KR2J-1-GP
27,42 H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R506 1 2 140R2F-GP
PROCHOT# SM_RCOMP0 SM_RCOMP_1 R507 1
A5 2 25D5R2F-GP

1
SM_RCOMP1
Intel recommends 43pf 56R2J-4-GP
SM_RCOMP2 A4 SM_RCOMP_2 R508 1 2 200R2F-L-GP

22,36 H_THERMTRIP# AN32 CLK_DP_N_R


THERMTRIP#
Signal Routing Guideline:
Do Not Stuff TP521 1 SM_RCOMP keep routing length less than 500 mils.
PRDY# AP29 XDP_PRDY# 1 TP511 Do Not Stuff
SVT PREQ# AP27 XDP_PREQ# 1 TP512 Do Not Stuff 1D0V_S0

TCK AR26 XDP_TCLK 1 TP513 Do Not Stuff

PWR MANAGEMENT
AR27 XDP_TMS 1

JTAG & BPM


TMS TP514 Do Not Stuff
2

19 H_PM_SYNC AM34 PM_SYNC TRST# AP30 XDP_TRST# 1 TP515 Do Not Stuff XDP_TDO R523 1
EC502 2
51R2J-2-GP
SC10P50V2JN-4GP Do Not Stuff TP524 1 AR28 XDP_TDI 1 TP516 Do Not Stuff
1

TDI
C
R504 TDO AP26 XDP_TDO 1 TP517 Do Not Stuff
C

22,36,97 H_CPUPW RGD 1 2 H_CPUPW RGD_R AP33 UNCOREPWRGOOD RN501


Do Not Stuff XDP_TMS 1 8
DBR# AL35 XDP_DBRESET# XDP_TDI 2 7
19,37 PM_DRAM_PW RGD 1 R505 2VDDPW RGOOD V8 XDP_TCLK 3 6
SM_DRAMPWROK XDP_TRST#
DY Do Not Stuff 4 5
1R503 2 H_CPUPW RGD_R Do Not Stuff TP522 1 BPM#0 AT28 XDP_BPM0 1 TP503 TPAD14-OP-GP
10KR2J-3-GP AR29 XDP_BPM1 1 SRN51J-1-GP
37 VDDPW RGOOD BPM#1 TP504 Do Not Stuff
AR30 XDP_BPM2 1 TP505 Do Not Stuff
BUF_CPU_RST# BPM#2 XDP_BPM3
Do Not Stuff TP520 1 AR33 RESET# BPM#3 AT30 1 TP506 Do Not Stuff
AP32 XDP_BPM4 1 TP507 Do Not Stuff
BPM#4 XDP_BPM5
BPM#5 AR31 1 TP508 Do Not Stuff
AT31 XDP_BPM6 1 TP509 Do Not Stuff
BPM#6 XDP_BPM7
BPM#7 AR32 1 TP510 Do Not Stuff

IVY-1

62.10040.821 3D3V_S0

1D0V_S0
19 XDP_DBRESET# XDP_DBRESET# 1 2
R516
1KR2J-1-GP
1

B B

R519 3D3V_S0
75R2J-1-GP
DY
2

Buffered reset to CPU R512


1 2
Close CPU side
1
Do Not Stuff
C503
U501 SCD1U10V2KX-5GP
2

1 IN B VCC 5
18,27,31,36,65,97 PLT_RST#
2 IN A
R517
3 GND OUT Y 4 BUFO_CPU_RST# BUF_CPU_RST#
1 2
1
74VHC1G09DFT2G-GP 43R2J-GP R515 DY

1
73.01G09.AAH Do Not Stuff
C501
DY Do Not Stuff

2
2

NOTE BOM
A A
U501 R512 R519 R517 R515 C503 C501
DY 0 ohm DY 1.5K ohm 750 ohm DY DY Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
HR Taipei Hsien 221, Taiwan, R.O.C.
63.R0034.1DL 64.15015.6DL 64.75005.6DL
Title
DY 75 ohm 43 ohm DY 0.1uF DY THERMAL/CLOCK/PM

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CRV Default CRV
73.01G09.AAH 63.75034.1DL 63.43034.1DL 78.10423.2FL Size Document Number Rev
A3 LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 5 of 103

5 4 3 2 1
5 4 3 2 1

SSID = CPU
CPU1C 3 OF 9 CPU1D 4 OF 9

D D
IVY-BRIDGE IVY-BRIDGE
SA_CK0 AB6 M_A_DIM0_CLK_DDR0 14 SB_CK0 AE2 M_B_DIM0_CLK_DDR0 15
M_A_DQ[63:0] AA6 M_B_DQ[63:0] AD2
14 M_A_DQ[63:0] SA_CLK#0 M_A_DIM0_CLK_DDR#0 14 15 M_B_DQ[63:0] SB_CLK#0 M_B_DIM0_CLK_DDR#0 15
M_A_DQ0 C5 V9 M_B_DQ0 C9 R9
M_A_DQ1 SA_DQ0 SA_CKE0 M_A_DIM0_CKE0 14 M_B_DQ1 SB_DQ0 SB_CKE0 M_B_DIM0_CKE0 15
D5 SA_DQ1 A7 SB_DQ1
M_A_DQ2 D3 M_B_DQ2 D10
M_A_DQ3 SA_DQ2 M_B_DQ3 SB_DQ2
D2 SA_DQ3 C8 SB_DQ3
M_A_DQ4 D6 AA5 M_B_DQ4 A9 AE1
M_A_DQ5 SA_DQ4 SA_CK1 M_A_DIM0_CLK_DDR1 14 M_B_DQ5 SB_DQ4 SB_CK1 M_B_DIM0_CLK_DDR1 15
C6 SA_DQ5 SA_CLK#1 AB5 M_A_DIM0_CLK_DDR#1 14 A8 SB_DQ5 SB_CLK#1 AD1 M_B_DIM0_CLK_DDR#1 15
M_A_DQ6 C2 V10 M_B_DQ6 D9 R10
M_A_DQ7 SA_DQ6 SA_CKE1 M_A_DIM0_CKE1 14 M_B_DQ7 SB_DQ6 SB_CKE1 M_B_DIM0_CKE1 15
C3 SA_DQ7 D8 SB_DQ7
M_A_DQ8 F10 M_B_DQ8 G4
M_A_DQ9 SA_DQ8 M_B_DQ9 SB_DQ8
F8 SA_DQ9 F4 SB_DQ9
M_A_DQ10 G10 AB4 M_B_DQ10 F1 AB2
M_A_DQ11 SA_DQ10 SA_CK2 M_B_DQ11 SB_DQ10 SB_CK2
G9 SA_DQ11 SA_CLK#2 AA4 G1 SB_DQ11 SB_CLK#2 AA2
M_A_DQ12 F9 W9 M_B_DQ12 G5 T9
M_A_DQ13 SA_DQ12 SA_CKE2 M_B_DQ13 SB_DQ12 SB_CKE2
F7 SA_DQ13 F5 SB_DQ13
M_A_DQ14 G8 M_B_DQ14 F2
M_A_DQ15 SA_DQ14 M_B_DQ15 SB_DQ14
G7 SA_DQ15 G2 SB_DQ15
M_A_DQ16 K4 AB3 M_B_DQ16 J7 AA1
M_A_DQ17 SA_DQ16 SA_CK3 M_B_DQ17 SB_DQ16 SB_CK3
K5 SA_DQ17 SA_CLK#3 AA3 J8 SB_DQ17 SB_CLK#3 AB1
M_A_DQ18 K1 W10 M_B_DQ18 K10 T10
M_A_DQ19 SA_DQ18 SA_CKE3 M_B_DQ19 SB_DQ18 SB_CKE3
J1 SA_DQ19 K9 SB_DQ19
M_A_DQ20 J5 M_B_DQ20 J9
M_A_DQ21 SA_DQ20 M_B_DQ21 SB_DQ20
J4 SA_DQ21 J10 SB_DQ21
M_A_DQ22 J2 AK3 M_B_DQ22 K8 AD3
M_A_DQ23 SA_DQ22 SA_CS#0 M_A_DIM0_CS#0 14 M_B_DQ23 SB_DQ22 SB_CS#0 M_B_DIM0_CS#0 15
K2 SA_DQ23 SA_CS#1 AL3 M_A_DIM0_CS#1 14 K7 SB_DQ23 SB_CS#1 AE3 M_B_DIM0_CS#1 15
M_A_DQ24 M8 AG1 M_B_DQ24 M5 AD6
C M_A_DQ25 SA_DQ24 SA_CS#2 M_B_DQ25 SB_DQ24 SB_CS#2 C
N10 SA_DQ25 SA_CS#3 AH1 N4 SB_DQ25 SB_CS#3 AE6
M_A_DQ26 N8 M_B_DQ26 N2
M_A_DQ27 SA_DQ26 M_B_DQ27 SB_DQ26
N7 SA_DQ27 N1 SB_DQ27
M_A_DQ28 M10 M_B_DQ28 M4
M_A_DQ29 SA_DQ28 M_B_DQ29 SB_DQ28
M9 SA_DQ29 SA_ODT0 AH3 M_A_DIM0_ODT0 14 N5 SB_DQ29 SB_ODT0 AE4 M_B_DIM0_ODT0 15

DDR SYSTEM MEMORY B


M_A_DQ30 N9 AG3 M_B_DQ30 M2 AD4
DDR SYSTEM MEMORY A
M_A_DQ31 SA_DQ30 SA_ODT1 M_A_DIM0_ODT1 14 M_B_DQ31 SB_DQ30 SB_ODT1 M_B_DIM0_ODT1 15
M7 SA_DQ31 SA_ODT2 AG2 M1 SB_DQ31 SB_ODT2 AD5
M_A_DQ32 AG6 AH2 M_B_DQ32 AM5 AE5
M_A_DQ33 SA_DQ32 SA_ODT3 M_B_DQ33 SB_DQ32 SB_ODT3
AG5 SA_DQ33 AM6 SB_DQ33
M_A_DQ34 AK6 M_B_DQ34 AR3
M_A_DQ35 SA_DQ34 M_B_DQ35 SB_DQ34
AK5 SA_DQ35 AP3 SB_DQ35
M_A_DQ36 AH5 M_A_DQS#[7:0] 14 M_B_DQ36 AN3 M_B_DQS#[7:0] 15
M_A_DQ37 SA_DQ36 M_A_DQS#0 M_B_DQ37 SB_DQ36 M_B_DQS#0
AH6 SA_DQ37 SA_DQS#0 C4 AN2 SB_DQ37 SB_DQS#0 D7
M_A_DQ38 AJ5 G6 M_A_DQS#1 M_B_DQ38 AN1 F3 M_B_DQS#1
M_A_DQ39 SA_DQ38 SA_DQS#1 M_A_DQS#2 M_B_DQ39 SB_DQ38 SB_DQS#1 M_B_DQS#2
AJ6 SA_DQ39 SA_DQS#2 J3 AP2 SB_DQ39 SB_DQS#2 K6
M_A_DQ40 AJ8 M6 M_A_DQS#3 M_B_DQ40 AP5 N3 M_B_DQS#3
M_A_DQ41 SA_DQ40 SA_DQS#3 M_A_DQS#4 M_B_DQ41 SB_DQ40 SB_DQS#3 M_B_DQS#4
AK8 SA_DQ41 SA_DQS#4 AL6 AN9 SB_DQ41 SB_DQS#4 AN5
M_A_DQ42 AJ9 AM8 M_A_DQS#5 M_B_DQ42 AT5 AP9 M_B_DQS#5
M_A_DQ43 SA_DQ42 SA_DQS#5 M_A_DQS#6 M_B_DQ43 SB_DQ42 SB_DQS#5 M_B_DQS#6
AK9 SA_DQ43 SA_DQS#6 AR12 AT6 SB_DQ43 SB_DQS#6 AK12
M_A_DQ44 AH8 AM15 M_A_DQS#7 M_B_DQ44 AP6 AP15 M_B_DQS#7
M_A_DQ45 SA_DQ44 SA_DQS#7 M_B_DQ45 SB_DQ44 SB_DQS#7
AH9 SA_DQ45 AN8 SB_DQ45
M_A_DQ46 AL9 M_B_DQ46 AR6
M_A_DQ47 SA_DQ46 M_B_DQ47 SB_DQ46
AL8 SA_DQ47 AR5 SB_DQ47
M_A_DQ48 AP11 M_A_DQS[7:0] 14 M_B_DQ48 AR9 M_B_DQS[7:0] 15
M_A_DQ49 SA_DQ48 M_A_DQS0 M_B_DQ49 SB_DQ48 M_B_DQS0
AN11 SA_DQ49 SA_DQS0 D4 AJ11 SB_DQ49 SB_DQS0 C7
M_A_DQ50 AL12 F6 M_A_DQS1 M_B_DQ50 AT8 G3 M_B_DQS1
M_A_DQ51 SA_DQ50 SA_DQS1 M_A_DQS2 M_B_DQ51 SB_DQ50 SB_DQS1 M_B_DQS2
AM12 SA_DQ51 SA_DQS2 K3 AT9 SB_DQ51 SB_DQS2 J6
M_A_DQ52 AM11 N6 M_A_DQS3 M_B_DQ52 AH11 M3 M_B_DQS3
M_A_DQ53 SA_DQ52 SA_DQS3 M_A_DQS4 M_B_DQ53 SB_DQ52 SB_DQS3 M_B_DQS4
AL11 SA_DQ53 SA_DQS4 AL5 AR8 SB_DQ53 SB_DQS4 AN6
B M_A_DQ54 M_A_DQS5 M_B_DQ54 M_B_DQS5 B
AP12 SA_DQ54 SA_DQS5 AM9 AJ12 SB_DQ54 SB_DQS5 AP8
M_A_DQ55 AN12 AR11 M_A_DQS6 M_B_DQ55 AH12 AK11 M_B_DQS6
M_A_DQ56 SA_DQ55 SA_DQS6 M_A_DQS7 M_B_DQ56 SB_DQ55 SB_DQS6 M_B_DQS7
AJ14 SA_DQ56 SA_DQS7 AM14 AT11 SB_DQ56 SB_DQS7 AP14
M_A_DQ57 AH14 M_B_DQ57 AN14
M_A_DQ58 SA_DQ57 M_B_DQ58 SB_DQ57
AL15 SA_DQ58 AR14 SB_DQ58
M_A_DQ59 AK15 M_B_DQ59 AT14
M_A_DQ60 SA_DQ59 M_B_DQ60 SB_DQ59
AL14 SA_DQ60 M_A_A[15:0] 14 AT12 SB_DQ60 M_B_A[15:0] 15
M_A_DQ61 AK14 AD10 M_A_A0 M_B_DQ61 AN15 AA8 M_B_A0
M_A_DQ62 SA_DQ61 SA_MA0 M_A_A1 M_B_DQ62 SB_DQ61 SB_MA0 M_B_A1
AJ15 SA_DQ62 SA_MA1 W1 AR15 SB_DQ62 SB_MA1 T7
M_A_DQ63 AH15 W2 M_A_A2 M_B_DQ63 AT15 R7 M_B_A2
SA_DQ63 SA_MA2 M_A_A3 SB_DQ63 SB_MA2 M_B_A3
SA_MA3 W7 SB_MA3 T6
V3 M_A_A4 T2 M_B_A4
SA_MA4 M_A_A5 SB_MA4 M_B_A5
SA_MA5 V2 SB_MA5 T4
W3 M_A_A6 T3 M_B_A6
SA_MA6 M_A_A7 SB_MA6 M_B_A7
14 M_A_BS0 AE10 SA_BS0 SA_MA7 W6 15 M_B_BS0 AA9 SB_BS0 SB_MA7 R2
14 M_A_BS1 AF10 V1 M_A_A8 15 M_B_BS1 AA7 T5 M_B_A8
SA_BS1 SA_MA8 M_A_A9 SB_BS1 SB_MA8 M_B_A9
14 M_A_BS2 V6 SA_BS2 SA_MA9 W5 15 M_B_BS2 R6 SB_BS2 SB_MA9 R3
AD8 M_A_A10 AB7 M_B_A10
SA_MA10 M_A_A11 SB_MA10 M_B_A11
SA_MA11 V4 SB_MA11 R1
W4 M_A_A12 T1 M_B_A12
SA_MA12 M_A_A13 SB_MA12 M_B_A13
14 M_A_CAS# AE8 SA_CAS# SA_MA13 AF8 15 M_B_CAS# AA10 SB_CAS# SB_MA13 AB10
14 M_A_RAS# AD9 V5 M_A_A14 15 M_B_RAS# AB8 R5 M_B_A14
SA_RAS# SA_MA14 M_A_A15 SB_RAS# SB_MA14 M_B_A15
14 M_A_W E# AF9 SA_WE# SA_MA15 V7 15 M_B_W E# AB9 SB_WE# SB_MA15 R4

A IVY-1 IVY-1 BOM A


62.10040.821 62.10040.821

BOM_CTRL BOM_CTRL Wistron Corporation


21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

www.vinafix.vn
Title
CPU (DDR)
Size Document Number Rev
A3 LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 6 of 103
5 4 3 2 1
5 4 3 2 1

SSID = CPU
CFG2
CFG7
D D

1
PEG Static Lane Reversal

1
R702 PEG DEFER TRAINING
Do Not Stuff R705
1: Normal Operation; Lane # Do Not Stuff
DY CFG2 definition matches socket pin map definition DY
CFG7 1: PEG Train immediately following xxRESETB de assertion
2

2
0:Lane Reversed 0: PEG Wait for BIOS for training

CFG4

Display Port Presence Strap


1

CPU1E 5 OF 9
R703
Do Not Stuff 1: Disabled; No Physical Display Port IVY-BRIDGE
CFG4
DY attached to Embedded Display Port
AH27 TP713
2

0: Enabled; An external Display Port device is VCC_DIE_SENSE 1 TP720 Do Not Stuff


1 CFG0 AK28 AH26
connected to the Embedded Display Port Do Not Stuff TP717 CFG0 VSS_DIE_SENSE
AK29 CFG1
CFG2 AL26 CFG2
CFG5 AL27 CFG3
CFG4 AK26 L7
CFG5 CFG4 RSVD#L7
CFG6 AL29 CFG5 RSVD#AG7 AG7
PCIE Port Bifurcation Straps CFG6 AL30 CFG6 RSVD#AE7 AE7
CFG7 AM31 AK2
1

CFG7 RSVD#AK2
R701 R704 AM32 CFG8

CFG
CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled AM30 W8
C
DY DY AM28
CFG9 RSVD#W8 C
CFG10
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled AM26 CFG11
2

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) AN28 CFG12 RSVD#AT26 AT26
AN31 AM33
Do Not Stuff

Do Not Stuff

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled CFG13 RSVD#AM33


AN26 CFG14 RSVD#AJ27 AJ27
AM27 CFG15
AK31 CFG16
AN29 CFG17

RSVD#T8 T8
RSVD#J16 J16
AJ31 VAXG_VAL_SENSE RSVD#H16 H16
AH31 VSSAXG_VAL_SENSE RSVD#G16 G16
AJ33 VCC_VAL_SENSE
AH33 VSS_VAL_SENSE

AJ26 AR35 NCTF#AR35 1 TP721 Do Not Stuff


RSVD#AJ26 RSVD_NCTF#AR35

RESERVED
AT34 NCTF#AT34 1 TP722 Do Not Stuff
RSVD_NCTF#AT34 NCTF#AT33
RSVD_NCTF#AT33 AT33 1 TP723 Do Not Stuff
AP35 NCTF#AP35 1 TP724 Do Not Stuff
RSVD_NCTF#AP35 NCTF#AR34
RSVD_NCTF#AR34 AR34 1 TP725 Do Not Stuff

F25 RSVD#F25
F24 RSVD#F24
F23 RSVD#F23
D24 RSVD#D24 RSVD_NCTF#B34 B34
B NCTF#A33 B
G25 RSVD#G25 RSVD_NCTF#A33 A33 1 TP727 Do Not Stuff
G24 A34 NCTF#A34 1 TP728 Do Not Stuff
RSVD#G24 RSVD_NCTF#A34
E23 RSVD#E23 RSVD_NCTF#B35 B35
D23 RSVD#D23 RSVD_NCTF#C35 C35
C30 RSVD#C30
A31 RSVD#A31
SIV
B30 RSVD#B30
B29 RSVD#B29
D30 RSVD#D30 RSVD#AJ32 AJ32
B31 RSVD#B31 RSVD#AK32 AK32
A30 RSVD#A30
C29 RSVD#C29
AN35 CLK_XDP_ITP_P 1 TP718 Do Not Stuff
BCLK_ITP CLK_XDP_ITP_N
J20 RSVD#J20 BCLK_ITP# AM35 1 TP719 Do Not Stuff
B18 RSVD#B18

J15 RSVD#J15 RSVD_NCTF#AT2 AT2


RSVD_NCTF#AT1 AT1
RSVD_NCTF#AR1 AR1

A BOM A

IVY-1
62.10040.821 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
BOM_CTRL

www.vinafix.vn
Title
CPU (RESERVED)
Size Document Number Rev
A3 LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 7 of 103
5 4 3 2 1
5 4 3 2 1

SSID = CPU
CPU1F POWER 6 OF 9

IVY-BRIDGE

VCC_CORE
1D0V_S0

AG35 VCC1
VCCIO:8.5A
VCC_CORE VCC CORE:53A AG34
AG33
VCC2 VCCIO1 AH13
AH10
D VCC3 VCCIO2 D

C805

C806

C807

C808

C809

C810

C838

C839

C840

C841
SC10U6D3V5KX-1GP
AG32 VCC4 VCCIO3 AG10

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
1

1
SC10U6D3V5KX-1GP
AG31 VCC5 VCCIO4 AC10
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
AG30 VCC6 VCCIO5 Y10

Do Not Stuff

Do Not Stuff
C801

C802

C803

C804

C811
AG29 U10

2
VCC7 VCCIO6
1

1
AG28 VCC8 VCCIO7 P10
AG27 VCC9 VCCIO8 L10
AG26 J14
2

2
VCC10 VCCIO9
AF35 VCC11 VCCIO10 J13
AF34 VCC12 VCCIO11 J12
AF33 VCC13 VCCIO12 J11
DY DY AF32 VCC14 VCCIO13 H14
AF31 VCC15 VCCIO14 H12
AF30 VCC16 VCCIO15 H11
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13

PEG AND DDR


SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
AF27 VCC19 VCCIO18 G12
C817

C820
AF26 VCC20 VCCIO19 F14
1

1 AD35 VCC21 VCCIO20 F13


AD34
AD33
VCC22 VCCIO21 F12
F11 1D0V_S0
-to 17pcs
2

VCC23 VCCIO22
AD32 VCC24 VCCIO23 E14
AD31 E12
AD30
VCC25
VCC26
VCCIO24 TC8xx
AD29 VCC27 VCCIO25 E11

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
AD28 D14
VCC28 VCCIO26
470uF x2

C812

C813

C814

C829

C830

C842

C843

C844

C845
AD27 VCC29 VCCIO27 D13

1
AD26 VCC30 VCCIO28 D12
AC35 VCC31 VCCIO29 D11
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
AC34 C14

2
VCC32 VCCIO30
C816

C821

C822

C823

C825

C826

C827
AC33 VCC33 VCCIO31 C13
1

1
C AC32 VCC34 VCCIO32 C12 C
AC31 VCC35 VCCIO33 C11
AC30 B14
2

2 VCC36 VCCIO34
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14
AC27 VCC39 VCCIO37 A13
AC26 VCC40 VCCIO38 A12
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 VCC44
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

AA31 VCC45
Do Not Stuff

Do Not Stuff
C837

C836

C835

C834

C833

C832

C831

C828

AA30 VCC46
1

AA29 VCC47
AA28 VCC48
AA27
2

VCC49
AA26 VCC50

CORE SUPPLY
Y35 VCC51 1D0V_S0
Y34 VCC52 R807 need to close to CPU
DY DY Y33 VCC53
Y32 VCC54
Y31

1
VCC55
Y30 VCC56 R808
Y29 R807 110722 Ge
VCC57 10R2F-L-GP
Y28 VCC58 1 2 1D0V_S0
Y27 VCC59 75R2F-2-GP

2
Y26 VCC60
V35 VCC61 VCCIO_SENSE

SVID
V34 AJ29 H_CPU_SVIDALRT# R803 1 2 43R2J-GP
VCC62 VIDALERT# VR_SVID_ALERT# 42
V33 AJ30 H_CPU_SVIDCLK_R R805 1 2 Do Not Stuff VSSIO_SENSE
VCC63 VIDSCLK H_CPU_SVIDDAT_R R806 1 H_CPU_SVIDCLK 42
V32 VCC64 VIDSOUT AJ28 2 Do Not Stuff H_CPU_SVIDDAT 42
B V31 VCC65 B

1
V30 VCC66
V29 R809
VCC67 R804 10R2F-L-GP
V28 VCC68 1 2 1D0V_S0
V27 VCC69
V26 130R2F-1-GP

2
VCC70
U35 VCC71 For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7
U34
U33
VCC72 For CRB VIDALERT# need to pull high 75 ohm close to CPU
VCC73
U32 VCC74
U31 VCC75
U30 VCC76
U29 VCC77
U28 VCC78
U27 VCC79
U26 VCC80
R35 VCC_CORE
VCC81
R34 VCC82
R33 VCC83 R801, R802 need to close to CPU

1
R32 VCC84
R31 R801
VCC85 100R2F-L1-GP-U
R30 VCC86
R29 VCC87
SENSE LINES

R28

2
VCC88
R27 VCC89 VCC_SENSE AJ35 VCCSENSE 42
R26 VCC90 VSS_SENSE AJ34 VSSSENSE 42
P35 VCC91

1
P34 VCC92
P33 R802
VCC93 VCCIO_SENSE 100R2F-L1-GP-U
P32 VCC94 VCCIO_SENSE B10 1 TP802 Do Not Stuff
P31 A10 VSSIO_SENSE 1
VCC95 VSS_SENSE_VCCIO TP803 Do Not Stuff
A P30 A

2
VCC96
P29 VCC97 BOM
P28 VCC98
P27 VCC99
P26 VCC100 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

www.vinafix.vn
Title
mCPU (VCC_CORE)
Size Document Number Rev
IVY-1
BOM_CTRL Custom LG4858_UMA -1
62.10040.821 Date: Friday, March 16, 2012 Sheet 8 of 103
5 4 3 2 1
5 4 3 2 1

SSID = CPU Routing Guideline:


Power from DDR_VREF_S3 and +V_SM_VREF_CNT M3 - Processor Generated SO-DIMM VREF_DQ
should have 10 mils trace width.
R915 1
DY
2 Do Not Stuff
VCC_GFXCORE
CPU1G
POWER 7 OF 9
M_VREF_DQ_DIMM0

M_VREF_CA_DIMM0 R916 1 2 Do Not Stuff


DY

4
3
D D

SENSE
LINES
AT24 IVY-BRIDGE AK35 RN903
VAXG1 VAXG_SENSE VCC_AXG_SENSE 42

RC901
AT23 AK34 Do Not Stuff
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
VAXG2 VSSAXG_SENSE VSS_AXG_SENSE 42 12 DDR_W R_VREF01

Do Not Stuff
Refer to the latest Huron River Mainstream PDG
C901

C902

C903

C904

C905

C906
AT21 VAXG3
DY
1

1
AT20 VAXG4 (Doc# 436735) for more details on S3 power 12 DDR_W R_VREF02
DY AT18 reduction implementation.

1
2
VAXG5
AT17
2

2
VAXG6
AR24 VAXG7
AR23 VAXG8
+V_SM_VREF_CNT should have 10 mil trace width
AR21 VAXG9
AR20 VAXG10
AR18 AL1 +V_SM_VREF_CNT
VAXG11 SM_VREF +V_SM_VREF_CNT 37
AR17 VAXG12

VREF
AP24 VAXG13
AP23 VAXG14
AP21 VAXG15
AP20 VAXG16 SA_DIMM_VREFDQ B4

RC902
AP18 D1
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
VAXG17 SB_DIMM_VREFDQ

Do Not Stuff
C907

C908

C918

C919

C920

C921
AP17 VAXG18
1

1
AN24 VAXG19
DY AN23 VAXG20
AN21
2

2
VAXG21
AN20 VAXG22 1D5V_S0

DDR3 -1.5V RAILS


AN18 VAXG23 VCC_GFXCORE
Close to CPU
AN17 VAXG24 PROCESSOR VDDQ: 12A SIV

GRAPHICS
AM24 VAXG25 VDDQ1 AF7
AM23 AF4

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
VAXG26 VDDQ2

C909

C910

C911

C912

C913

C914
AM21 VAXG27 VDDQ3 AF1

1
AM20 AC7 TC902
C VAXG28 VDDQ4 Do Not Stuff R906 C
AM18 VAXG29 VDDQ5 AC4
AM17 AC1 100R2F-L1-GP-U

2
VAXG30 VDDQ6
AL24 VAXG31 VDDQ7 Y7
AL23 Y4

2
VAXG32 VDDQ8 VCC_AXG_SENSE
AL21 VAXG33 VDDQ9 Y1 DY
AL20
AL18
VAXG34 VDDQ10 U7
U4
TC9xx VSS_AXG_SENSE
VAXG35 VDDQ11 VCCSA
AL17 U1
VAXG36 VDDQ12
330uF

1
AK24 VAXG37 VDDQ13 P7
AK23 P4 PROCESSOR VCCSA: 6A R907
VAXG38 VDDQ14 100R2F-L1-GP-U
AK21 VAXG39 VDDQ15 P1
AK20 TC9xx

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
VAXG40

C916

C915

C917
AK18

2
VAXG41

1
AK17 VAXG42
AJ24
AJ23
VAXG43 330uF

2
VAXG44 SIV for intel recommend
AJ21 VAXG45
AJ20 VAXG46
AJ18
AJ17
VAXG47
M27 NOTE
SA RAIL
VAXG48 VCCSA1
AH24 VAXG49 VCCSA2 M26
AH23 L26
AH21
VAXG50
VAXG51
VCCSA3
VCCSA4 J26 R906/R907
AH20 J25
AH18
VAXG52
VAXG53
VCCSA5
VCCSA6 J24 100 ohm
AH17 VAXG54 VCCSA7 H26
H25
HR 64.10005.6DL
VCCSA8
R902 need be close to pin H23. 10 ohm
B Default CRV CRV B
64.10R05.6DL
1.8V RAIL

H23 VCCSA_SENSE
1D8V_S0 VCCSA_SENSE VCCSA_SENSE 48

VCCPLL:1.5A B6 VCCPLL1
MISC

A6 C22
SC1U10V2KX-1GP

SC1U10V2KX-1GP
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

VCCPLL2 VCCSA_VID0 VCCSA_SELECT0 48


C925

C923

C922

C924

A2 C24
VCCPLL3 VCCSA_VID1 VCCSA_SELECT1 48
BOM Control
1

R917~R920
2

A19 1D0V_S0 1D0V_S0


VCCIO_SEL

Default Intel check list


10K ohm
IVY-1 Intel
---------------
62.10040.821

2
TC9xx R917 R920 1K ohm
Do Not Stuff Do Not Stuff CRV 66.10236.04L
330uF SIV DY DY

1
3D3V_S5
VCCSA_SELECT0 VCCSA_SELECT1 20110728 for Danny
1

2
2

R913 R919
Do Not Stuff R918 1KR2J-1-GP
A DY 1KR2J-1-GP
BOM A
2

1
Wistron Corporation
1

ES2 dummy R913 H_VCCP_SEL


21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

www.vinafix.vn
Title
mCPU (VCC_GFXCORE)
Size Document Number Rev
A3 LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 9 of 103
5 4 3 2 1
5 4 3 2 1

SSID = CPU
CPU1H 8 OF 9 CPU1I 9 OF 9
D D
AT35 VSS1 VSS81 AJ22
AT32 VSS2 VSS82 AJ19
AT29 IVY-BRIDGE AJ16 T35 IVY-BRIDGE F22
VSS3 VSS83 VSS161 VSS234
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30
AT22 VSS6 VSS86 AJ7 T32 VSS164 VSS237 E27
AT19 VSS7 VSS87 AJ4 T31 VSS165 VSS238 E24
AT16 VSS8 VSS88 AJ3 T30 VSS166 VSS239 E21
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18
AT10 VSS10 VSS90 AJ1 T28 VSS168 VSS241 E15
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6
AR16 VSS17 VSS98 AH25 P3 VSS175 VSS248 E5
AR13 VSS18 VSS99 AH22 P2 VSS176 VSS249 E4
AR10 VSS19 VSS100 AH19 N35 VSS177 VSS250 E3
AR7 VSS20 VSS101 AH16 N34 VSS178 VSS251 E2
AR4 VSS21 VSS102 AH7 N33 VSS179 VSS252 E1
AR2 VSS22 VSS103 AH4 N32 VSS180 VSS253 D35
AP34 VSS23 VSS104 AG9 N31 VSS181 VSS254 D32
AP31 VSS24 VSS105 AG8 N30 VSS182 VSS255 D29
AP28 VSS25 VSS106 AG4 N29 VSS183 VSS256 D26
AP25 VSS26 VSS107 AF6 N28 VSS184 VSS257 D20
AP22 VSS27 VSS108 AF5 N27 VSS185 VSS258 D17
AP19 VSS28 VSS109 AF3 N26 VSS186 VSS259 C34
C AP16 AF2 M34 C31 C
VSS29 VSS110 VSS187 VSS260
AP13 VSS30 VSS111 AE35 L33 VSS188 VSS261 C28
AP10 VSS31 VSS112 AE34 L30 VSS189 VSS262 C27
AP7 VSS32 VSS113 AE33 L27 VSS190 VSS263 C25
AP4 VSS33 VSS114 AE32 L9 VSS191 VSS264 C23
AP1 VSS34 VSS115 AE31 L8 VSS192 VSS265 C10
AN30 VSS35 VSS116 AE30 L6 VSS193 VSS266 C1
AN27 VSS36 VSS117 AE29 L5 VSS194 VSS267 B22
AN25
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE28
AE27
AE26
L4
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B19
B17
B15
AN16 VSS40 VSS121 AE9 L1 VSS198 VSS271 B13
AN13 VSS41 VSS122 AD7 K35 VSS199 VSS272 B11
AN10 VSS42 VSS123 AC9 K32 VSS200 VSS273 B9
AN7 VSS43 VSS124 AC8 K29 VSS201 VSS274 B8
AN4 VSS44 VSS125 AC6 K26 VSS202 VSS275 B7
AM29 VSS45 VSS126 AC5 J34 VSS203 VSS276 B5
AM25 VSS46 VSS127 AC3 J31 VSS204 VSS277 B3
AM22 VSS47 VSS128 AC2 H33 VSS205 VSS278 B2
AM19 VSS48 VSS129 AB35 H30 VSS206 VSS279 A35
AM16 VSS49 VSS130 AB34 H27 VSS207 VSS280 A32
AM13 VSS50 VSS131 AB33 H24 VSS208 VSS281 A29
AM10 VSS51 VSS132 AB32 H21 VSS209 VSS282 A26
AM7 VSS52 VSS133 AB31 H18 VSS210 VSS283 A23
AM4 VSS53 VSS134 AB30 H15 VSS211 VSS284 A20
AM3 VSS54 VSS135 AB29 H13 VSS212 VSS285 A3
AM2 VSS55 VSS136 AB28 H10 VSS213
AM1 VSS56 VSS137 AB27 H9 VSS214
AL34 VSS57 VSS138 AB26 H8 VSS215
B B
AL31 VSS58 VSS139 Y9 H7 VSS216
AL28 VSS59 VSS140 Y8 H6 VSS217
AL25 VSS60 VSS141 Y6 H5 VSS218
AL22 VSS61 VSS142 Y5 H4 VSS219
AL19 VSS62 VSS143 Y3 H3 VSS220
AL16 VSS63 VSS144 Y2 H2 VSS221
AL13 VSS64 VSS145 W35 H1 VSS222
AL10 VSS65 VSS146 W34 G35 VSS223
AL7 VSS66 VSS147 W33 G32 VSS224
AL4 VSS67 VSS148 W32 G29 VSS225
AL2 VSS68 VSS149 W31 G26 VSS226
AK33 VSS69 VSS150 W30 G23 VSS227
AK30 VSS70 VSS151 W29 G20 VSS228
AK27 VSS71 VSS152 W28 G17 VSS229
AK25 VSS72 VSS153 W27 G11 VSS230
AK22 VSS73 VSS154 W26 F34 VSS231
AK19 VSS74 VSS155 U9 F31 VSS232
AK16 VSS75 VSS156 U8 F29 VSS233
AK13 VSS76 VSS157 U6
AK10 VSS77 VSS158 U5
AK7 VSS78 VSS159 U3
AK4 VSS79 VSS160 U2
AJ25 VSS80

IVY-1 IVY-1
A 62.10040.821 62.10040.821 BOM A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

www.vinafix.vn
Title
CPU(VSS)
Size Document Number Rev
A3 LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 10 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Reserved)

B B

BOM

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title
XDP

www.vinafix.vn
Size Document Number Rev
LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 11 of 103
5 4 3 2 1
5 4 3 2 1

VREF circuit -M1 (Voltage Driver Network) & M3 (Driven by Processor) Implementation

For CRV:
R1226

2
1 DY 2
SA_DIMM_VREFDQ R1228
Do Not Stuff
Do Not Stuff

Driven by process (PIN#B4) DY


D U1203 D

1
9 DDR_W R_VREF01 4 3 DDR_W R_VREF01_B4

20,37 DRAMRST_CNTRL_PCH 5 2 DRAMRST_CNTRL_PCH 20,37


DDR_W R_VREF01_D1 6 1 DDR_W R_VREF02 9
84.2N702.A3F 2N7002KDW -GP

1
2nd = 84.2N702.F3F Driven by process (PIN#D1)
R1227

1
R1208
2
Do Not Stuff DY SB_DIMM_VREFDQ

2
Do Not Stuff
DY

SIV

DDR_W R_VREF01_B4

C C
DDR_VREF_S3 1D5V_S3 DDR_VREF_S3 1D5V_S3 TP1201
Do Not Stuff

R1222
2

1
1

1
R1231 R1204 R1232 1 2 +V_SM_VREF 37
Do Not Stuff R1201 DY Do Not Stuff Do Not Stuff R1212
Do Not Stuff DY Do Not Stuff DY Do Not Stuff
1

1
R1203 R1213
2

2
M3_1D5V_DQ0 1 2 M_VREF_DQ_DIMM0 1 2 M_VREF_CA_DIMM0

1
Do Not Stuff Do Not Stuff
1

R1211 C1207
1

1
R1202 Do Not Stuff DY SCD1U10V2KX-4GP

2
1
Do Not Stuff DY C1201 C1205 C1203
SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP R1217
2

2
Do Not Stuff
2

2
1

R1209 R1219
DDR_VREF_S3 1D5V_S3 DDR_W R_VREF01_B4
DY Do Not Stuff 1 2

Do Not Stuff
DY
2

DDR_VREF_S3 1D5V_S3 R1220


2

M_VREF_CA_DIMM 1 2 DDR_W R_VREF01_D1


1

B R1230 B
Do Not Stuff R1205 Do Not Stuff
DY

1
Do Not Stuff DY

1
R1229 R1218
1

Do Not Stuff R1214 Do Not Stuff


R1207
2

M3_1D5V_DQ1
DY Do Not Stuff DY
1 2 M_VREF_DQ_DIMM1

2
R1216

2
Do Not Stuff
1

+V_VREF_VD2 1 2 M_VREF_CA_DIMM1
1

R1206

1
Do Not Stuff DY C1202 C1206
SCD1U10V2KX-4GP SCD1U10V2KX-4GP R1215 Do Not Stuff
2

1
Do Not Stuff DY C1204
2

SCD1U10V2KX-4GP C1208
SCD1U10V2KX-4GP

2
1

R1210
DY Do Not Stuff
2

SIV

DDR_W R_VREF01_D1

A BOM A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

www.vinafix.vn
Title
M1 & M3 Implementation
Size Document Number Rev
LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 12 of 103
5 4 3 2 1
5 4 3 2 1

D D

C C

(Blanking)

B B

BOM

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title
Reserved

www.vinafix.vn
Size Document Number Rev
LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 13 of 103
5 4 3 2 1
5 4 3 2 1

DIMM1
SSID = MEMORY M_A_A0 98 A0 NP1 NP1
M_A_A1 97 NP2
M_A_A2 A1 NP2
M_A_A[15:0] 6 96 A2
M_A_A3 95 110 M_A_RAS# 6
M_A_A4 A3 RAS#
92 A4 WE# 113 M_A_WE# 6
M_A_A5 91 115 M_A_CAS# 6
M_A_A6 A5 CAS#
M_A_A7
90 A6 Note:
86 A7 CS0# 114 M_A_DIM0_CS#0 6
M_A_A8 89 121 M_A_DIM0_CS#1 6
If SA0 DIM0 = 0, SA1_DIM0 = 0
M_A_A9 A8 CS1#
85 A9 RN1401 SO-DIMMA SPD Address is 0xA0
D M_A_A10 107 73 M_A_DIM0_CKE0 6 D
A10/AP CKE0
M_A_A11 84 A11 CKE1 74 M_A_DIM0_CKE1 6 SA0_DIM0 2 3 SO-DIMMA TS Address is 0x30
M_A_A12 83 SA1_DIM0 1 4
M_A_A13 A12
119 A13 CK0 101 M_A_DIM0_CLK_DDR0 6
M_A_A14 80 A14 CK0# 103 M_A_DIM0_CLK_DDR#0 6 SRN10KJ-5-GP
If SA0 DIM0 = 1, SA1_DIM0 = 0
M_A_A15 78
79
A15
102 SIV SO-DIMMA SPD Address is 0xA2
6 M_A_BS2 A16/BA2 CK1 M_A_DIM0_CLK_DDR1 6
CK1# 104 M_A_DIM0_CLK_DDR#1 6 SO-DIMMA TS Address is 0x32
6 M_A_BS0 109 BA0
6 M_A_BS1 108 BA1 DM0 11
6 M_A_DQ[63:0] DM1 28
M_A_DQ0 5 46
M_A_DQ1 DQ0 DM2
7 DQ1 DM3 63
M_A_DQ2 15 136
M_A_DQ3 DQ2 DM4
17 DQ3 DM5 153
M_A_DQ4 4 170
M_A_DQ5 DQ4 DM6
6 DQ5 DM7 187
M_A_DQ6 16
M_A_DQ7 DQ6
18 DQ7 SDA 200 PCH_SMBDATA 15,20,65,69
M_A_DQ8
M_A_DQ9
M_A_DQ10
21
23
DQ8
DQ9
SCL 202 PCH_SMBCLK 15,20,65,69
3D3V_S0
Thermal EVENT
33 DQ10 EVENT# 198 TS#_DIMM0_1 15
M_A_DQ11 35 3D3V_S0
M_A_DQ12 DQ11
22 DQ12 VDDSPD 199
M_A_DQ13 24 TS#_DIMM0_1 1R1403 2
M_A_DQ14 DQ13 SA0_DIM0 10KR2J-3-GP
34 DQ14 SA0 197

1
M_A_DQ15 36 201 SA1_DIM0 C1402
DQ15 SA1 C1401
M_A_DQ16 39 Do Not Stuff
DQ16 SCD1U10V2KX-5GP
M_A_DQ17 41 77

2
M_A_DQ18 51
DQ17 NC#77
122 DY
M_A_DQ19 DQ18 NC#122 1D5V_S3
53 DQ19 NC#125/TEST 125
M_A_DQ20 40
M_A_DQ21 DQ20
42 DQ21 VDD 75
M_A_DQ22 50 76
M_A_DQ23 DQ22 VDD
52 81
C M_A_DQ24 57
DQ23 VDD
82 SODIMM A DECOUPLING C
M_A_DQ25 DQ24 VDD 1D5V_S3
59 DQ25 VDD 87
M_A_DQ26 67 88
M_A_DQ27 DQ26 VDD
69 DQ27 VDD 93
M_A_DQ28 56 94
M_A_DQ29 DQ28 VDD
58 DQ29 VDD 99
M_A_DQ30 68 100

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
DQ30 VDD

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
M_A_DQ31

C1403

C1404

C1405

C1406

C1407

C1408

C1409

C1410
70 DQ31 VDD 105

1
M_A_DQ32 129 106 TC1401
M_A_DQ33 DQ32 VDD
131 111 SE390U2D5VM-12-GP
M_A_DQ34 DQ33 VDD
141 DQ34 VDD 112

2
M_A_DQ35 143 117 77.53971.01L
M_A_DQ36 DQ35 VDD
130 DQ36 VDD 118
M_A_DQ37 132 123
M_A_DQ38 140
DQ37 VDD
124 DY DY DY DY
M_A_DQ39 DQ38 VDD SIT
142 DQ39
M_A_DQ40 147 2
M_A_DQ41 DQ40 VSS
149 DQ41 VSS 3
M_A_DQ42 157 8

SCD1U10V2KX-5GP
M_A_DQ43 DQ42 VSS

C1414

C1415

C1416

C1417
159 9

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
DQ43 VSS

1
M_A_DQ44 146 13 Layout Note:
M_A_DQ45 DQ44 VSS
0D75V_S0 Place these caps M_A_DQ46
148 DQ45 VSS 14
Place these Caps near
158 19

2
close to VTT1 and M_A_DQ47 DQ46 VSS
160 DQ47 VSS 20 SO-DIMMB.
M_A_DQ48 163 25
VTT2. M_A_DQ49 DQ48 VSS
165 DQ49 VSS 26
M_A_DQ50 175 31
M_A_DQ51 DQ50 VSS
177 32
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

DQ51 VSS
Do Not Stuff

Do Not Stuff

M_A_DQ52
C1419

C1420

C1421

C1422

164 DQ52 VSS 37


1

M_A_DQ53 166 38
C1418 DQ53 VSS
M_A_DQ54 174 43
M_A_DQ55 DQ54 VSS
176 44
2

DQ55 VSS
Do Not Stuff

M_A_DQ56 181 48
M_A_DQ57 DQ56 VSS
183 DQ57 VSS 49
M_A_DQ58 191 54
B DY DY M_A_DQ59 193
DQ58 VSS
55 B
DY M_A_DQ60 DQ59 VSS
180 DQ60 VSS 60
M_A_DQ61 182 61
M_A_DQ62 DQ61 VSS
192 DQ62 VSS 65
M_A_DQ63 194 66
DQ63 VSS
VSS 71
M_A_DQS#0 10 72
M_A_DQS#1 DQS0# VSS
27 DQS1# VSS 127
M_A_DQS#2 45 128
M_A_DQS#3 DQS2# VSS
62 DQS3# VSS 133
M_A_DQS#4 135 134
M_A_DQS#5 DQS4# VSS
152 DQS5# VSS 138
M_A_DQS#[7:0] 6 M_A_DQS#6 169 139
M_A_DQS#7 DQS6# VSS
186 DQS7# VSS 144
M_A_DQS[7:0] 6 VSS 145
M_A_DQS0 12 150
M_A_DQS1 DQS0 VSS
29 DQS1 VSS 151
M_A_DQS2 47 155
M_A_DQS3 DQS2 VSS
64 DQS3 VSS 156
M_A_DQS4 137 161
M_A_DQS5 DQS4 VSS
154 DQS5 VSS 162
M_A_DQS6 171 167
M_A_DQS7 DQS6 VSS
188 DQS7 VSS 168
VSS 172
6 M_A_DIM0_ODT0 116 ODT0 VSS 173
6 M_A_DIM0_ODT1 120 ODT1 VSS 178
VSS 179
M_VREF_CA_DIMM0 126 VREF_CA VSS 184
M_VREF_DQ_DIMM0 1 VREF_DQ VSS 185
VSS 189
15,37 DDR3_DRAMRST# 30 RESET# VSS 190
VSS 195
VSS 196
0D75V_S0 203 VTT1 VSS 205
204 VTT2 VSS 206
A A
1

FC1402
DY DDR3-240P-28-GP
Do Not Stuff

BOM
2

62.10017.R91
SIT
BOM_CTRL Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

www.vinafix.vn
1st = 62.10017.V61 Taipei Hsien 221, Taiwan, R.O.C.
2nd = 62.10017.X51 Title
3rd = 62.10017.R91
DDR3-SODIMM1
Size Document Number Rev

After layout, BOM change P/N


LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 14 of 103
5 4 3 2 1
5 4 3 2 1

SSID = MEMORY DIMM2

M_B_A0 98 NP1
M_B_A1 A0 NP1
97 A1 NP2 NP2
M_B_A[15:0] 6 M_B_A2 96
M_B_A3 A2
95 A3 RAS# 110 M_B_RAS# 6
M_B_A4 92 113 M_B_WE# 6
M_B_A5 A4 WE#
91 A5 CAS# 115 M_B_CAS# 6
M_B_A6 90
M_B_A7 A6
86 A7 CS0# 114 M_B_DIM0_CS#0 6
M_B_A8 89 121 M_B_DIM0_CS#1 6
M_B_A9 A8 CS1#
85 A9
D M_B_A10 107 73 M_B_DIM0_CKE0 6 D
M_B_A11 A10/AP CKE0
84 A11 CKE1 74 M_B_DIM0_CKE1 6
M_B_A12 83 A12
M_B_A13 119 A13 CK0 101 M_B_DIM0_CLK_DDR0 6 SIV
M_B_A14 80 103 M_B_DIM0_CLK_DDR#0 6 Note:
M_B_A15 A14 CK0# 3D3V_S0
78 A15
6 M_B_BS2 79 A16/BA2 CK1 102 M_B_DIM0_CLK_DDR1 6 RN1501
SO-DIMMB SPD Address is 0xA4
CK1# 104 M_B_DIM0_CLK_DDR#1 6 SO-DIMMB TS Address is 0x34
109 SA1_DIM1 2 3
6 M_B_BS0 BA0 SA0_DIM1
6 M_B_BS1 108 BA1 DM0 11 1 4
6 M_B_DQ[63:0] DM1 28
M_B_DQ0 5 46 SO-DIMMB is placed farther from
M_B_DQ1 DQ0 DM2 SRN10KJ-5-GP
7 DQ1 DM3 63
M_B_DQ2 15 136 the Processor than SO-DIMMA
M_B_DQ3 DQ2 DM4
17 DQ3 DM5 153
M_B_DQ4 4 170
M_B_DQ5 DQ4 DM6
6 DQ5 DM7 187
M_B_DQ6 16
M_B_DQ7 DQ6
18 DQ7 SDA 200 PCH_SMBDATA 14,20,65,69
M_B_DQ8 21 202
DQ8 SCL PCH_SMBCLK 14,20,65,69
M_B_DQ9 23
M_B_DQ10 DQ9 3D3V_S0
33 DQ10 EVENT# 198 TS#_DIMM0_1 14
M_B_DQ11 35
M_B_DQ12 DQ11
22 DQ12 VDDSPD 199
M_B_DQ13 24 DQ13

1
M_B_DQ14 34 197 SA0_DIM1
M_B_DQ15 DQ14 SA0 SA1_DIM1 C1501 C1502
36 DQ15 SA1 201
M_B_DQ16 39 SCD1U10V2KX-5GP Do Not Stuff

2
M_B_DQ17 DQ16
41 77
M_B_DQ18 51
DQ17 NC#1
122 DY
M_B_DQ19 DQ18 NC#2 1D5V_S3
53 DQ19 NC#/TEST 125
M_B_DQ20 40
M_B_DQ21 DQ20
42 DQ21 VDD1 75
M_B_DQ22 50 76
M_B_DQ23 DQ22 VDD2
52 DQ23 VDD3 81
C M_B_DQ24 57 82 C
M_B_DQ25 DQ24 VDD4
59 DQ25 VDD5 87
M_B_DQ26 67 88
M_B_DQ27 DQ26 VDD6
69 DQ27 VDD7 93
M_B_DQ28 56 94
M_B_DQ29 DQ28 VDD8
58 DQ29 VDD9 99
M_B_DQ30 68 100
M_B_DQ31 DQ30 VDD10
70 DQ31 VDD11 105
M_B_DQ32 129 106
M_B_DQ33 DQ32 VDD12
131 DQ33 VDD13 111
M_B_DQ34 141 112
M_B_DQ35 DQ34 VDD14
143 DQ35 VDD15 117
M_B_DQ36 130 118
M_B_DQ37 DQ36 VDD16
132 DQ37 VDD17 123
M_B_DQ38 140 124
M_B_DQ39 DQ38 VDD18 1D5V_S3
142 DQ39
M_B_DQ40 147 2 SODIMM B DECOUPLING
M_B_DQ41 DQ40 VSS
149 DQ41 VSS 3
M_B_DQ42 157 8 SIV
M_B_DQ43 DQ42 VSS
159 DQ43 VSS 9
M_B_DQ44 146 13

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
DQ44 VSS

Do Not Stuff

Do Not Stuff

Do Not Stuff
M_B_DQ45 TC1502

C1503

C1504

C1505

C1506

C1507

C1508

C1509

C1510
148 DQ45 VSS 14

1
M_B_DQ46 158 19
M_B_DQ47 DQ46 VSS
160 DQ47 VSS 20
TC15xx DY DY DY DY DY

Do Not Stuff
M_B_DQ48 163 25

2
M_B_DQ49 DQ48 VSS
165 DQ49 VSS 26
M_B_DQ50
M_B_DQ51
175
177
DQ50
DQ51
VSS
VSS
31
32 330uF
M_B_DQ52 164 37
M_B_DQ53 DQ52 VSS
166 DQ53 VSS 38
M_B_DQ54 174 43
M_B_DQ55 DQ54 VSS
Place these caps M_B_DQ56
176 DQ55 VSS 44
181 48

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
0D75V_S0 close to VTT1 and M_B_DQ57 DQ56 VSS

C1511

C1512

C1513

C1514
183 DQ57 VSS 49

1
M_B_DQ58 191 54
VTT2. M_B_DQ59 DQ58 VSS
B 193 DQ59 VSS 55 B
M_B_DQ60 180 60

2
M_B_DQ61 DQ60 VSS
182 DQ61 VSS 61
M_B_DQ62
C1518

C1519

C1520

C1521

192 65
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

DQ62 VSS
1

1
Do Not Stuff

Do Not Stuff

M_B_DQ63 194 66
DQ63 VSS
DY M_B_DQS#0 VSS 71
10 72
2

M_B_DQS#1 DQS0# VSS


27 DQS1# VSS 127
M_B_DQS#2 45 128
M_B_DQS#3 DQS2# VSS
62 133
DY M_B_DQS#4 135
DQS3# VSS
134
M_B_DQS#5 DQS4# VSS
152 DQS5# VSS 138
M_B_DQS#6 169 139
M_B_DQS#7 DQS6# VSS
186 DQS7# VSS 144
VSS 145
M_B_DQS0 12 150
M_B_DQS1 DQS0 VSS
M_B_DQS#[7:0] 6 29 DQS1 VSS 151
M_B_DQS2 47 155
M_B_DQS3 DQS2 VSS
M_B_DQS[7:0] 6 64 DQS3 VSS 156
M_B_DQS4 137 161
M_B_DQS5 DQS4 VSS
154 DQS5 VSS 162
M_B_DQS6 171 167
M_B_DQS7 DQS6 VSS
188 DQS7 VSS 168
VSS 172
6 M_B_DIM0_ODT0 116 ODT0 VSS 173
6 M_B_DIM0_ODT1 120 ODT1 VSS 178
VSS 179
M_VREF_CA_DIMM1 126 VREF_CA VSS 184
M_VREF_DQ_DIMM1 1 VREF_DQ VSS 185
VSS 189
14,37 DDR3_DRAMRST# 30 RESET# VSS 190
VSS 195
VSS 196
0D75V_S0 203 VTT1 VSS 205

A
204 VTT2 VSS 206 After layout, BOM change P/N A

DDR3-204P-108-GP
BOM_CTRL
H = 8mm BOM
62.10017.X41

1st = 62.10024.G21
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

www.vinafix.vn
Taipei Hsien 221, Taiwan, R.O.C.
2nd = 62.10017.X41 Title
DDR3-SODIMM2
3rd = 62.10017.M51 Size Document Number Rev
LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 15 of 103
5 4 3 2 1
5 4 3 2 1

D D

(Blanking)
C C

B B

BOM

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A Taipei Hsien 221, Taiwan, R.O.C. A

Title
DDR3-SODIMM3

www.vinafix.vn
Size Document Number Rev
LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 16 of 103
5 4 3 2 1
5 4 3 2 1

L_DDC_DATA(K47):
This signal is on the LVDS interface.
This signal needs to be left NC if eDP is
3D3V_S0 used for the local flat panel display

RN1701 4 OF 10 3D3V_S0
PCH1D
1 4 L_CTRL_DATA 49 L_BKLT_EN J47 AP43
L_CTRL_CLK L_BKLTEN SDVO_TVCLKINN
2 3 49 LVDS_VDD_EN M45 L_VDD_EN SDVO_TVCLKINP AP45
D D

4
3
SRN2K2J-1-GP 49 L_BKLT_CTRL P45 L_BKLTCTL SDVO_STALLN AM42
AM40 RN1706
LVDS_DDC_CLK_R SDVO_STALLP
49 LVDS_DDC_CLK_R T40 L_DDC_CLK SRN2K2J-1-GP DDI Port B Detect:(SDVO_CTRL_ DATA)
LVDS_DDC_DATA_R K47 AP39
49 LVDS_DDC_DATA_R L_DDC_DATA SDVO_INTN 1: Port B detected
SDVO_INTP AP40
L_CTRL_CLK T45 0: Port B not detected

1
2
L_CTRL_DATA L_CTRL_CLK
P39 L_CTRL_DATA
R1704
LVDS_IBG AF37 P38
1 2 L_BKLT_EN LVD_IBG SDVO_CTRLCLK PCH_HDMI_CLK 51
Do Not Stuff TP1701 1 LVDS_VBG AF36 M39
LVD_VBG SDVO_CTRLDATA PCH_HDMI_DATA 51
100KR2J-1-GP

1
AE48 LVD_VREFH
R1701 AE47 AT49
R1703 2K37R2F-GP LVD_VREFL DDPB_AUXN
LVDS_VDD_EN AT47
1 2 Place near PCH DDPB_AUXP
AT40
10KR2J-3-GP DDPB_HPD HDMI_PCH_DET 51
49 LVDSA_CLK# AK39

2
LVDSA_CLK#

LVDS
49 LVDSA_CLK AK40 AV42 DDBP_DATA2# 1 2 C1701 SCD1U10V2KX-5GP HDMI_DATA2_R# 51
LVDSA_CLK DDPB_0N DDBP_DATA2 C1702 SCD1U10V2KX-5GP
DDPB_0P AV40 1 2 HDMI_DATA2_R 51
49 LVDSA_DATA0# AN48 AV45 DDBP_DATA1# 1 2 C1703 SCD1U10V2KX-5GP HDMI_DATA1_R# 51
LVDSA_DATA#0 DDPB_1N DDBP_DATA1 C1704 SCD1U10V2KX-5GP
SIT 49 LVDSA_DATA1# AM47 LVDSA_DATA#1 DDPB_1P AV46 1 2 HDMI_DATA1_R 51

Digital Display Interface


49 LVDSA_DATA2# AK47 AU48 DDBP_DATA0# 1 2 C1705 SCD1U10V2KX-5GP HDMI_DATA0_R# 51
LVDSA_DATA#2 DDPB_2N DDBP_DATA0 C1706 SCD1U10V2KX-5GP
AJ48 LVDSA_DATA#3 DDPB_2P AU47 1 2 HDMI_DATA0_R 51
AV47 DDBP_CLK# 1 2 C1707 SCD1U10V2KX-5GP HDMI_CLK_R# 51
DDPB_3N DDBP_CLK C1708 SCD1U10V2KX-5GP
49 LVDSA_DATA0 AN47 LVDSA_DATA0 DDPB_3P AV49 1 2 HDMI_CLK_R 51
49 LVDSA_DATA1 AM49 LVDSA_DATA1
49 LVDSA_DATA2 AK49 LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
C DDPC_CTRLDATA P42 C

AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
AH45 LVDSB_DATA#0 DDPC_HPD AT38 Impedance:100 ohm
AH47
AF49
LVDSB_DATA#1
AY47
Impedance:90 ohm
LVDSB_DATA#2 DDPC_0N
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 LVDSB_DATA1 DDPC_2N BA47
AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49
CRT_BLUE
CRT_GREEN
CRT_RED 50 CRT_BLUE N48 CRT_BLUE DDPD_CTRLCLK M43
50 CRT_GREEN P49 CRT_GREEN DDPD_CTRLDATA M36
50 CRT_RED T49 CRT_RED

DDPD_AUXN AT45

CRT
50 CRT_DDC_CLK T39 CRT_DDC_CLK DDPD_AUXP AT43
M40 BH41
5
6
7
8

50 CRT_DDC_DATA CRT_DDC_DATA DDPD_HPD


RN1705
SRN150F-1-GP DDPD_0N BB43
50 CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
Close to PCH side 50 CRT_VSYNC M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
4
3
2
1

B
DDPD_2N BF42 B
DAC_IREF_R T43 BE42
DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
1

DDPD_3P BG42
R1702
Notes: 1KR2D-1-GP PANTHER-GP-NF

1K 0.5% 0402. BOM_CTRL


2

SIV = 71.PANTH.D0U
鎖料: 71.PANTH.D0U
PCH鎖

A BOM A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

www.vinafix.vn
Title
PCH ( LVDS/CRT/HDMI )
Size Document Number Rev
LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 17 of 103
5 4 3 2 1
5 4 3 2 1

SSID = PCH
PCH1E 5 OF 10 1D8V_S0
RSVD1 AY7
RSVD2 AV7
BG26 AU3

1
TP1 RSVD3 Danbury Technology:
3D3V_S0 BJ26 BG4 R1810
BH25
TP2 RSVD4 Disabled when Low.
Do Not Stuff
For intel check list BJ16
TP3
AT10 Enable when High. DY
TP4 RSVD5
3D3V_S0 BG16 TP5 RSVD6 BC8

2
RN1801 AH38

2
D DBC_EN TP6 D
1 10 3D3V_S0 AH37 TP7 RSVD7 AU2 NV_ALE
INT_PIRQB# 2 9 INT_PIRQD# DY AK43 AT4

2
R1821 TP8 RSVD8
INT_PIRQF# 3 8 INT_PIRQE# AK45 AT3
Do Not Stuff TP9 RSVD9
INT_PIRQA# 4 7 INT_PIRQC# C18 AT1
R1820 DY TP10 RSVD10
INT_PIRQG#

1
3D3V_S0 5 6 Do Not Stuff N30 TP11 RSVD11 AY3
H3 TP12 RSVD12 AT5

1
SRN8K2J-2-GP-U DGPU_PW R_EN# DGPU_HOLD_RST# AH12 AV3
TP13 RSVD13
AM4 TP14 RSVD14 AV1
AM5 BB1

2
TP15 RSVD15
R1818 R1817 Y13 TP16 RSVD16 BA3
10KR2J-3-GP 10KR2J-3-GP K24 TP17 RSVD17 BB5
L24 TP18 RSVD18 BB3
AB46 TP19 RSVD19 BB7

1
DY AB45 TP20 RSVD20 BE8

RSVD
R1801 2 1 Do Not Stuff PCI_GNT3# BD4
RSVD21
RSVD22 BF6

B21 AV5 NV_ALE


TP21 RSVD23 NV_RCOMP
A16 swap override Strap/Top-Block M20 TP22 RSVD24 AV10 1 TP1803 Do Not Stuff
AY16
Swap Override jumper TP23
For PPT USB3.0 feature BG46 TP24 RSVD25 AT8

PCI_GNT#3 Low = A16 swap (For LG4858L) RSVD26 AY5


BA2
override/Top-Block BE28
RSVD27
Swap Override enabled 62 USB3_2_RX4_N USB3RN1
62 USB3_1_RX2_N BC30 USB3RN2 RSVD28 AT12
High = Default BE32 USB3RN3 RSVD29 BF3
BJ32 USB3RN4
C 62 USB3_2_RX4_P BC28 USB3RP1 C
62 USB3_1_RX2_P BE30 USB3RP2
BF32
BG32
AV26
USB3RP3
USB3RP4 USBP0N C24
A24
USB_PN3
USB_PP3
USB_PN3 62
USB Table
(For LG4858L)
62 USB3_2_TX4_N USB3TN1 USBP0P USB_PP3 62
62 USB3_1_TX2_N BB26 C25 USB_PN1 USB_PN1 62
AU28
USB3TN2 USBP1N
B25 USB_PP1 Pair Device
USB3TN3 USBP1P USB_PP1 62
AY30 C26 USB_PN2 USB_PN2 82
DY AU26
USB3TN4 USBP2N
A26 USB_PP2 0 USB3.0 ext port 2
62 USB3_2_TX4_P USB3TP1 USBP2P USB_PP2 82
R1802 1 2 Do Not Stuff BBS_BIT1 62 USB3_1_TX2_P AY26 K28 USB_PN12 49
AV28
USB3TP2 USBP3N
H28 1 USB3.0 ext port 1
USB3TP3 USBP3P USB_PP12 49
R1803 1 2 Do Not Stuff BBS_BIT0 AW30 E28
BBS_BIT0 21 USB3TP4 USBP4N
D28 2 USB2.0 ext port 4
DY 3D3V_S0 USBP4P
C28
USBP5N
A28 3 CAMERA
USBP5P
C29
USBP6N
B29 4 X
G58B R1814 USBP6P
2
BOOT BIOS Strap INT_PIRQA# K40 N28 X
Do Not Stuff
INT_PIRQB# K38
PIRQA# USBP7N
M28 5
GNT1#/GPIO51 SATA1GP/GPIO19 BOOT BIOS Location PIRQB# USBP7P

PCI
Do Not Stuff TP1808 1 DY INT_PIRQC# H38 L30 USB_PN4 USB_PN4 63
INT_PIRQD# G38
PIRQC# USBP8N
K30 USB_PP4 6 X
PIRQD# USBP8P USB_PP4 63
0 0 LPC G30 USB_PN9 82 7 X
1

DGPU_HOLD_RST# USBP9N
C46 REQ1#/GPIO50 USBP9P E30 USB_PP9 82

USB
0 1 Reserved Do Not Stuff TP1805 1 DGPU_SELECT# C44 REQ2#/GPIO52 USBP10N C30 USB_PN5 82 8 BLUETOOTH
Do Not Stuff TP1807 1 DGPU_PW R_EN# E40 A30 USB_PP5 82
REQ3#/GPIO54 USBP10P
1 0 Reserved USBP11N L32 USB_PN11 65 9 USB2.0 ext port 3
G58B BBS_BIT1 D47 K32 USB_PP11 65
GNT1#/GPIO51 USBP11P
1 1 SPI(Default) DGPU_PW M_SELECT# E42 GNT2#/GPIO53 USBP12N G32
10 CARD READER
Do Not Stuff TP18011 PCI_GNT3# F46 GNT3#/GPIO55 USBP12P E32
B 20110714 C32 B
Do Not Stuff
USBP13N
A32 11 WLAN(Bluetooth)
INT_PIRQE# USBP13P
G42
3D3V_S0
DY 1 R1813 2 INT_PIRQF# G40
PIRQE#/GPIO2 12 X
20110727 for DANNY 27,56 SATA_ODD_DA# PIRQF#/GPIO3
Do Not Stuff TP1804 1 INT_PIRQG# C42 C33 USB_RBIAS 1 2
DBC_EN D44
PIRQG#/GPIO4 USBRBIAS# R1811 13 X
SIV PIRQH#/GPIO5 22D6R2F-L1-GP
B33
Utilize Port 9 for USB debug
2

USBRBIAS
R1819 Do Not Stuff TP1802 1 PCI_PME# K10 PME#
10KR2J-3-GP
PCI_PLTRST# C6 A14 USB_OC#0_1 USB_OC#0_1 62 USB3.0 port1
PLTRST# OC0#/GPIO59 USB_OC#2_3
OC1#/GPIO40 K20
USB_OC#4_5
USB_OC#2_3 61 USB2.0 port4
1

R1804 1 OC2#/GPIO41 B17 USB_OC#4_5 62 USB3.0 port2


65 CLK_PCI_LPC 2 22R2J-2-GP CLK_PCI_LPC_R H49 CLKOUT_PCI0 OC3#/GPIO42 C16 USB_OC#6_7
20 CLK_PCI_FB R1805 1 2 22R2J-2-GP CLK_PCI_FB_R H43 L16 USB_OC#8_9 USB_OC#8_9 61 USB2.0 port3
DGPU_PW M_SELECT# CLKOUT_PCI1 OC4#/GPIO43
27 CLK_PCI_KBC R1806 1 233R2J-2-GP CLK_PCI_KBC_R J48 A16 USB_OC#10_11
CLKOUT_PCI2 OC5#/GPIO9
TP1806 1 PCH_CLK_PCI3 K42 CLKOUT_PCI3 OC6#/GPIO10 D14 USB_OC#12_13
H40 C14 PCH_GPIO14
110706 DY DY CLKOUT_PCI4 OC7#/GPIO14
2

Do Not Stuff
EC1802 EC1801
Do Not Stuff Do Not Stuff PANTHER-GP-NF
1

20110727 for vendor


鎖料: 71.PANTH.00U
PCH鎖 OC[3:0]# for Device 29 (Ports 0-7)
OC[7:4]# for Device 26 (Ports 8-13)
R1807

5,27,31,36,65,97 PLT_RST# 1 2 PCI_PLTRST#

Do Not Stuff
A BOM A
DY
1

DY
1

RN1802
R1816 C1801
Do Not Stuff Do Not Stuff USB_OC#2_3
PCH_GPIO14
1 10
USB_OC#12_13
3D3V_S5 Wistron Corporation
2

2 9 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


USB_OC#6_7 3 8 USB_OC#8_9 Taipei Hsien 221, Taiwan, R.O.C.
2

USB_OC#0_1 4 7 USB_OC#10_11
USB_OC#4_5

www.vinafix.vn
3D3V_S5 5 6 Title
SRN10KJ-L3-GP
PCH ( PCI/USB/NVRAM)
Size Document Number Rev
LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 18 of 103
5 4 3 2 1
5 4 3 2 1

SSID = PCH 4 DMI_RXN[3:0]


4 DMI_RXP[3:0] FDI_TXN[7:0] 4
FDI_TXP[7:0] 4
Do Not Stuff
DY 4 DMI_TXN[3:0]
2 1 R1932 DMI_RXN3 4 DMI_TXP[3:0]
Do Not Stuff 2 1 R1900 DMI_RXP3 PCH1C 3 OF 10

DY 4 DMI_RXN0 BC24 DMI0RXN FDI_RXN0 BJ14 FDI_TXN0 4


4 DMI_RXN1 BE20 DMI1RXN FDI_RXN1 AY14 FDI_TXN1 4
4 DMI_RXN2 BG18 DMI2RXN FDI_RXN2 BE14 FDI_TXN2 4
D 4 DMI_RXN3 R1903 1 2 DMI_RXN3_R BG20 BH13 FDI_TXN3 4 D
Do Not Stuff DMI3RXN FDI_RXN3
FDI_RXN4 BC12 FDI_TXN4 4
4 DMI_RXP0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_TXN5 4
4 DMI_RXP1 BC20 DMI1RXP FDI_RXN6 BG10 FDI_TXN6 4
4 DMI_RXP2 BJ18 DMI2RXP FDI_RXN7 BG9 FDI_TXN7_L1 2 FDI_TXN7 4
4 DMI_RXP3 R1906 1 2 DMI_RXP3_R BJ20 R1934 0R2J-2-GP
Do Not Stuff DMI3RXP
FDI_RXP0 BG14 FDI_TXP0 4
Signal Routing Guideline: 4 DMI_TXN0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_TXP1 4 For platforms not supporting Deep S4/S5
4 DMI_TXN1 AW20 BF14 FDI_TXP2 4
DMI_ZCOMP keep W=4 mils and 4 DMI_TXN2 BB18
DMI1TXN
DMI2TXN
FDI_RXP2
FDI_RXP3 BG13 FDI_TXP3 4 1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)
routing length less than 500 AV18 BE12
4 DMI_TXN3 DMI3TXN FDI_RXP4 FDI_TXP4 4
2.DPWROK and RSMRST# will rise at the same time (connected on board)

DMI
FDI
mils. FDI_RXP5 BG12 FDI_TXP5 4
AY24 BJ10
DMI_IRCOMP keep W=4 mils and 4
4
DMI_TXP0
DMI_TXP1 AY20
DMI0TXP FDI_RXP6
BH9 FDI_TXP7_L 1 2
FDI_TXP6
FDI_TXP7
4
4
3.SLP_SUS# and SUSACK# are left as ‘no connect’
routing length less than 500 DMI1TXP FDI_RXP7 R1933 0R2J-2-GP
AY18
mils.
4
4
DMI_TXP2
DMI_TXP3 AU18
DMI2TXP 4.SUSWARN# used as SUSPWRDNACK/GPIO30
DMI3TXP
FDI_INT AW16 FDI_INT 4
1D05V_VTT BJ24 AV12
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 4
R1901 1 2 49D9R2F-GP DMI_COMP_R BG25 BC10 FDI_FSYNC1 4
DMI_IRCOMP FDI_FSYNC1
R1902 1 2 750R2F-GP RBIAS_CPY BH21 AV14 FDI_LSYNC0 4
DMI2RBIAS FDI_LSYNC0
FDI_TXN7 R1935 1
DY
FDI_LSYNC1 BB10 FDI_LSYNC1 4 2Do Not Stuff

DY 1 TP1937 Do Not Stuff 1 TP1933 Do Not Stuff FDI_TXP7 R1936 1 2Do Not Stuff
1 2 R1926 SYS_PW ROK
Do Not Stuff
DSWVRMEN A18 DSW ODVREN Do Not Stuff R1910
DY
C 1 2 R1904 PW ROK 1 2 PM_RSMRST# C
100KR2J-1-GP DY

System Power Management


SUS_PW R_ACK R1927 1 2Do Not Stuff SUSACK# C12 E22 PCH_DPW ROK 1 R1911 2 Do Not Stuff RTC_AUX_S5
SUSACK# DPWROK
DY
DY R1928 Do Not Stuff
5 XDP_DBRESET# R1925 1 2Do Not Stuff SYS_RESET# K3 B9 PCIE_W AKE#_P 1 2 PCIE_W AKE# 31,65
SYS_RESET# WAKE#

3D3V_S0 R1905 1 2 10KR2J-3-GP


36 SYS_PW ROK P12 SYS_PWROK CLKRUN#/GPIO32 N3 PM_CLKRUN# 27
1 Do Not Stuff TP1936 1 1R1923 2
Do Not Stuff TP1935
Do Not Stuff R1924 DY Do Not Stuff
27,36 S0_PW R_GOOD 1 2 PW ROK L22 PWROK SUS_STAT#/GPIO61 G8 PM_SUS_STAT# 1 TP1901 TPAD14-OP-GP
R1930 1 2 0R2J-2-GP
R1913
45,46,47 RUNPW ROK 1 2 MEPW ROK L10 N14 SUS_CLK 1 2 PCH_SUSCLK_KBC 27
APWROK SUSCLK/GPIO62
R1929 DY Do Not Stuff
Do Not Stuff
DSWODVREN - On Die DSW VR Enable
Do Not Stuff TP1934 1
5,37 PM_DRAM_PW RGD B13 D10 PM_SLP_S5# 1 TP1902 Do Not Stuff 1 TP1938 Do Not Stuff HIGH Enabled (DEFAULT)
DRAMPWROK SLP_S5#/GPIO63
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
R1914 Do Not Stuff LOW Disabled
Do Not Stuff TP1932 1 PM_RSMRST# C21 H4 SLP_S4#_R 1 2 PM_SLP_S4# 27,46
RSMRST# SLP_S4#

R1915 Do Not Stuff


27 SUS_PW R_ACK SUS_PW R_ACK K16 F4 SLP_S3#_R 1 2 PM_SLP_S3# 27,36,37,47
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# RTC_AUX_S5
1 2
PM_SLP_A#
R1991 DY Do Not Stuff
27,97 PM_PW RBTN# E20 PWRBTN# SLP_A# G10 1 TP1939 Do Not Stuff
1 R1917
2
1 Do Not Stuff 330KR2J-L1-GP
B TP1940 B
27 ACPRESENT H20 G16 PM_SLP_SUS# 1 TP1904 Do Not Stuff
ACPRESENT/GPIO31 SLP_SUS# DSW ODVREN R1918 1 2 Do Not Stuff

BATLOW # E10 AP14 H_PM_SYNC


H_PM_SYNC 5
DY
BATLOW#/GPIO72 PMSYNCH

PM_RI# A10 K14 PM_SLP_LAN# 1 TP1931 Do Not Stuff


RI# SLP_LAN#/GPIO29

PANTHER-GP-NF

3D3V_S5 鎖料: 71.PANTH.00U


PCH鎖 3D3V_S0

R1919
PM_CLKRUN# 1 2 10KR2J-3-GP

3D3V_AUX_S5
RN1901
8 1 BATLOW # R1909
7 2 PM_RI#
ACPRESENT 2 1
6 3 100KR2J-1-GP
PCIE_W AKE# 20110728 for vendor
5 4 PCH_WAKE#
2

SRN10KJ-6-GP SIV CRB : 1K R1916


Q1901 R1912
DY
2
R1921
1 Do Not Stuff SUS_PW R_ACK CHKLIST: 10K 10KR2J-3-GP
4 3 PM_RSMRST# 1 2 RSMRST#_KBC 27
1KR2J-1-GP
1

3V_5V_POK_# 5 2 3V_5V_POK 41
A 2 R1922 1 Do Not Stuff PM_PW RBTN# BOM A
DY 6 1

2 R1920 1 Do Not Stuff PM_SLP_LAN# 2N7002KDW -GP Wistron Corporation


SIV For intel 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
DY Taipei Hsien 221, Taiwan, R.O.C.
84.2N702.A3F

www.vinafix.vn
Title
R1908 2nd = 84.2N702.F3F PCH (DMI/FDI/PM)
2 1 10KR2J-3-GP PM_RSMRST#
Size Document Number Rev
LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 19 of 103
5 4 3 2 1
5 4 3 2 1

3D3V_S5 3D3V_S5
SSID = PCH SMB_CLK 4 1 RN2003

1
SMB_DATA 3 2 SRN2K2J-1-GP
R2004
10KR2J-3-GP
SML0_DATA 3 2 RN2004
PCH1B 2 OF 10 SML0_CLK 4 1 SRN2K2J-1-GP

2
Do Not Stuff TP2004 1 PCIE_RXN1 BG34 PEG_CLKREQ#_R SML1_CLK 2 3 RN2005
PCIE_RXP1 PERN1 EC_SW I# SML1_DATA
Do Not Stuff TP2005 1 BJ34 PERP1 SMBALERT#/GPIO11 E12 1 TP2015 Do Not Stuff 1 4 SRN2K2J-1-GP

1
Do Not Stuff TP2006 1 PCIE_TXN1_C AV32
PCIE_TXP1_C PETN1
Do Not Stuff TP2007 1 AU32 PETP1 W-WAN SMBCLK H14 SMB_CLK DY R2005
Do Not Stuff
PCIE_CLK_REQ6#
PCH_GPIO74
1
2
4 RN2006
3 SRN10KJ-5-GP
D BE34 C9 SMB_DATA D
65 PCIE_RXN2 PERN2 SMBDATA
65 PCIE_RXP2 BF34

2
C2001 PERP2
65 PCIE_TXN2 1 2 SCD1U10V2KX-5GP PCIE_TXN2_C BB32 PETN2 WLAN
C2002 2 SCD1U10V2KX-5GP PCIE_TXP2_C
65 PCIE_TXP2 1 AY32 PETP2 20110715

SMBUS
A12 DRAMRST_CNTRL_PCH R2009
SML0ALERT#/GPIO60 DRAMRST_CNTRL_PCH 12,37 3D3V_S0 DRAMRST_CNTRL_PCH 1
BG36 PERN3 2
BJ36 C8 SML0_CLK RN2007 1KR2J-1-GP
PERP3 SML0CLK
AV34 PETN3 2 3
AU34 G12 SML0_DATA 1 4
PETP3 SML0DATA
CRB: 1K
BF36 SRN2K2J-1-GP
31 PCIE_RXN4
BE36
PERN4 CHKLT: 10K
31 PCIE_RXP4 PERP4
C2005 2 SCD1U10V2KX-5GP PCIE_TXN4_C
31 PCIE_TXN4 C2006
1
1 2 SCD1U10V2KX-5GP PCIE_TXP4_C
AY34
BB34
PETN4 LAN SML1ALERT#/PCHHOT#/GPIO74 C13 PCH_GPIO74
31 PCIE_TXP4 PETP4 SML1_CLK
SML1CLK/GPIO58 E14 SML1_CLK 27 2N7002KDW -GP

PCI-E*
BG37 PERN5
BH37 M16 SML1_DATA SMB_DATA 6 1
PERP5 SML1DATA/GPIO75 SML1_DATA 27 PCH_SMBDATA 14,15,65,69
AY36 PETN5
BB36 PETP5 5 2

BJ38 PERN6 4 3
BG38 PERP6 CL_CLK
84.2N702.A3F

Controller
AU36 PETN6 CL_CLK1 M7 1 TP2001 Do Not Stuff Q2001
AV36 PETP6 2nd = 84.2N702.F3F
PCH_SMBCLK 14,15,65,69

Link
BG40 T11 CL_DATA 1 TP2002 Do Not Stuff
PERN7 CL_DATA1 SMB_CLK
BJ40 PERP7
AY40 PETN7
BB40 P10 CL_RST# 1 TP2003 Do Not Stuff
C PETP7 CL_RST1# XTAL25_IN 1 DY 2 C
BE38 R2008 Do Not Stuff
PERN8
BC38 PERP8
R2008 and C2008 CO-LAY SIT
AW38 PETN8
AY38 C2008
PETP8 XTAL25_IN 2 1
PEG_A_CLKRQ#/GPIO47 M10

2
Y40 SC12P50V2JN-3GP
CLKOUT_PCIE0N
WWAN CLK Y39 G58B R2006 X2001
CLKOUT_PCIE0P 1M1R2J-GP
CLKOUT_PEG_A_N AB37 XTAL-25MHZ-102-GP
CLK_PCIE_W W AN_REQ# J2

CLOCKS
AB38

1
PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P 82.30020.851 C2007

1
RN2023 RN2025 XTAL25_OUT 2nd = 82.30020.791 2 1
1 4 CLK_PCH_SRC1_N AB49 AV22 CLKOUT_DMI_N 2 3
WLAN CLK65
65 CLK_PCIE_W LAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_EXP_N 5
CLK_PCIE_W LAN 2 3 CLK_PCH_SRC1_P AB47 AU22 CLKOUT_DMI_P 1 4 CLK_EXP_P 5 SC15P50V2JN-2-GP
SRN0J-6-GP CLKOUT_PCIE1P CLKOUT_DMI_P SRN0J-6-GP
65 CLK_PCIE_W LAN_REQ# M1 RN2017
PCIECLKRQ1#/GPIO18 CLKOUT_DP_N
CLKOUT_DP_N AM12 1 4 CLK_DP_N_R 5
CLKOUT_DP_P AM13 CLKOUT_DP_P 2 3 CLK_DP_P_R 5 DGPU_PRSNT#,UMA_DIS#
AA48 Do Not Stuff 3D3V_S0 3D3V_S0
CLKOUT_PCIE2N UMA: 1 1
AA47 CLKOUT_PCIE2P DY DIS : 0 1
20110708 CLKIN_DMI_N BF18 CLK_BUF_EXP_N
10KR2J-3-GP SG(PX) : 0 0

1
PCIE_CLK_RQ2# V10 BE18 CLK_BUF_EXP_P 10KR2J-3-GP
PCIECLKRQ2#/GPIO20 CLKIN_DMI_P R2013
R2012 Optimus : 1 0
RN2022 UMA
LAN CLK 4 CLK_PCH_SRC3_N
31 CLK_PCIE_LAN# 1 Y37 BJ30 CLK_BUF_CPYCLK_N RN2008 1 4 SRN10KJ-5-GP
CLKOUT_PCIE3N CLKIN_GND1_N
31 CLK_PCIE_LAN 2 3 CLK_PCH_SRC3_P Y36 BG30 CLK_BUF_CPYCLK_P 2 3

2
SRN0J-6-GP CLKOUT_PCIE3P CLKIN_GND1_P UMA_DIS# UMA_DIS# 22
31 PCIE_CLK_LAN_REQ# A8 DGPU_PRSNT#
B PCIECLKRQ3#/GPIO25 CLK_BUF_DOT96_N B
CLKIN_DOT_96N G24

1
E24 CLK_BUF_DOT96_P
CLKIN_DOT_96P
Y43 CLKOUT_PCIE4N
Y45 CLKOUT_PCIE4P CLK_BUF_CKSSCD_N
R2010 DY DY
CLKIN_SATA_N AK7 Do Not Stuff R2011
CLK_PCIE_USB3_REQ# L12 AK5 CLK_BUF_CKSSCD_P
Do Not Stuff

2
PCIECLKRQ4#/GPIO26 CLKIN_SATA_P
SIV
V45 K45 CLK_BUF_REF14
CLKOUT_PCIE5N REFCLK14IN
V46 CLKOUT_PCIE5P 3D3V_S5 RN2001
PCIE_CLK_REQ5# L14 H45 CLK_PCI_FB CLK_PCI_FB 18 1 8CLK_PCIE_W W AN_REQ#
PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK
2 7
PL 10K FOR Integrated CLOCK GEN mode. 3 6 PCIE_CLK_LAN_REQ#
AB42 V47 XTAL25_IN 1 TP2016 Do Not Stuff 4 5 CLK_PCIE_USB3_REQ#
CLKOUT_PEG_B_N XTAL25_IN RN2009
AB40 V49 XTAL25_OUT 1 TP2017 Do Not Stuff
CLKOUT_PEG_B_P XTAL25_OUT CLK_BUF_REF14 1 10 SRN10KJ-6-GP
CLK_BUF_CKSSCD_N 2 9 CLK_BUF_EXP_N
PEG_B_CLKRQ# E6 RN2002
3D3V_S0 PEG_B_CLKRQ#/GPIO56 CLK_BUF_CKSSCD_P 3 8 CLK_BUF_EXP_P
R2007 CLK_BUF_DOT96_N 1 8 EC_SW I#
XCLK_RCOMP 1 4 7
XCLK_RCOMP Y47 2 +VCCDIFFCLKN CLK_BUF_DOT96_P 2 7 PCIE_CLK_REQ5#
RN2018 5 6
V40 CLKOUT_PCIE6N 90D9R2F-1-GP 3 6 PCIE_CLK_NEW _REQ#
1 4 CLK_PCIE_W LAN_REQ# V42 4 5 PEG_B_CLKRQ#
CLKOUT_PCIE6P SRN10KJ-L3-GP
2 3 PCIE_CLK_RQ2#
PCIE_CLK_REQ6# T13 need very close to PCH SRN10KJ-6-GP
PCIECLKRQ6#/GPIO45
SRN10KJ-5-GP
V38 K43 JTAG_TCK 1 TP2013 Do Not Stuff
FLEX CLOCKS

CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64
PCIECLKRQ1# and PCIECLKRQ2# V37 CLKOUT_PCIE7P
F47 CLK_PCH_48M_L 1 Do Not Stuff
support S0 power only PCIE_CLK_NEW _REQ# K12 CLKOUTFLEX1/GPIO65 TP2012
A PCIECLKRQ7#/GPIO46 BOM A
CLKOUTFLEX2/GPIO66 H47 LAN_25M 1 TP2014 Do Not Stuff
Do Not Stuff TP2010 1 PCIE_CLK_XDP_N AK14
PCIE_CLK_XDP_P CLKOUT_ITPXDP_N
K49 DGPU_PRSNT#
Do Not Stuff TP2011 1 AK13 CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 110706 modified Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
PANTHER-GP-NF Taipei Hsien 221, Taiwan, R.O.C.

www.vinafix.vn
– Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 Title
– Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2
PCH ( PCI-E/SMBUS/CLOCK/CL)
if more than 2 PCI clocks + PCI loopback are routed. Size Document Number Rev
鎖料: 71.PANTH.00U
PCH鎖 LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 20 of 103
5 4 3 2 1
5 4 3 2 1

NOTE
SSID = PCH RTC_AUX_S5 Do Not Stuff TP2111 1
R2111,R2118~R2120,R2125

2
RN2104
3
0 ohm
1 4 INTVRMEN- Integrated SUS HR 63.R0034.1DL
RTC_X1 1.05V VRM Enable
22 ohm

1
C2103
1 2 RTC_X2
SRN20KJ-1-GP
SC1U6D3V2KX-GP High - Enable internal VRs CRV
R2101 10MR2J-L-GP SIT Low - Enable external VRs 64.22R05.6DL

2
D
D Q2130 1 22 ohm 5% D
X2101 Do Not Stuff TP2114 PCH1A 1 OF 10 LPC_AD[0..3]
LPC_AD[0..3] 27,65

SC1U6D3V2KX-GP
2N7002K-2-GP
Do Not Stuff TP2115 1 RTC_X1 LPC_AD0_TPM R2111 1 22R2J-2-GP LPC_AD0
1 4 A20 C38 2
SIT 84.2N702.J31 RTCX1 FWH0/LAD0
A38 LPC_AD1_TPM R2118 1 2 22R2J-2-GP LPC_AD1
2nd = 84.2N702.W31 FWH1/LAD1

LPC
C2101 RTC_X2 C20 B37 LPC_AD2_TPM R2119 1 2 22R2J-2-GP LPC_AD2
1 RTCX2 FWH2/LAD2
1

Do Not Stuff TP2112 C37 LPC_AD3_TPM R2120 1 2 22R2J-2-GP LPC_AD3


C2102 FWH3/LAD3
SC6P50V2CN-1GP

2 3 RTC_RST# D20
1

S
RTCRST# LPC_FRAME#_L R2125
D36 1 2

SC6P50V2CN-1GP
LPC_FRAME# 27,65
2

FWH4/LFRAME#

2
D2130 G2101 1M1R2J-GP SRTC_RST#

KBC_RTCRST#_Q
G22 SRTCRST# 22R2J-2-GP

1
C2104 Do Not Stuff R2104
2

Do Not Stuff LDRQ0# E36


SM_INTRUDER# GPIO23

RTC
2 1 K22 K36
SIT 2 INTRUDER# LDRQ1#/GPIO23
X-32D768KHZ-34GPU R2105

2
RTC_AUX_S5 1 2 PCH_INTVRMEN C17 V5 INT_SERIRQ 27 (LG4858L)HM70

1
3 INTVRMEN SERIRQ
DY 330KR2F-L-GP
Do Not Stuff TP2113 1
1
SATA0RXN AM3 SATA_RXN1_C 56
27 RTCRST_ON HDA_BITCLK N34 AM1 SATA_RXP1_C 56
1 2 KBC_RTCRST# 27 HDA_BCLK SATA0RXP
AP7 SATA_TXN1_C C2105 1 2 SCD01U16V2KX-3GP HDD1

SATA 6G
0R2J-2-GP SATA0TXN SATA_TXN1 56
R2130 HDA_SYNC L34 AP5 SATA_TXP1_C C2106 1 2
2
HDA_SYNC SATA0TXP SATA_TXP1 56
SCD01U16V2KX-3GP
R2131
29 HDA_SPKR T10 AM10
DY Do Not Stuff SPKR SATA1RXN
AM8
HDA_RST# SATA1RXP
K34 HDA_RST# SATA1TXN AP11
1

SATA1TXP AP10

29 HDA_SDIN0 E34 HDA_SDIN0 SATA2RXN AD7


R2123 2 1 33R2J-2-GP HDA_SDOUT AD5
29 HDA_CODEC_SDOUT SATA2RXP
RN2102 G34 HDA_SDIN1 SATA2TXN AH5
C HDA_RST# SATA2TXP AH4 C
1 4 ER2233
29 HDA_CODEC_RST#
2 3 HDA_BITCLK_C 1 2 HDA_BITCLK C34 HDA_SDIN2 Move Cap close to Device or Connector.

IHDA
29 HDA_CODEC_BITCLK For EMC AB8
Do Not Stuff SATA3RXN SATA_RXN4_C 56
SRN33J-5-GP-U A34 HDA_SDIN3 SATA3RXP AB10
SATA3TXN AF3
AF1 SATA_RXP4_C 56
HDA_SDOUT SATA3TXP SATA_TXN4_C 56
Flash Descriptor Security Overide A36 HDA_SDO
1 R2107 2 1KR2J-1-GP SATA_TXP4_C 56

SATA
27 ME_UNLOCK Y7
Low = Default
SATA4RXN G48
+3VS_+1.5VS_HDA_IO
HDA_SDOUT High = Enable Do Not Stuff TP2105 1 PCH_GPIO33 C36 HDA_DOCK_EN#/GPIO33
SATA4RXP
SATA4TXN
Y5
AD3 SATA_TXN4_C C2109 1
SATA_TXP4_C C2110 1
2 Do Not Stuff SATA_TXN4 56 ODD
SATA4TXP AD1 2 Do Not Stuff SATA_TXP4 56
N32
Do Not Stuff TP2106 1 HDA_DOCK_RST#/GPIO13
Y3 SATA_RXN5 1
G48
TP2107 Do Not Stuff
1
R2102
2
Do Not Stuff
HDA_SDOUT 4K7R2J-2-GP
R2121
SATA5RXN
SATA5RXP Y1
AB3
SATA_RXP5
SATA_TXN5
1
1
TP2108
TP2109
Do Not Stuff
Do Not Stuff
Delete
SATA5TXN
DY 2 1 PCH_JTAG_TCK_BUF J3 JTAG_TCK SATA5TXP AB1 SATA_TXP5 1 TP2110 Do Not Stuff
ESATA
1 PCH_JTAG_TMS H7 Y11 1D05V_VTT
3D3V_S0 NO REBOOT STRAP Do Not Stuff TP2102 JTAG_TMS SATAICOMPO

JTAG
No Reboot Strap 1 PCH_JTAG_TDI K5 Y10 SATA_COMP R2112 1 2
Do Not Stuff TP2103 JTAG_TDI SATAICOMPI
R2106 37D4R2F-GP
Low = Default 1 PCH_JTAG_TDO H1 1D05V_VTT
1 2 HDA_SPKR Do Not Stuff TP2104 JTAG_TDO
Do Not Stuff HDA_SPKR High = No Reboot SATA3RCOMPO AB12
DY SATA3_COMP R2113
SATA3COMPI AB13 1 2 49D9R2F-GP

33R2J-2-GP
+3VS_+1.5VS_HDA_IO 27,60,65 SPI_CLK_R 1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP
R2108 SPI_CLK SATA3RBIAS
For Ge
B 27,60,65 SPI_CS0#_R 1 2 PCH_SPI_CS0# Y14 B
1 R2103 2 1KR2J-1-GP HDA_SYNC SPI_CS0#
33R2J-2-GP R2109 LA37/LA57/CRV-Std:750ohm
T1
This signal has a weak internal pull down. SIT SPI_CS1# LA47: 806 ohm

SPI
P3 SATA_LED# 1 TP2130 Do Not Stuff
On Die PLL VR is supplied by 1.5V when SATALED#
R2232
sampled high, 1.8 V when sampled low. 27,60,65 SPI_SI_R 1 2 PCH_SPI_SI V4 SPI_MOSI SATA0GP/GPIO21 V14 GPIO21_SATA_DET#0 1 2 SATA_DET#0
Needs to be pulled High for Huron River platform. R2110
33R2J-2-GP Do Not Stuff
U3 P1 GPIO19_BBS_BIT0
co-operate with R2310 27,60,65 SPI_SO_R SPI_MISO SATA1GP/GPIO19
R2231
1 2 BBS_BIT0 18 3D3V_S0
PANTHER-GP-NF
PLL ODVR VOLTAGE 鎖料: 71.PANTH.00U
PCH鎖 Do Not Stuff

Low = 1.8V (Default) SATA_DET#0 1 2 R2129


HDA_SYNC High = 1.5V HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to 10KR2J-3-GP
sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this
signal on the board. Signal may have leakage paths via powered off devices (Audio 20110727 for vendor RN2101 SRN10KJ-5-GP
DY Codec) and hence contend with the external pull-up. A blocking FET is INT_SERIRQ 1 4
Do Not Stuff 1 2 R2122 2 3
recommended in such a case to isolate HDA_SYNC from the Audio Codec device 22 PSW _CLR#

until after the Strap sampling is complete. SIV


84.2N702.J31
2ND = 84.2N702.W31 R2128
Q2101 GPIO23 1 2
10KR2J-3-GP
S HDA_CODEC_SYNC_L 1 2 HDA_CODEC_SYNC 29 HDA_CODEC_BITCLK HDA_CODEC_SDOUT SPI_CS0#_R
A HDA_SYNC D
R2124 BOM 110706 modified A
33R2J-2-GP
2

2
1

G EC2102 EC2103 EC2101


R2127
1MR2F-GP DY DY DY
Wistron Corporation
1

1
Do Not Stuff

Do Not Stuff

Do Not Stuff
2N7002K-2-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2

www.vinafix.vn
5V_S0 Title
PCH (SPI/RTC/LPC/SATA/IHDA)
Size Document Number Rev
LG4858_UMA -1
Date: Friday, March 16, 2012 Sheet 21 of 103
5 4 3 2 1
5 4 3 2 1

3D3V_S0 SIV
SSID = PCH
INTERNAL GFX EXTERNAL GFX
Note:
R2202 1 2 200KR2F-L-GP SATA_ODD_PRSNT# For PCH debug with XDP, need to NO STUFF R2218 R2205 DY 10K
PCH1F 6 OF 10
110706 modified
S_GPIO 1 R2218 2 GPIO0 T7 C40
R2206 100K DY
BMBUSY#/GPIO0 TACH4/GPIO68 SATA_ODD_PW RGT 56
3D3V_S0 PCH_GPIO15 100R2J-2-GP
SVT EC_SMI# A42 B41 UMA_DIS#
TACH1/GPIO1 TACH5/GPIO69 UMA_DIS# 20

2
RN2203 DY 20110728 for Vendor 3D3V_S0
1 4 H_A20GATE R2233 DGPU_HPD_INTR# H36 C41 VRAM_SIZE1
H_RCIN# TACH2/GPIO6 TACH6/GPIO70
D 2 3 100KR2J-1-GP D

1
27 EC_SCI# EC_SCI# E38 A40 VRAM_SIZE2
Do Not Stuff TACH3/GPIO7 TACH7/GPIO71 R2205

1
GPIO27 has a weak[20K] internal pull up. ICC_EN# Do Not Stuff
C10 GPIO8 DY
To enable on-die PLL Voltage regurator, SIT
60 RTC_DET# RTC_DET# C4
should not place external pull down.

2
LAN_PHY_PWR_CTRL/GPIO12
Check GFX_CRB_DET
LOW: ODD exist PCH_GPIO15 G2 GPIO15 A20GATE P4 H_A20GATE 27

1
Note HIGH: ODD non-exist AU16 H_PECI_R 1 R2203 2 DY R2206
PECI 0R2J-2-GP H_PECI 5,27 100KR2J-1-GP
56 SATA_ODD_PRSNT# 1 R2213 2 PCH_GPIO16 U2 SATA4GP/GPIO16
P5 H_RCIN# 27
R2202 ---- Do Not Stuff RCIN#

2
GPIO
Do Not Stuff TP2238 1 DGPU_PW ROK D40 AY11 H_CPUPW RGD 5,36,97
200K ohm TACH0/GPIO17 PROCPWRGD

CPU/MISC
HR 64.20035.6DL PCH_GPIO15 pull high => 11252 or 11291 PCH_GPIO22 T5 SCLOCK/GPIO22 THRMTRIP# AY10 PCH_THERMTRIP_R R2204 1 2 390R2J-1-GP H_THERMTRIP# 5,36
PCH_GPIO15 pull Low => 11326 or 12206 PCH_GPIO24 E8 T14 INIT3_3V# 1 TP2201 Do Not Stuff
10K ohm GPIO24 INIT3_3V#
CRB 63.10334.1DL 3D3V_S5 1
R2225
2 PCH_GPIO27 E16 GPIO27 DF_TVS AY1 NV_CLE 1D8V_S0
10KR2J-3-GP