Logical Operator 8051 Instruction

Chapter 3 ECP2036 Part III
Logical Instruction (pg. 75 – 77)

• One application area of 8051 is in machine control
which involves performing Boolean operations on
bytes or bits of data
• The 8051 has instruction set that performs logical
operations as shown below:
Logical Operator 8051 Instruction

AND ANL (AND Logical)
OR ORL (OR Logical)
XOR XRL (XOR Logical)
NOT CPL (Complement)
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continue ...
• The addressing modes for these logical instructions
are: immediate, register, direct and indirect
• For instance, the AND Logical instruction can take
several forms:
ANL A, 55H (direct)
ANL A, @R0 (indirect)
ANL A, R6 (register)
ANL A, #33H (immediate)
• Logical operation can be performed between any byte
in the internal RAM and an immediate data without
having to go through the accumulator
• Nevertheless, the logical instructions using
accumulator as one of the operands execute in only one
machine cycle

continue ...
• Consider the following example
Assembly instruction Comment
MOV A, #0FFH ; A = FFH
MOV R0, #77H ; R0 = 77H
ANL A, R0 ; A = 77H
MOV 15H, A ; internal RAM location 15H = 77H
CPL A ; A = 88H
XRL 15H, #0FFH ; internal RAM location 15H = 88H
ORL R0, 15H ; R0 = FFH
CLR A ; A = 00H
R0 0 1 1 1 0 1 1 1 (77H) A 0 1 1 1 0 1 1 1 (77H) 1 1 1 1 1 1 1 1 (FFH)
AND CPL XOR
A 1 1 1 1 1 1 1 1 (FFH) A 1 0 0 0 1 0 0 0 (88H) 15H 0 1 1 1 0 1 1 1 (77H)
A 0 1 1 1 0 1 1 1 (77H) 15H 1 0 0 0 1 0 0 0 (88H)
15H 1 0 0 0 1 0 0 0 (88H) A 1 0 0 0 1 0 0 0 (88H)

OR CLR
R0 0 1 1 1 0 1 1 1 (77H) A 0 0 0 0 0 0 0 0 (00H)
R0 1 1 1 1 1 1 1 1 (FFH)
Logical Rotate Instructions

• 8051 is also equipped with logical rotate instructions
that operate only on a byte, or a byte and the carry flag,
to perform limited 8 and 9-bit shift register operations:
Mnemonic Operation
RL Rotate a byte to the left; MSB becomes LSB
RLC Rotate a byte and the carry bit to the left; the carry bit becomes LSB and MSB
becomes the carry
RR Rotate a byte to the right; LSB becomes MSB
RRC Rotate a byte and the carry to the right; LSB becomes the carry and the carry bit
becomes the MSB
SWAP Exchange the low and high nibbles in a byte
7 6 5 4 3 2 1 0
RL A
C 7 6 5 4 3 2 1 0
carry flag RLC A

continue ...
7 6 5 4 3 2 1 0
RR A
C 7 6 5 4 3 2 1 0
carry flag RRC A
7 6 5 4 3 2 1 0
High Nibble Low Nibble
SWAP A

continue ...
• Example
MOV A, #0A5H ; A = 1010 01012 = A5H
RR A ; A = 1101 00102 = D2H
SWAP A ; A = 0010 11012 = 2DH
CLR C ;C=0
RRC A ; C = 1, A = 0001 01102 = 16H
RL A ; A = 0010 11002 = 2CH
SWAP A ; A = 1100 00102 = C2H
RLC A ; C = 1, A = 1000 01012 = 85H
C A
A 1 1 0 1 0 0 1 0 (D2H)
A 1 0 1 0 0 1 0 1 (A5H) 0 0 0 1 0 1 1 0 1 (2DH)
RR RRC
A SWAP
1 1 0 1 0 0 1 0 (D2H) 1 0 0 0 1 0 1 1 0 (16H)
C A
A 0 0 1 0 1 1 0 1 (2DH)
C A
A 0 0 1 0 1 1 0 0 (2CH)
A 0 0 0 1 0 1 1 0 (16H) 1 1 1 0 0 0 0 1 0 (C2H)
RL RLC
SWAP
A 0 0 1 0 1 1 0 0 (2CH) 1 1 0 0 0 0 1 0 1 (85H)
A 1 1 0 0 0 0 1 0 (C2H)
Example
An 8-bit signed data is stored in internal RAM at address
30H. Set the carry flag to 1 if the data is a positive number;
otherwise clear the carry flag to 0 if it is negative.
Solution:
MOV A, 30H
RLC A
CPL C
ACC 30H 0 1 0 1 1 0 1 0
0 0 1 0 1 1 0 1 0
carry flag RLC A
1 positive number
carry flag

Boolean Variable Instructions (pg. 81 – 82)
• 8051 has a complete Boolean processor for single-bit

operations
• The internal RAM (20H to 2FH) contains 128
addressable bits, and the SFR space support up to
another 128 addressable bits
• The bit-level instructions include: move, set, clear,
complement, OR, AND and conditional branching
• All bit-level instruction use direct addressing with bit
addresses 00H - 7FH in the lower 128 locations, and
bit addresses 80H - FFH in the SFR space
• The carry flag (C) in the PSW stores the result for most
of the bit-level instructions, since it can be tested for
program flow control (conditional branching)

continue ...
• The table below lists the Boolean bit-level operations:
Assembly instruction Operation
ANL C, b AND C and the addressed bit; put result in C
ANL C, /b AND C and the complement of addressed bit; put result in C
ORL C, b OR C and the addressed bit; put result in C
ORL C, /b OR C and the complement of addressed bit; put result in C
CPL C Complement C
CPL bit Complement the addressed bit
CLR C Clear C to 0
CLR bit Clear the addressed bit to 0
MOV C, bit Copy the addressed bit to C
MOV bit, C Copy C to the addressed bit
SETB C Set C to 1
SETB bit Set the addressed bit to 1

continue ...
• Example
SETB 00H ; Bit 0 of RAM byte 20H = 1
MOV C, 00H ;C=1
MOV 7FH, C ; Bit 7 of RAM byte 2FH = 1
ANL C, /00H ; C = 0 since bit 0 of RAM byte 20H = 1
ORL C, 00H ;C=1
CPL 7FH ; Bit 7 of RAM byte 2FH = 0
CLR C ;C=0
ORL C, /7FH ; C = 1 since bit 7 of RAM byte 2FH = 0

continue ...
• By using the bit level instruction, the 8051 can also be
programmed to perform the operation of a logic circuit
• Example
P Q R
Symbol Bit address

P 00H
Q 01H
S R 02H
S 03H
MOV C, 02H
ANL C, /01H
ORL C, 00H
MOV 03H, C

Program Branching Instructions (pg. 82– 86)
• In a program, it is often necessary to branch or jump to

certain part of the program
• The 8051 supports the following program branching
instructions:
i. Jump on bit conditions
ii. Compare bytes and jump if not equal
iii. Decrement byte and jump if not zero
iv. Jump unconditionally
v. Call a subroutine
vi. Return from a subroutine
• Four addressing modes are used for different range of
branching: relative, absolute, long and indexed

Jump or Call Program Range

• A branching instruction can replace the contents of the
program counter with a new address
• The distance (in bytes) between the destination address
and the original address (before branching) is known
as the range of jump or call
Code memory
jump instruction
PC Next instruction
...
Jump
range
destination
...

continue ...
• Depending on the addressing mode, jump or call
instructions may have one of three ranges:
i. Relative range of -12810 to +12710 bytes from
instruction following the jump or call
ii. An absolute range on the same 2K page as the
instruction following the jump or call
iii. A long range of any address from 0000H to FFFFH
• As such there are 3 variations of jump instructions:
SJMP, AJMP and LJMP
• However, there are only 2 variations of call instruction:
ACALL and LCALL

continue ... LJMP

0000H LADD Limit
previous page AJMP

current page AADD Limit
SJMP
PC – 12810 Relative Limit
JC
JNC
Bit
JB
Jumps
JNB
Jump opcode
JBC
PC Next opcode
CJNE
DJNZ Byte
JZ Jumps
JNZ
PC + 12710 Relative Limit
current page AADD Limit

next page
FFFFH LADD Limit

continue ...
• The ASM51 assembler allows the use of generic JMP
mnemonic if the programmer does not care which
jump instruction to be used
• The assembler converts the generic mnemonic to a real
instruction based on the following rules:
i. SJMP if no forward references are used and the
jump destination is within –128 locations
ii. AJMP if no forward references are used and the
jump destination is in the same 2k page as the
instruction immediately following the JMP
iii. LJMP if short or absolute forms cannot be used
• There is also a generic CALL instruction which works
the same way for ACALL and LCALL

Jumps
• There are 2 types of jump instructions: conditional
jump and unconditional jump
• 8051 has a set of conditional jump instructions that can
operate at the bit or byte levels
• Conditional jumps operate by testing for conditions
that are specified in the instruction
• If the condition is true, then the jump is taken and the
program counter is altered to the destination address
• If the condition is false, then the instruction
immediately following the jump instruction is executed
since the program counter is not altered

Bit Jumps
• Bit jumps operate according to the status of the carry
flag in the PSW or the status of any bit-addressable
location
• Jump instructions that test for bit condition are:
Mnemonic Operation
JC Jump relative if the carry flag is set to 1
JNC Jump relative if the carry flag is reset/cleared to 0
JB Jump relative if addressable bit is set to 1
JNB Jump relative if addressable bit is reset/cleared to 0
JBC Jump relative if the addressable bit is set, and clear the addressable
bit to 0

continue ...
• Example
Write a program to set the upper 4 pins of Port 2 to ‘1’
if pin 0 of port 1 is high; otherwise set the lower 4 pins
of port 2 to ‘1’
Label Assembly instruction Comment
ORG 0000H
MOV P1, #0FFH ; make P1 an input port
REPEAT: JB P1.0, ON ; jump to ON if pin 0 of P1 is high
OFF: MOV P2, #0FH ; if low, set the lower 4 pins of P2 to '1'
SJMP REPEAT ; jump back to check the status of P1.0
ON: MOV P2, #0F0H ; set the upper 4 pins of P2 to '1'
SJMP REPEAT ; jump back to check the status of P1.0
END

Byte Jumps
• Byte jumps test a byte of data and operate according to
the tested condition; jump if the condition is true or
proceed to the next instruction if the condition is false
• The following table gives a list of byte jumps:
Mnemonic Operation
CJNE Compare the magnitudes of the first two operands, and branches to the
relative address stated by the 3rd operand if their values are not equal
DJNZ Decrement the location indicated by the first operand, and branches to
the relative address indicated by the 2nd operand if the resulting value is
not zero
JZ Jump to the relative address if A is 0; the flags and A are not changed
JNZ Jump to the relative address if A is not 0; the flags and A are not changes

continue ...
• Example
Write an instruction sequence to clear the contents of
internal RAM location starting from address 30H to
7FH
MOV R0, #30H ; initialize R0 to point to address 30H
LOOP: MOV @R0, #00H ; clear the contents of location pointed by R0
INC R0 ; increment R0
CJNE R0, #80H, LOOP ; jump back to clear memory locations as long
; as R0 is less than 80H

continue ...
• Example
32 bytes of data are stored using 8-bit 2s complement
notation in internal RAM locations starting from 30H.
Write an instruction sequence to calculate the negative
number in these data and store the result in R5.
MOV R0, #30H ; initialize R0 to point to address 30H
MOV R1, #32 ; number of data byte to processed
MOV R5, #0 ; clear R5
LOOP: MOV A, @R0 ; move the data pointed by R0 into A
RLC A ; move the MSB of the data into carry flag
JNC SKIP ; if C=0, not a negative number; don't count
INC R5 ; otherwise, increment the count by 1
SKIP: INC R0 ; increment R0 to point to the next address
DJNZ R1, LOOP ; decrement the number of byte
; repeat until 32 bytes of data has been processed

Unconditional Jumps
• Unconditional jumps do not test any bit or byte to
determine whether the jump should be taken; the jump
is always taken
• The following table shows a list of unconditional
jumps:
Mnemonic Operation
JMP @A+DPTR Jump to the address formed by adding A to the DPTR; the
address can be anywhere in a program memory space
AJMP Jump to absolute short range address (within the same 2K
page)
LJMP Jump to absolute long range address (0000H to FFFFH)
SJMP Jump to relative address (PC-12810 to PC+12710)

continue ...
• Example
MOV A, #10000000B ; set pin 7 of port 1 to high
LOOP: MOV P1, A ; move the contents of accumulator to A
RR A ; rotate the contents of A 1 bit to the right
CALL DELAY_1S ; delay for 1 second
SJMP LOOP ; always jump back to repeat the process
0
1 1
0 1
0 1
0 1
0 1
0 1
0 0
1

Jump Table
• Case dependent jump can be implemented using jump table
• In jump table, indexed addressing is used where the DPTR
is loaded with the address of a jump table, and the
accumulator acts as an index
• For e.g., if 3 cases are desired, accumulator is loaded with
a value from 0 to 2
0100 MOV DPTR, #JMP_TBL ; JMP_TBL = 0105H
0103 RL A ; multiply A by 2
0104 JMP @A+DPTR
0105 JMP_TBL: AJMP LABEL0 ; LABEL0 = 0200H
0107 AJMP LABEL1 ; LABEL1 = 0250H
0109 AJMP LABEL2 ; LABEL2 = 02A0H
• Each entry contains another absolute jump to actual
places to execute different tasks
Note: “RL A” is needed as the address for each entry is differ by 2 25
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Subroutines
• If the same instruction sequence is being used
repeatedly, it can be written as a subroutine
• This subroutine can then be called by the main
program as many times as needed
• A call to subroutine causes a jump to the address where
the subroutine is located
• After executing the subroutine, the program resumes
operation at the next instruction (in main program)
after the call
• The return address must be stored so that the main
program can resume after it returns from subroutine
• To do this, the stack area of internal RAM is used to
automatically store this return address

continue ...
Main program
Call subroutine
PC Next instruction
The return address,
...
which is the current
contents of PC, is
pushed on to stack Two pop operations
restore the return
Subroutine address to the PC
from the stack
RET
Program Counter
PCH PCL
ACALL / LCALL /
Interrupt
SP + 2 PCH SP – 1
SP + 1 PCL SP – 2
RET / RETI
SP Stack Area SP
PCH PCL
Program Counter
Internal RAM
continue ...
• The programmer must ensure that the subroutine ends
with a RET instruction and the stack does not grow up
into data area used by the program
• The following table shows a list of call instruction
Mnemonic Operation
ACALL Call the subroutine located on the same 2K page
LCALL Call the subroutine located anywhere in the program memory
space (0000H - FFFFH)
RET Pop two bytes from the stack into the program counter

No Operation (pg. 86 – 87)

• There is an instruction that perform nothing – NOP
• Although this instruction is not doing anything, it takes
one machine cycle to execute
• Thus, it is used to create a delay of one machine cycle
• For precise and short time delay, NOP can be used
• E.g. To create a short pulse of 3 machine cycles at Pin
0 of Port 1:
SETB P1.0
NOP P1.0 SETB NOP NOP CLR
NOP
1mc 1mc 1mc 1mc
CLR P1.0

Time Delay Generation

• In certain occasions, a delay of a fixed time is required
during the execution of a program
• This delay can be inserted in the program by calling to
a subroutine which generates the delay
• In 8051, one machine cycle lasts for 12 oscillator
periods
• For eg., if the crystal frequency is f = 12MHz, one
machine cycle will be 1/f × 12 = 1s
• Therefore, a delay of one second can be generated by
calling a subroutine which executes for 1 million
machine cycles (1 × 106 × 1s = 1s)

continue ...
• The subroutine below causes a delay of 1 second
(crystal frequency = 12 MHz)
Label Assembly instruction Machine cycles
1 DELAY: MOV R0, #4 1 machine cycle
2 REPEAT: MOV R1, #250 1 machine cycle
3 AGAIN: MOV R2, #250 1 machine cycle
4 HERE: NOP 1 machine cycle
5 NOP 1 machine cycle
6 DJNZ R2, HERE 2 machine cycle
7 DJNZ R1, AGAIN 2 machine cycle
8 DJNZ R0, REPEAT 2 machine cycle
9 RET 2 machine cycle
4s x 250 = 1ms
(4s x 250) x 250 = 0.25s
((4s x 250) x 250) x 4 = 1s

continue ...
• However, the actual execution time of this subroutine
is not one second
Label Assembly instruction Machine cycles
1 DELAY: MOV R0, #4 1 machine cycle
2 REPEAT: MOV R1, #250 1 machine cycle
3 AGAIN: MOV R2, #250 1 machine cycle
4 HERE: NOP 1 machine cycle
5 NOP 1 machine cycle
6 DJNZ R2, HERE 2 machine cycle
7 DJNZ R1, AGAIN 2 machine cycle
8 DJNZ R0, REPEAT 2 machine cycle
9 RET 2 machine cycle
Lines 3 and 7 (AGAIN loop) introduce an addition of

(1+2) x 1s x 250 x 4 = 3ms
Lines 2 and 8 (REPEAT loop) introduce a delay of
(1+2) x 1s x 4 = 12s
continue ...
Line 1 and line 9 will introduce another delay of
(1+2 ) x 1s = 3s
Therefore the actual delay generated by the subroutine is

1s + 3ms +12s + 3s = 1.003015s

Example
Using the previous example, generate a delay of 30s and 61.5s.
Main program: Subroutine:

Assembly instruction Comment Label Assembly instruction
... DELAY: MOV R0, A
MOV A, #____ ; 30s / 0.25s = ____ REPEAT: MOV R1, #250
AGAIN: MOV R2, #250
ACALL DELAY ; generate a delay of 30s
HERE: NOP
... NOP
MOV A, #____ ; 61.5s / 0.25s = ____ DJNZ R2, HERE
ACALL DELAY ; generate a delay of 61.5s DJNZ R1, AGAIN
... DJNZ R0, REPEAT
RET

Logical Operator 8051 Instruction

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Chapter 3 ECP2036 Part III

Logical Instruction (pg. 75 – 77)

Logical Operator 8051 Instruction

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AND CPL XOR

A 1 1 1 1 1 1 1 1 (FFH) A 1 0 0 0 1 0 0 0 (88H) 15H 0 1 1 1 0 1 1 1 (77H)

A 0 1 1 1 0 1 1 1 (77H) 15H 1 0 0 0 1 0 0 0 (88H)

15H 1 0 0 0 1 0 0 0 (88H) A 1 0 0 0 1 0 0 0 (88H)

Logical Rotate Instructions

carry flag RLC A

carry flag RRC A

High Nibble Low Nibble

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Boolean Variable Instructions (pg. 81 – 82)

• 8051 has a complete Boolean processor for single-bit

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Symbol Bit address

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Program Branching Instructions (pg. 82– 86)

• In a program, it is often necessary to branch or jump to

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Jump or Call Program Range

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continue ... LJMP

previous page AJMP

current page AADD Limit

FFFFH LADD Limit

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No Operation (pg. 86 – 87)

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Time Delay Generation

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((4s x 250) x 250) x 4 = 1s

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Lines 3 and 7 (AGAIN loop) introduce an addition of

Therefore the actual delay generated by the subroutine is

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Main program: Subroutine:

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