Resource person
Ms. Sadiya Arsad ( National manager )
BHARTI VIDYAPEETH’S
COLLEGE OF ENGINEERING, NEW DELHI
PRESENTS
One week FDP
on
FPGA and ASIC design
th st
February 25 2019 to 1 march 2019
Organized by
Dept. of ECE, BVCOE, New Delhi
Institute:
Bharati Vidyapeeth’s College of Engineering
(BVCOE), New Delhi, since its establishment in 1999,
has strived to provide the best engineering education
to its students through well-qualified and dedicated
faculty and provision of well-equipped modern labs.
The College is affiliated to Guru Gobind Singh
Indraprastha University, New Delhi, and approved by
All India Council for Technical Education (AICTE),
Ministry of HRD, Govt. of India. BVCOE is steadily
striding forward in its quest of establishing itself among
the top engineering colleges in North India. The vision
of the college is to continuously excel and thus coming
together enlivens the research themes, creates
awareness about upcoming technologies and provide
platform to budding research workers for achieving
their rightful place in the scientific community.
Partner Organisation:
CoreEL Technologies is a Customer Application
Specific Product & Solutions (CASPS) company
offering innovative solutions, which ranges across
Intellectual Property (IP) cores, Design & Mr Prakhar Priyadarshi, Assistant Prof. BVCOE, ND
Development, Bespoke System Design & Prototype
Development, Next-Gen Digital products, Integrated
solutions, Low Volume Manufacturing, System
Upgrades and Obsolescence management, EDA tools,
COTS products, Semiconductor solutions and
Technology Training. CoreEL is a leading developer of
advanced electronic system level products and
solutions to three primary markets– Aerospace &
Defense, Digital Media Broadcast and Universities &
Institutions of higher learning.
Topics to be covered
FPGA design flow using Vivado:7-Series Architecture
Overview, Vivado Design Flow-Use Vivado IDE to create a
simple HDL design, Combinational design, Sequential
design. Simulate the design using the XSIM HDL simulator
available in Vivado design suite. Generate the bitstream and
verify in hardware. Synthesis Technique.
ASIC: Basic of ASIC design , full custom design flow, spice
net list, spice models & analysis , layer map file, DRC &
LVS rule layout design. Designing of digital blocks using
Pyxsis Tool, schematic design , spice simulation using Eldo
tool , layout design Layout design using SDL, caliber DRC,
Caliber LVS, Caliber PEX, post layout simulation. EDA
Solutions for IC/ASIC Design & Verification – Semi - Custom
Design Flow demonstration ( RTL to GDSII Flow )-RTL
Code writing, simulation, synthesis, Floor Planning,
Placement, routing, DRC, LVS with XRC.
For further information please contact:
For Technical aspects:
Dr. Manoj Sharma, Associate Prof. BVCOE, ND
For Registration & Logistics aspects:
S B Kumar, Assistant Prof. BVCOE, ND
Mr. Ankur Sangal ( Sr. Application Engineer )
University Program, CoreEL Technologies,
Ph: 8826892619/9891884347.
Registration Fees
Registration fees is Rs.500/- per participant. This
includes Tea and certificate cost. Lunch facility is on
payment basis in our canteen. The Demand Draft
should be drawn in favor of “Principal BVCOE”
th
payable at Delhi before 25 February 2019.
Registration
Participants (Faculty, Research Scholars, Students) need
to register by filling On-Line registration form
(https://goo.gl/forms/QdG110GyIWgRdSHv2) and send
the copy of form with payment proof to
manoj.sharma@bharatividyapeeth.edu .
Last Date of Registration: 24th February 2019
A certificate of participation would be provided to
the participants on conclusion of the programme.
REGISTRATION FORM
Name : ………………………………………………………………..
Academic Qualification: ……………………………………..
Designation : ………….……………………..…………………….
Department : ………….…………….…………………………….
Organization : ………….………………………………………….
Address (O) : ……………..…….………………………………….
Phone/Fax : ……………..……..……………………………….
E-mail : ………………………….……………………………….
Payment Details (DD No./Date/Amount):
REGISTRATION Online Link: -
https://goo.gl/forms/QdG110GyIWgRdSHv2
Signature of the Candidate