ARM Processor (Cortex M3)

Subject code: Exam Hours: 03 Hrs

No. of Hrs/Week: 04 IA marks: 50
Total Teaching Hours: 36 Exam marks: 100

UNIT-I

ARM Cortex M3: ARM Cortex M3 Processor and ARM Family, Cortex-M3 Processor Applications,
Architecture of ARM Cortex M3, Operation Modes, The built-in nested Vectored Interrupt Controller,
Memory Map, The Bus Interface, The MPU, Low Power and High Energy Efficiency, Debugging Support

Text: 1.1, 1.2, 1.5, 2.1, 2.3, 2.4, 2.5, 2.6, 2.7, 2.9.1, 2.10

ARM Cortex M3 Architecture: Registers, Special Registers, Vector Tables, Stack Memory Operation,
Reset Sequence

Text: 3.1, 3.2, 3.5, 3.6, 3.7 7 Hrs

UNIT-II

ARM Cortex M3 Instruction Set: Assembly Basics, Instruction List, Instruction Descriptions, Several
Useful Instructions in the Cortex M3

Text: 4.1, 4.2, 4.3, 4.4, 4.5, 4.6

ARM Cortex M3 Memory Systems: Memory System Features Overview, Memory Map, Memory Access
Attributes, Memory Access Permissions, Bit-Band Operations, Unaligned Transfers, Exclusive Access,
Endian Mode

Text: 5.1, 5.2, 5.3, 5.4, 5.5, 5.6 7 Hrs

UNIT-III

ARM Cortex M3 Exceptions: Exception Types, Definition of Priorities, Vector Tables, Interrupt Inputs and
Pending Behavior, Fault Exceptions, Supervisor Call and Pendable Service Call

Text: 7.1, 7.2, 7.3, 7.4, 7.5, 7.6

ARM Cortex M3 NVIC: Nested Vectored Interrupt Controller Overview, The Basic Interrupt
Configuration, Example Procedures in Setting Up an Interrupt, Software Interrupts, The SYSTICK Timer

Text: 8.1, 8.2, 8.3, 8.4, 8.5, 8.6 7 Hrs

UNIT-IV

ARM Cortex M3 Programming: Overview, A Typical Development Flow, Using C, CMSIS, Using Assembly,
Using Exclusive Access for Semaphores, Using Bit Band for Semaphores, Working with Bit Field Extract
and Table Branch

Text: 10.1, 10.2, 10.3, 10.4, 10.5, 10.6

ARM Cortex M3 Advanced Programming: Running a System with Two Separate Stacks, Double-Word
Stack Alignment, Nonbase Thread Enable, Performance Considerations, Lockup Situations, FAULTMASK

Text: 12.1, 12.2, 12.3, 12.4, 12.5, 12.6 7 Hrs

UNIT-V

ARM Cortex M3 MPU and Other Features: MPU Registers, Setting Up the MPU, The SYSTICK Timer,
Power Management, Multiprocessor Communication, Self-Reset Control

Text: 13.2, 13.3, 14.1, 14.2, 14.3, 14.4

ARM Cortex M3 Debug Architecture: Debugging Features Overview, CoreSight Overview, Debug Modes,
Debugging Events, Breakpoint in the Cortex-M3, Accessing Register Content in Debug, Other Core
Debugging Features

Text: 15.1, 15.2, 15.3, 15.4, 15.5, 15.6, 15.7 8 Hrs

Text Books:

1. Joseph Yiu, “The Definitive Guide to the ARM Cortex-M3, Newnes, (Elsevier), 2008