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00502-003
VOUT =
10V
Algebraic computation (WITH Z TIED TO OUTPUT)
Power measurements Figure 1.
Instrumentation applications
Available in chip form GUARANTEED PERFORMANCE OVER
TEMPERATURE
GENERAL DESCRIPTION The AD532J and AD532K are specified for maximum multiplying
The AD532 is the first pretrimmed, single chip, monolithic errors of ±2% and ±1% of full scale, respectively at 25°C, and
multiplier/divider. It guarantees a maximum multiplying error are rated for operation from 0°C to 70°C. The AD532S has a
of ±1.0% and a ±10 V output voltage without the need for any maximum multiplying error of ±1% of full scale at 25°C; it is
external trimming resistors or output op amp. Because the AD532 also 100% tested to guarantee a maximum error of ±4% at the
is internally trimmed, its simplicity of use provides design extended operating temperature limits of −55°C and +125°C.
engineers with an attractive alternative to modular multipliers, All devices are available in either a hermetically sealed TO-100
and its monolithic construction provides significant advantages metal can or 14-lead D-14 side brazed ceramic DIP. The J, K,
in size, reliability, and economy. Further, the AD532 can be a and S grade chips are also available.
direct replacement for other IC multipliers that require external
trim networks.
ADVANTAGES OF ON THE CHIP TRIMMING OF
THE MONOLITHIC AD532
FLEXIBILITY OF OPERATION
1. True ratiometric trim for improved power supply rejection.
The AD532 multiplies in four quadrants with a transfer function of 2. Reduced power requirements since no networks across
(X1 − X2)(Y1 − Y2)/10 V, divides in two quadrants with a 10 V Z/ supplies are required.
(X1 − X2) transfer function, and square roots in one quadrant 3. More reliable because standard monolithic assembly
with a transfer function of 10 V Z . In addition to these basic techniques can be used rather than more complex hybrid
functions, the differential X and Y inputs provide significant approaches.
operating flexibility both for algebraic computation and transducer 4. High impedance X and Y inputs with negligible circuit
instrumentation applications. Transfer functions, such as XY/10 V, loading.
(X2 − Y2)/10 V, ±X2/10 V, and 10 V Z/(X1 − X2), are easily attained 5. Differential X and Y inputs for noise rejection and additional
and are extremely useful in many modulation and function computational flexibility.
generation applications, as well as in trigonometric calculations
for airborne navigation and guidance applications, where the
monolithic construction and small size of the AD532 offer
considerable system advantages. In addition, the high common-
mode rejection ratio (CMRR) (75 dB) of the differential inputs
makes the AD532 especially well qualified for instrumentation
applications, as it can provide an output signal that is the product of
two transducer generated input signals.
TABLE OF CONTENTS
Features .............................................................................................. 1 Functional Description .....................................................................9
Applications ....................................................................................... 1 AD532 Performance Characteristics ........................................... 10
General Description ......................................................................... 1 Nonlinearity ................................................................................ 10
Flexibility of Operation .................................................................... 1 AC Feedthrough ......................................................................... 10
Functional Block Diagram .............................................................. 1 Common-Mode Rejection ........................................................ 10
Guaranteed Performance Over Temperature ............................... 1 Dynamic Characteristics ........................................................... 10
Advantages of On The Chip Trimming of The Monolithic Power Supply Considerations ................................................... 10
AD532 ................................................................................................ 1 Noise Characteristics ................................................................. 10
Revision History ............................................................................... 2 Applications..................................................................................... 11
Specifications..................................................................................... 3 Replacing Other IC Multipliers ................................................ 11
Thermal Resistance .......................................................................... 5 Square Root ................................................................................. 12
Chip Dimensions And Bonding Diagram ................................ 5 Difference of Squares ................................................................. 12
ESD Caution .................................................................................. 5 Additional Information ............................................................. 12
Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 13
Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 13
REVISION HISTORY
9/15—Rev. D to Rev. E
Deleted E-20-1 Package ................................................ Throughout
Changes to Guaranteed Performance Over Temperature Section ... 1
Deleted Figure 4; Renumbered Sequentially................................. 6
Deleted Table 4; Renumbered Sequentially .................................. 7
Changes to Figure 14, Figure 15, and Figure 16 ......................... 11
Changes to Figure 17 and Figure 18 ............................................. 12
Added Additional Information Section....................................... 12
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 14
2/11—Rev. C to Rev. D
Updated Format .................................................................. Universal
Added Pin Configuration and Function Descriptions Section .. 6
Added Typical Performance Characteristics Section .................. 8
Changes to Figure 11 ........................................................................ 8
Changes to Figure 12 and Figure 13 ............................................... 9
Changes to Ordering Guide .......................................................... 15
Rev. E | Page 2 of 14
Data Sheet AD532
SPECIFICATIONS
At 25°C, VS = ±15 V, R ≥ 2 kΩ VOS grounded, unless otherwise noted.
Table 1.
AD532J AD532K AD532S
Model Test Conditions Min Typ Max Min Typ Max Min Typ Max Unit
MULTIPLIER PERFORMANCE
Transfer Function ( X 1 X 2 ) (Y1 Y2 ) ( X 1 X 2 ) (Y1 Y2 ) ( X 1 X 2 ) (Y1 Y2 )
10 V 10 V 10 V
Total Error −10 V ≤ X, Y ≤ +10 V ±1.5 ±2.0 ±0.7 ±1.0 ±0.5 ±1.0 %
TA = Minimum to Maximum ±2.5 ±1.5 ±4.0 %
Total Error vs. Temperature ±0.04 ±0.03 ±0.01 ±0.04 %/°C
Supply Rejection ±15 V ±10% ±0.05 ±0.05 ±0.05 %/%
Nonlinearity, X X = 20 V p-p, Y = 10 V ± 0.8 ±0.5 ±0.5 %
Nonlinearity, Y Y = 20 V p-p, X = 10 V ±0.3 ±0.2 ±0.2 %
Feedthrough, X Y nulled, X = 20 V p-p 50 Hz 50 200 30 100 30 100 mV
Rev. E | Page 3 of 14
AD532 Data Sheet
AD532J AD532K AD532S
Model Test Conditions Min Typ Max Min Typ Max Min Typ Max Unit
SQUARE PERFORMANCE ( X1 X 2 )2
( X1 X 2 )
2
( X1 X 2 ) 2
10 V 10 V 10 V
Transfer Function
Total Error ±0.8 ±0.4 ±0.4 %
SQUARE ROOTER
PERFORMANCE
Transfer Function
10 V Z 10 V Z 10 V Z
Total Error 0 V ≤ VZ ≤ 10 V ±1.5 ±1.0 ±1.0 %
POWER SUPPLY
SPECIFICATIONS
Supply Voltage
Rated Performance ±15 ±15 ±15 V
Operating ±10 ±18 ±10 ±18 ±10 ±22 V
Supply Current
Quiescent 4 6 4 6 4 6 mA
Rev. E | Page 4 of 14
Data Sheet AD532
THERMAL RESISTANCE
θJA is specified for the worst case conditions, that is, a device CHIP DIMENSIONS AND BONDING DIAGRAM
soldered in a circuit board for surface-mount packages.
Contact factory for the latest dimensions. Dimensions are
Table 2. Thermal Resistance shown in inches and (millimeters).
Package Type θJA θJC Unit 0.107
(2.718)
H-10A 150 25 °C/W –VS OUTPUT
D-14 85 22 °C/W
Z
X1
0.062
(1.575)
+VS
Y1
00502-002
X2 GND VOS Y2
Figure 2.
ESD CAUTION
Rev. E | Page 5 of 14
AD532 Data Sheet
00502-105
X1
00502-103
OUT NC = NO CONNECT.
DO NOT CONNECT TO THIS PIN.
–VS
Figure 3. 10-Lead Header Pin Configuration (H-10) Figure 4. 14-Lead Side Brazed DIP (D-14)
Rev. E | Page 6 of 14
Data Sheet AD532
60
Y COMMON-MODE REJ
(X1 – X2) = +10V
50
DISTORTION (%)
XIN
CMRR (dB)
YIN 40
X COMMON-MODE REJ
0.1 (Y1 – Y2) = +10V
30
20
10
0.01 0
00502-005
00502-008
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 100 1k 10k 100k 1M 10M
PEAK SIGNAL AMPLITUDE (V) FREQUENCY (Hz)
Figure 5. Distortion vs. Peak Signal Amplitude Figure 8. CMRR vs. Frequency
100 1
20V p-p SIGNAL
RL = 2kΩ, CL = 1000pF
10 AMPLITUDE (V)
DISTORTION (%)
RL = 2kΩ, CL = 0pF
0.1
1
XIN
YIN
0.1 0.01
00502-006
00502-009
10 100 1k 10k 100k 1M 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)
Y FEEDTHROUGH
FEEDTHROUGH (mV)
100
AMPLITUDE (V)
VX = 10V
10 X FEEDTHROUGH
VX = 1V
VX = 5V
1 0.1
00502-007
00502-010
Rev. E | Page 7 of 14
AD532 Data Sheet
14 5
12 4
PEAK SIGNAL VOLTAGE (±V)
SATURATED OUTPUT
MAX X OR Y INPUT
FOR 1% LINEARITY
8 2
6 1
4 0
00502-011
00502-012
10 12 14 16 18 20 22 10 100 1k 10k 100k
POWER SUPPLY VOLTAGE (V) FREQUENCY (Hz)
Figure 11. Signal Swing vs. Supply Figure 12. Spot Noise vs. Frequency
Rev. E | Page 8 of 14
Data Sheet AD532
FUNCTIONAL DESCRIPTION
The functional block diagram for the AD532 is shown in Figure 1 The product of the two inputs is resolved in the multiplier cell
and the complete schematic in Figure 13. In the multiplying and using Gilbert’s linearized transconductance technique. The cell
squaring modes, Z is connected to the output to close the feedback is laser trimmed to obtain VOUT = (X1 − X2)(Y1 − Y2)/10 V. The
around the output op amp. In the divide mode, it is used as an built in op amp is used to obtain low output impedance and make
input terminal. possible self contained operation. The residual output voltage offset
The X and Y inputs are fed to high impedance differential can be zeroed at VOS in critical applications. Otherwise, the VOS pin
amplifiers featuring low distortion and good common-mode should be grounded.
rejection. The amplifier voltage offsets are actively laser trimmed to
zero during production.
X2
+VS
R2 R6 R8 R16 R23
R27
Z
Q1 Q2 C1
R20 Q25
R34
R22
R9 VOS
Y1 Q9 Q10
R1 R30
X1 Q3 Q4 R13 R21 R31
R3 Q22 Q26
R28
COM
Q23 OUTPUT
R10 Q18
R29
Q5 Q6 Q11 Q12
Q24 Q27
R19
R32 R11 Q20
R14 Q19
Q28 Q13
R4 R5 R12
R15 R24 R25 R26
00502-004
–VS CAN
R18
Y2
Rev. E | Page 9 of 14
AD532 Data Sheet
Rev. E | Page 10 of 14
Data Sheet AD532
APPLICATIONS
The performance and ease of use of the AD532 is achieved through Squaring
the laser trimming of thin film resistors deposited directly on
X1 Z
the monolithic chip. This trimming on the chip technique provides
X2
a number of significant advantages in terms of cost, reliability, AD532 OUT VOUT
Y1
and flexibility over conventional in package trimming of off the VIN2
Y2 +VS VOS –VS VOUT =
10V
chip resistors mounted or deposited on a hybrid substrate.
VIN (OPTIONAL)
Trimming on the chip eliminates the need for a hybrid substrate 20kΩ
00502-014
and the additional bonding wires that are required between the +VS –VS
resistors and the multiplier chip. By trimming more appropriate Figure 15. Squarer Connection
resistors on the AD532 chip itself, the second input terminals The squaring circuit in Figure 15 is a simple variation of the
that were committed to external trimming networks have been multiplier. The differential input capability of the AD532, however,
freed to allow fully differential operation at both the X and Y can obtain a positive or negative output response to the input, a
inputs. Further, the requirement for an input attenuator to useful feature for control applications, as it might eliminate the
adjust the gain at the Y input has been eliminated, letting the need for an additional inverter somewhere else.
user take full advantage of the high input impedance properties
of the input differential amplifiers. Therefore, the AD532 offers Division
Z
greater flexibility for both algebraic computation and transducer 10VZ
X X1 Z VOUT =
instrumentation applications. X
X2
Provision for fine trimming the output voltage offset has been AD532 OUT VOUT
Y1
included. This connection is optional, however, as the AD532 has Y2 +VS –VS
been factory trimmed for total performance as described in the 1kΩ
(SF)
listed specifications. 47kΩ
2.2kΩ 10kΩ
20kΩ
REPLACING OTHER IC MULTIPLIERS
00502-015
(X0)
+VS –VS
Existing designs using IC multipliers that require external
Figure 16. Divider Connection
trimming networks can be simplified using the pin for pin
replaceability of the AD532 by merely grounding the X2, Y2, The AD532 can be configured as a two-quadrant divider by
and VOS terminals. The VOS terminal must always be grounded connecting the multiplier cell in the feedback loop of the op
when unused. amp and using the Z terminal as a signal input, as shown in
Figure 16. It should be noted, however, that the output error is
Multiplication
given approximately by 10 V εm/(X1 − X2), where εm is the total
X1 Z error specification for the multiply mode and bandwidth by fm ×
X2 (X1 − X2)/10 V, where fm is the bandwidth of the multiplier.
AD532 OUT VOUT
Y1 Further, to avoid positive feedback, the X input is restricted to
Y2 VOS
(X1 – X2) (Y1 – Y2) negative values. Thus, for single-ended negative inputs (0 V to
VOUT =
(OPTIONAL) 10V −10 V), connect the input to X and the offset null to X2; for single-
20kΩ
00502-013
Rev. E | Page 11 of 14
AD532 Data Sheet
Table 5. Adjustment Procedure (Divider or Square Rooter) DIFFERENCE OF SQUARES
Divider Square Rooter
X X1 Z
With: Adjust for: With: Adjust for: X2
Adjust X Z VOUT Z VOUT AD532 OUT VOUT
Y1
20kΩ 20kΩ X2 – Y 2
Scale −10 V +10 V −10 V +10 V −10 V Y Y2 +VS VOS –VS VOUT =
Factor –Y 10V
00502-017
AD741KH
+VS –VS
The optional scale factor and offset adjustments listed in Table 5
Figure 18. Differential of Squares Connection
may be interactive. Repeat until satisfactory results are obtained.
The differential input capability of the AD532 allows for the
SQUARE ROOT algebraic solution of several interesting functions, such as the
Z
difference of squares, X2 − Y2/10 V. As shown in Figure 18, the
X1 Z VOUT = 10VZ
AD532 is configured in the square mode, with a simple unity
X2
AD532 OUT VOUT gain inverter connected between one of the signal inputs (Y)
Y1
Y2 +VS –VS
and one of the inverting input terminals (−YIN) of the multiplier.
1kΩ The inverter should use precision (0.1%) resistors or be otherwise
(SF)
trimmed for unity gain for best accuracy.
47kΩ
2.2kΩ 10kΩ
20kΩ ADDITIONAL INFORMATION
00502-016
(X0)
+VS –VS
For additional information about the applications for the AD532,
Figure 17. Square Rooter Connection refer to the Multiplier Application Guide.
The connections for square root mode are shown in Figure 17.
Similar to the divide mode, the multiplier cell is connected in
the feedback of the op amp by connecting the output back to
both the X and Y inputs. The diode D1 is connected as shown to
prevent latch-up as ZIN approaches 0 V. In this case, the VOS
adjustment is made with ZIN = +0.1 V dc, adjusting VOS to obtain
−1.0 V dc in the output, VOUT = 10 V Z . For optimum
performance, gain (SF) and offset (X0) adjustments are
recommended as shown and explained in Table 5.
Rev. E | Page 12 of 14
Data Sheet AD532
OUTLINE DIMENSIONS
0.005 (0.13) MIN 0.080 (2.03) MAX
14 8
0.310 (7.87)
1 0.220 (5.59)
7
PIN 1
0.100 (2.54)
BSC 0.320 (8.13)
0.765 (19.43) MAX 0.290 (7.37)
0.200 (5.08) 0.060 (1.52)
MAX 0.015 (0.38)
0.150
(3.81)
0.200 (5.08) MIN
0.125 (3.18) SEATING 0.015 (0.38)
0.070 (1.78) 0.008 (0.20)
PLANE
0.023 (0.58) 0.030 (0.76)
0.014 (0.36)
01-19-2015-A
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
AD532JCHIPS 0°C to 70°C Chip
AD532JDZ 0°C to 70°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD532JHZ 0°C to 70°C 10-Pin Metal Header Package [TO-100] H-10
AD532KDZ 0°C to 70°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD532KHZ 0°C to 70°C 10-Pin Metal Header Package [TO-100] H-10
AD532SCHIPS −55°C to +125°C Chip
AD532SD −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD532SD/883B −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD532SH −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD532SH/883B −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
1
Z = RoHS Compliant Part.
Rev. E | Page 13 of 14
AD532 Data Sheet
NOTES
Rev. E | Page 14 of 14